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DSP_Simulation/simulation/Release/chesswork/signal_path-6fcf7f.sfg
2026-01-15 13:06:36 +01:00

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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! int sig_init_delay(SingleSignalPath *, int)
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
frm : ( );
}
****
!! int sig_init_buffer(BufferPtr *, int *, int, int)
F_Z15sig_init_bufferP9BufferPtrPiii : user_defined, called {
fnm : "sig_init_buffer" 'int sig_init_buffer(BufferPtr *, int *, int, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
***/
[
0 : _Z14sig_init_delayP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
29 : __vola typ=uint20_ bnd=b stl=PM
32 : __extDM typ=int8_ bnd=b stl=DM
33 : __extPM typ=uint20_ bnd=b stl=PM
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
38 : __extDM_SingleSignalPath__delay_buffer typ=int8_ bnd=b stl=DM
39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
40 : __extDM_void typ=int8_ bnd=b stl=DM
41 : __extPM_void typ=uint20_ bnd=b stl=PM
42 : __rd___sp typ=dmaddr_ bnd=m
43 : __ct_0 typ=uint1_ val=0f bnd=m
44 : __la typ=dmaddr_ bnd=p tref=dmaddr___
45 : __rt typ=int32_ bnd=p tref=__sint__
46 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
47 : n_delay typ=int32_ bnd=p tref=__sint__
53 : __tmp typ=dmaddr_ bnd=m
56 : __tmp typ=dmaddr_ bnd=m
57 : __ct_16 typ=int32_ val=16f bnd=m
58 : __ct typ=int32_ bnd=m
59 : _Z15sig_init_bufferP9BufferPtrPiii typ=dmaddr_ val=0r bnd=m
62 : __tmp typ=int32_ bnd=m
76 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
99 : __ct_0S0 typ=int18_ val=0S0 bnd=m
100 : __ct_116 typ=int18_ val=116f bnd=m
103 : __ct_0s0 typ=int18_ val=0s0 bnd=m
105 : __ct_64 typ=int18_ val=64f bnd=m
]
F_Z14sig_init_delayP16SingleSignalPathi {
#142 off=0
(__R_SP.24 var=26) st_def () <48>;
(__vola.27 var=29) source () <51>;
(__extDM.30 var=32) source () <54>;
(__extPM.31 var=33) source () <55>;
(__sp.32 var=34) source () <56>;
(__extDM_SingleSignalPath.33 var=35) source () <57>;
(__extDM_SingleSignalPath_delay_buffer.34 var=36) source () <58>;
(__extDM_BufferPtr.35 var=37) source () <59>;
(__extDM_SingleSignalPath__delay_buffer.36 var=38) source () <60>;
(__extDM_int32_.37 var=39) source () <61>;
(__extDM_void.38 var=40) source () <62>;
(__extPM_void.39 var=41) source () <63>;
(__ct_0.41 var=43) const () <65>;
(__la.43 var=44 stl=LR off=0) inp () <67>;
(__la.44 var=44) deassign (__la.43) <68>;
(signal.47 var=46 stl=A off=0) inp () <71>;
(signal.48 var=46) deassign (signal.47) <72>;
(n_delay.50 var=47 stl=RA off=1) inp () <74>;
(n_delay.51 var=47) deassign (n_delay.50) <75>;
(__rd___sp.53 var=42) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.132 __sp.32) <81>;
(__ct_16.68 var=57) const () <92>;
(_Z15sig_init_bufferP9BufferPtrPiii.71 var=59) const () <95>;
(__rd___sp.88 var=42) rd_res_reg (__R_SP.24 __sp.58) <102>;
(__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.176 __sp.58) <106>;
(__rt.132 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.211) <192>;
(__rt.154 var=76) __Pvoid__pl___Pvoid_int18_ (signal.48 __ct_116.212) <220>;
(__rt.176 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.215) <248>;
(__rt.198 var=76) __Pvoid__mi___Pvoid_int18_ (__rt.154 __ct_64.217) <276>;
(__ct_0S0.211 var=99) const () <303>;
(__ct_116.212 var=100) const () <305>;
(__ct_0s0.215 var=103) const () <311>;
(__ct_64.217 var=105) const () <315>;
() void_jump_dmaddr_ (_Z15sig_init_bufferP9BufferPtrPiii.71) <339>;
call {
(__tmp.62 var=53 stl=A off=0) assign (__rt.154) <86>;
(__tmp.66 var=56 stl=A off=1) assign (__rt.198) <90>;
(n_delay.67 var=47 stl=RA off=1) assign (n_delay.51) <91>;
(__ct.70 var=58 stl=RB off=0) assign (__ct_16.68) <94>;
(__la.74 var=44 stl=LR off=0) assign (__la.44) <98>;
(__tmp.75 var=62 stl=RA off=0 __extDM.78 var=32 __extDM_BufferPtr.79 var=37 __extDM_SingleSignalPath.80 var=35 __extDM_SingleSignalPath__delay_buffer.81 var=38 __extDM_SingleSignalPath_delay_buffer.82 var=36 __extDM_int32_.83 var=39 __extDM_void.84 var=40 __extPM.85 var=33 __extPM_void.86 var=41 __vola.87 var=29) F_Z15sig_init_bufferP9BufferPtrPiii (__la.74 __tmp.62 __tmp.66 n_delay.67 __ct.70 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath__delay_buffer.36 __extDM_SingleSignalPath_delay_buffer.34 __extDM_int32_.37 __extDM_void.38 __extPM.31 __extPM_void.39 __vola.27) <99>;
(__tmp.76 var=62) deassign (__tmp.75) <100>;
} #4 off=1
#6 off=2 nxt=-2
(__rt.94 var=45 stl=RA off=0) assign (__tmp.76) <108>;
() out (__rt.94) <109>;
() sink (__vola.87) <110>;
() sink (__extDM.78) <113>;
() sink (__extPM.85) <114>;
() sink (__sp.93) <115>;
() sink (__extDM_SingleSignalPath.80) <116>;
() sink (__extDM_SingleSignalPath_delay_buffer.82) <117>;
() sink (__extDM_BufferPtr.79) <118>;
() sink (__extDM_SingleSignalPath__delay_buffer.81) <119>;
() sink (__extDM_int32_.83) <120>;
() sink (__extDM_void.84) <121>;
() sink (__extPM_void.86) <122>;
() sink (__ct_0.41) <123>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,152:0,0);
4 : (0,153:11,1);
6 : (0,153:4,1);
142 : (0,153:4,1);
----------
77 : (0,152:4,0);
81 : (0,152:4,0);
86 : (0,153:34,0);
90 : (0,153:56,0);
91 : (0,153:73,0);
92 : (0,153:82,0);
94 : (0,153:82,0);
98 : (0,153:11,0);
99 : (0,153:11,1);
102 : (0,153:4,0);
106 : (0,153:4,1);
108 : (0,153:26,0);
192 : (0,152:4,0);
220 : (0,153:34,1);
248 : (0,153:4,0);
276 : (0,153:56,0);
303 : (0,152:4,0);
305 : (0,153:34,0);
311 : (0,153:4,0);
315 : (0,153:56,0);
339 : (0,153:11,1);