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Calc-Funktion weiter, unnötige Funktionen auskommentiert (kompiliert)

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This commit is contained in:
Patrick Hangl
2026-02-02 16:12:41 +01:00
parent fa787bec48
commit f6fa0ed021
85 changed files with 16931 additions and 12836 deletions
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4
simulation/Release/chesswork/main-9f2435.#
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@@ -1,8 +1,8 @@
466ba9a29dd6732e5048de41303e492793f3e524
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
6a7c0bd95aec01b6196443462b0bfaac2fdb71b7
b2c950574d0ce15bee5baf4ae26b6b2a6b0cde52
da39a3ee5e6b4b0d3255bfef95601890afd80709
3bd5322a9dbb239e10fcf3ab8e3860e4e55187f2
6c3ad4e45b3a251a078236ee385f3021dffdd8c8
28
0

BIN
simulation/Release/chesswork/main-9f2435.o
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301
simulation/Release/chesswork/main-9f2435.sfg
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -14,9 +14,9 @@ F_main : user_defined, called {
frm : ( l=88 b=8 );
}
****
!! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
!! void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "initialize_signal" 'void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
@@ -45,9 +45,9 @@ Ffscanf : user_defined, called, varargs {
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
!! void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calculate_output" 'void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );
@@ -135,20 +135,19 @@ Ffclose : user_defined, called {
103 : fp1 typ=dmaddr_ bnd=m tref=__PFILE__
104 : fp2 typ=dmaddr_ bnd=m tref=__PFILE__
105 : fp3 typ=dmaddr_ bnd=m tref=__PFILE__
110 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m
110 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
112 : __ct_0 typ=int32_ val=0f bnd=m
115 : __ct_0 typ=uint40_ val=0f bnd=m
160 : __ct_2 typ=int32_ val=2f bnd=m
161 : __ct typ=int32_ bnd=m
163 : __ct typ=int32_ bnd=m
164 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m
165 : __ct typ=int64_ bnd=m
167 : __ct typ=int64_ bnd=m
168 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m
169 : __ct typ=int64_ bnd=m
170 : __ct_64 typ=int32_ val=64f bnd=m
171 : __ct typ=int32_ bnd=m
172 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
172 : _Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
174 : __link typ=dmaddr_ bnd=m
175 : fopen typ=dmaddr_ val=0r bnd=m
177 : __link typ=dmaddr_ bnd=m
@@ -175,7 +174,7 @@ Ffclose : user_defined, called {
225 : __tmp typ=int16_ bnd=m
241 : __tmp typ=dmaddr_ bnd=m
244 : __tmp typ=dmaddr_ bnd=m
245 : _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=dmaddr_ val=0r bnd=m
245 : _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=dmaddr_ val=0r bnd=m
247 : __link typ=dmaddr_ bnd=m
257 : __fch__ZL11output_port typ=int16_ bnd=m
258 : __fch__ZL11output_port typ=int32_ bnd=m
@@ -224,7 +223,7 @@ Ffclose : user_defined, called {
457 : __trgt typ=int10_ val=0j bnd=m
]
F_main {
#368 off=0
#366 off=0
(__M_SDMB.6 var=8) st_def () <12>;
(__M_WDMA.9 var=11) st_def () <18>;
(__R_SP.24 var=26) st_def () <48>;
@@ -256,46 +255,45 @@ F_main {
(__rd___sp.87 var=58) rd_res_reg (__R_SP.24 __sp.32) <111>;
(__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.1692 __sp.32) <115>;
(__rd___sp.93 var=58) rd_res_reg (__R_SP.24 __sp.92) <117>;
(__ct_4604930618986332160.120 var=110) const () <144>;
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_4604930618986332160.120 __rt.1714 b0.33) <149>;
(__ct_4607182418800017408.120 var=110) const () <144>;
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_4607182418800017408.120 __rt.1714 b0.33) <149>;
(__ct_0.127 var=115) const () <150>;
(__M_LDMA.132 var=14 b0.133 var=35) store (__ct_0.127 __rt.1878 b0.126) <155>;
(__M_LDMA.139 var=14 b0.140 var=35) store (__ct_0.127 __rt.1900 b0.133) <161>;
(__M_LDMA.146 var=14 b0.147 var=35) store (__ct_0.127 __rt.1922 b0.140) <167>;
(__M_LDMA.153 var=14 b0.154 var=35) store (__ct_0.127 __rt.1944 b0.147) <173>;
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_4604930618986332160.120 __rt.1736 b1.34) <179>;
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_4607182418800017408.120 __rt.1736 b1.34) <179>;
(__M_LDMA.167 var=14 b1.168 var=36) store (__ct_0.127 __rt.1966 b1.161) <185>;
(__M_LDMA.174 var=14 b1.175 var=36) store (__ct_0.127 __rt.1988 b1.168) <191>;
(__M_LDMA.181 var=14 b1.182 var=36) store (__ct_0.127 __rt.2010 b1.175) <197>;
(__M_LDMA.188 var=14 b1.189 var=36) store (__ct_0.127 __rt.2032 b1.182) <203>;
(__ct_2.194 var=160) const () <208>;
(__ct_4606281698874543309.200 var=164) const () <214>;
(__ct_4576918229304087675.206 var=168) const () <220>;
(__ct_64.209 var=170) const () <223>;
(_Z4initP16SingleSignalPathS0_PdS1_iidddi.212 var=172) const () <226>;
(__link.214 var=174) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.212) <228>;
(__rt.1692 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_m88S0.2045) <1439>;
(__rt.1714 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_0t0.2047) <1467>;
(__rt.1736 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_40t0.2048) <1495>;
(__rt.1878 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_8t0.2059) <1679>;
(__rt.1900 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_16t0.2062) <1707>;
(__rt.1922 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_24t0.2065) <1735>;
(__rt.1944 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_32t0.2068) <1763>;
(__rt.1966 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_48t0.2071) <1791>;
(__rt.1988 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_56t0.2074) <1819>;
(__rt.2010 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_64t0.2077) <1847>;
(__rt.2032 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_72t0.2080) <1875>;
(__ct_m88S0.2045 var=398) const () <1935>;
(__ct_0t0.2047 var=400) const () <1939>;
(__ct_40t0.2048 var=401) const () <1941>;
(__ct_8t0.2059 var=412) const () <1963>;
(__ct_16t0.2062 var=415) const () <1969>;
(__ct_24t0.2065 var=418) const () <1975>;
(__ct_32t0.2068 var=421) const () <1981>;
(__ct_48t0.2071 var=424) const () <1987>;
(__ct_56t0.2074 var=427) const () <1993>;
(__ct_64t0.2077 var=430) const () <1999>;
(__ct_72t0.2080 var=433) const () <2005>;
(_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi.212 var=172) const () <226>;
(__link.214 var=174) dmaddr__call_dmaddr_ (_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi.212) <228>;
(__rt.1692 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_m88S0.2045) <1436>;
(__rt.1714 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_0t0.2047) <1464>;
(__rt.1736 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_40t0.2048) <1492>;
(__rt.1878 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_8t0.2059) <1676>;
(__rt.1900 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_16t0.2062) <1704>;
(__rt.1922 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_24t0.2065) <1732>;
(__rt.1944 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_32t0.2068) <1760>;
(__rt.1966 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_48t0.2071) <1788>;
(__rt.1988 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_56t0.2074) <1816>;
(__rt.2010 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_64t0.2077) <1844>;
(__rt.2032 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_72t0.2080) <1872>;
(__ct_m88S0.2045 var=398) const () <1931>;
(__ct_0t0.2047 var=400) const () <1935>;
(__ct_40t0.2048 var=401) const () <1937>;
(__ct_8t0.2059 var=412) const () <1959>;
(__ct_16t0.2062 var=415) const () <1965>;
(__ct_24t0.2065 var=418) const () <1971>;
(__ct_32t0.2068 var=421) const () <1977>;
(__ct_48t0.2071 var=424) const () <1983>;
(__ct_56t0.2074 var=427) const () <1989>;
(__ct_64t0.2077 var=430) const () <1995>;
(__ct_72t0.2080 var=433) const () <2001>;
call {
(__ptr_c_sensor_signal_t.190 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <204>;
(__ptr_acc_sensor_signal_t.191 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <205>;
@@ -303,12 +301,12 @@ F_main {
(__ptr_b1.193 var=91 stl=A off=3) assign (__rt.1736) <207>;
(__ct.196 var=161 stl=RA off=0) assign (__ct_2.194) <210>;
(__ct.199 var=163 stl=RA off=1) assign (__ct_2.194) <213>;
(__ct.202 var=165 stl=AX off=0) assign (__ct_4606281698874543309.200) <216>;
(__ct.205 var=167 stl=AX off=1) assign (__ct_4606281698874543309.200) <219>;
(__ct.202 var=165 stl=AX off=0) assign (__ct_4607182418800017408.120) <216>;
(__ct.205 var=167 stl=AX off=1) assign (__ct_4607182418800017408.120) <219>;
(__ct.208 var=169 stl=BX off=0) assign (__ct_4576918229304087675.206) <222>;
(__ct.211 var=171 stl=RB off=0) assign (__ct_64.209) <225>;
(__link.215 var=174 stl=LR off=0) assign (__link.214) <229>;
(_ZL10input_port.216 var=48 _ZL11output_port.217 var=50 _ZL17c_sensor_signal_t.218 var=37 _ZL19acc_sensor_signal_t.219 var=39 __extDM.220 var=32 __extDM_SingleSignalPath.221 var=38 __extDM_int16_.222 var=49 __extDM_int32_.223 var=57 __extDM_int64_.224 var=54 __extDM_int8_.225 var=55 __extDM_void.226 var=52 __extPM.227 var=33 __extPM_FILE.228 var=56 __extPM_void.229 var=53 b0.230 var=35 b1.231 var=36 __vola.232 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.215 __ptr_c_sensor_signal_t.190 __ptr_acc_sensor_signal_t.191 __ptr_b0.192 __ptr_b1.193 __ct.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 _ZL10input_port.46 _ZL11output_port.48 _ZL17c_sensor_signal_t.35 _ZL19acc_sensor_signal_t.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.55 __extDM_int64_.52 __extDM_int8_.53 __extDM_void.50 __extPM.31 __extPM_FILE.54 __extPM_void.51 b0.154 b1.189 __vola.27) <230>;
(_ZL10input_port.216 var=48 _ZL11output_port.217 var=50 _ZL17c_sensor_signal_t.218 var=37 _ZL19acc_sensor_signal_t.219 var=39 __extDM.220 var=32 __extDM_SingleSignalPath.221 var=38 __extDM_int16_.222 var=49 __extDM_int32_.223 var=57 __extDM_int64_.224 var=54 __extDM_int8_.225 var=55 __extDM_void.226 var=52 __extPM.227 var=33 __extPM_FILE.228 var=56 __extPM_void.229 var=53 b0.230 var=35 b1.231 var=36 __vola.232 var=29) F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi (__link.215 __ptr_c_sensor_signal_t.190 __ptr_acc_sensor_signal_t.191 __ptr_b0.192 __ptr_b1.193 __ct.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 _ZL10input_port.46 _ZL11output_port.48 _ZL17c_sensor_signal_t.35 _ZL19acc_sensor_signal_t.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.55 __extDM_int64_.52 __extDM_int8_.53 __extDM_void.50 __extPM.31 __extPM_FILE.54 __extPM_void.51 b0.154 b1.189 __vola.27) <230>;
} #4 off=1
#5 off=2
(__ptr___str45bf45e5.61 var=64) const () <85>;
@@ -352,19 +350,19 @@ F_main {
(__tmp.319 var=190 stl=RA off=0 _ZL10input_port.322 var=48 _ZL11output_port.323 var=50 _ZL17c_sensor_signal_t.324 var=37 _ZL19acc_sensor_signal_t.325 var=39 __extDM.326 var=32 __extDM_SingleSignalPath.327 var=38 __extDM_int16_.328 var=49 __extDM_int32_.329 var=57 __extDM_int64_.330 var=54 __extDM_int8_.331 var=55 __extDM_void.332 var=52 __extPM.333 var=33 __extPM_FILE.334 var=56 __extPM_void.335 var=53 b0.336 var=35 b1.337 var=36 __vola.338 var=29) Ffeof (__link.318 fp1.314 _ZL10input_port.297 _ZL11output_port.298 _ZL17c_sensor_signal_t.299 _ZL19acc_sensor_signal_t.300 __extDM.301 __extDM_SingleSignalPath.302 __extDM_int16_.303 __extDM_int32_.304 __extDM_int64_.305 __extDM_int8_.306 __extDM_void.307 __extPM.308 __extPM_FILE.309 __extPM_void.310 b0.311 b1.312 __vola.313) <266>;
(__tmp.320 var=190) deassign (__tmp.319) <267>;
} #12 off=9
#717 off=10
#715 off=10
(__ct_0.122 var=112) const () <146>;
(__tmp.2095 var=439) uint3__cmp_int72__int72_ (__tmp.320 __ct_0.122) <2030>;
(__tmp.2105 var=382) bool_nequal_uint3_ (__tmp.2095) <2088>;
(__trgt.2114 var=453) const () <2183>;
() void_jump_bool_int10_ (__tmp.2105 __trgt.2114) <2184>;
(__either.2115 var=452) undefined () <2185>;
(__tmp.2095 var=439) uint3__cmp_int72__int72_ (__tmp.320 __ct_0.122) <2026>;
(__tmp.2105 var=382) bool_nequal_uint3_ (__tmp.2095) <2083>;
(__trgt.2114 var=453) const () <2176>;
() void_jump_bool_int10_ (__tmp.2105 __trgt.2114) <2177>;
(__either.2115 var=452) undefined () <2178>;
if {
{
() if_expr (__either.2115) <325>;
} #15
{
(__true.2121 var=450) const () <2193>;
(__true.2121 var=450) const () <2186>;
} #16
{
#18 off=11
@@ -375,12 +373,12 @@ F_main {
(__tmp.402 var=199 stl=RA off=0 _ZL10input_port.405 var=48 _ZL11output_port.406 var=50 _ZL17c_sensor_signal_t.407 var=37 _ZL19acc_sensor_signal_t.408 var=39 __extDM.409 var=32 __extDM_SingleSignalPath.410 var=38 __extDM_int16_.411 var=49 __extDM_int32_.412 var=57 __extDM_int64_.413 var=54 __extDM_int8_.414 var=55 __extDM_void.415 var=52 __extPM.416 var=33 __extPM_FILE.417 var=56 __extPM_void.418 var=53 b0.419 var=35 b1.420 var=36 __vola.421 var=29) Ffeof (__link.401 fp2.397 _ZL10input_port.322 _ZL11output_port.323 _ZL17c_sensor_signal_t.324 _ZL19acc_sensor_signal_t.325 __extDM.326 __extDM_SingleSignalPath.327 __extDM_int16_.328 __extDM_int32_.329 __extDM_int64_.330 __extDM_int8_.331 __extDM_void.332 __extPM.333 __extPM_FILE.334 __extPM_void.335 b0.336 b1.337 __vola.338) <333>;
(__tmp.403 var=199) deassign (__tmp.402) <334>;
} #19 off=12
#711 off=13
(__tmp.2085 var=439) uint3__cmp_int72__int72_ (__tmp.403 __ct_0.122) <2014>;
(__tmp.2110 var=202) bool_nequal_uint3_ (__tmp.2085) <2136>;
(__trgt.2122 var=456) const () <2194>;
() void_jump_bool_int10_ (__tmp.2110 __trgt.2122) <2195>;
(__either.2123 var=452) undefined () <2196>;
#709 off=13
(__tmp.2085 var=439) uint3__cmp_int72__int72_ (__tmp.403 __ct_0.122) <2010>;
(__tmp.2110 var=202) bool_nequal_uint3_ (__tmp.2085) <2130>;
(__trgt.2122 var=456) const () <2187>;
() void_jump_bool_int10_ (__tmp.2110 __trgt.2122) <2188>;
(__either.2123 var=452) undefined () <2189>;
} #17
{
(__vola.426 var=29) merge (__vola.338 __vola.421) <340>;
@@ -400,35 +398,35 @@ F_main {
(__extDM_int8_.440 var=55) merge (__extDM_int8_.331 __extDM_int8_.414) <354>;
(__extPM_FILE.441 var=56) merge (__extPM_FILE.334 __extPM_FILE.417) <355>;
(__extDM_int32_.442 var=57) merge (__extDM_int32_.329 __extDM_int32_.412) <356>;
(__tmp.2111 var=203) merge (__true.2121 __either.2123) <2137>;
(__tmp.2111 var=203) merge (__true.2121 __either.2123) <2131>;
} #21
} #14
if {
{
() if_expr (__tmp.2111) <411>;
() chess_frequent_else () <412>;
() chess_rear_then () <2197>;
() chess_rear_then () <2190>;
} #24
{
(__trgt.2124 var=457) const () <2198>;
() void_jump_int10_ (__trgt.2124) <2199>;
(__trgt.2124 var=457) const () <2191>;
() void_jump_int10_ (__trgt.2124) <2192>;
} #72 off=30
{
#760 off=14
#758 off=14
(__ptr___str41232700.71 var=74) const () <95>;
(__ct_8388608.73 var=76) const () <97>;
(__ct_8388624.76 var=78) const () <100>;
(__ptr___str2eb09b76.79 var=80) const () <103>;
(fscanf.665 var=210) const () <583>;
(_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884 var=245) const () <709>;
(_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884 var=245) const () <709>;
(fprintf.1030 var=259) const () <837>;
(__rt.1758 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_80t0.2051) <1523>;
(__rt.1780 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_84t0.2054) <1551>;
(__ct_80t0.2051 var=404) const () <1947>;
(__ct_84t0.2054 var=407) const () <1953>;
(__ct_2.2057 var=410) const () <1959>;
(__trgt.2116 var=454) const () <2186>;
(__trgt.2119 var=455) const () <2190>;
(__rt.1758 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_80t0.2051) <1520>;
(__rt.1780 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_84t0.2054) <1548>;
(__ct_80t0.2051 var=404) const () <1943>;
(__ct_84t0.2054 var=407) const () <1949>;
(__ct_2.2057 var=410) const () <1955>;
(__trgt.2116 var=454) const () <2179>;
(__trgt.2119 var=455) const () <2183>;
do {
{
(__vola.497 var=29) entry (__vola.1325 __vola.426) <413>;
@@ -450,7 +448,7 @@ F_main {
(__extDM_int8_.523 var=55) entry (__extDM_int8_.1377 __extDM_int8_.440) <439>;
(__extPM_FILE.524 var=56) entry (__extPM_FILE.1379 __extPM_FILE.441) <440>;
(__extDM_int32_.525 var=57) entry (__extDM_int32_.1381 __extDM_int32_.442) <441>;
(__shv___ptr_input_port.1646 var=333) entry (__shv___ptr_input_port.1644 __ct_8388608.73) <1338>;
(__shv___ptr_input_port.1646 var=333) entry (__shv___ptr_input_port.1644 __ct_8388608.73) <1336>;
} #27
{
#36 off=15
@@ -471,16 +469,16 @@ F_main {
(__link.696 var=216 stl=LR off=0) assign (__link.695) <596>;
(__tmp.697 var=217 stl=RA off=0 _ZL10input_port.700 var=48 _ZL11output_port.701 var=50 _ZL17c_sensor_signal_t.702 var=37 _ZL19acc_sensor_signal_t.703 var=39 __extDM.704 var=32 __extDM_SingleSignalPath.705 var=38 __extDM_int16_.706 var=49 __extDM_int32_.707 var=57 __extDM_int64_.708 var=54 __extDM_int8_.709 var=55 __extDM_void.710 var=52 __extPM.711 var=33 __extPM_FILE.712 var=56 __extPM_void.713 var=53 b0.714 var=35 b1.715 var=36 d0.716 var=46 d1.717 var=47 __vola.718 var=29) VA1Ffscanf (__link.696 fp2.690 __ptr___str41232700.691 __ptr_d1.692 _ZL10input_port.672 _ZL11output_port.673 _ZL17c_sensor_signal_t.674 _ZL19acc_sensor_signal_t.675 __extDM.676 __extDM_SingleSignalPath.677 __extDM_int16_.678 __extDM_int32_.679 __extDM_int64_.680 __extDM_int8_.681 __extDM_void.682 __extPM.683 __extPM_FILE.684 __extPM_void.685 b0.686 b1.687 d0.688 d1.515 __vola.689) <597>;
} #39 off=18
#490 off=19
#488 off=19
(__fch_d0.719 var=218) load (__M_WDMA.9 __rt.1758 d0.716) <600>;
(__tmp.720 var=219) __sshort___sshort___sint (__fch_d0.719) <601>;
(__M_SDMB.725 var=8 _ZL10input_port.726 var=48 __vola.727 var=29) store (__tmp.720 __shv___ptr_input_port.1646 _ZL10input_port.700 __vola.718) <606>;
(__fch_d1.728 var=224) load (__M_WDMA.9 __rt.1780 d1.717) <607>;
(__tmp.729 var=225) __sshort___sshort___sint (__fch_d1.728) <608>;
(__M_SDMB.737 var=8 _ZL10input_port.738 var=48 __vola.739 var=29) store (__tmp.729 __rt.1834 _ZL10input_port.726 __vola.727) <616>;
(__link.886 var=247) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884) <711>;
(__rt.1834 var=357) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1646 __ct_2.2057) <1623>;
(__rt.1856 var=357) __Pvoid__mi___Pvoid_int18_ (__rt.1834 __ct_2.2057) <1651>;
(__link.886 var=247) dmaddr__call_dmaddr_ (_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884) <711>;
(__rt.1834 var=357) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1646 __ct_2.2057) <1620>;
(__rt.1856 var=357) __Pvoid__mi___Pvoid_int18_ (__rt.1834 __ct_2.2057) <1648>;
call {
(__ptr_c_sensor_signal_t.873 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <698>;
(__ptr_acc_sensor_signal_t.874 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <699>;
@@ -488,7 +486,7 @@ F_main {
(__tmp.882 var=244 stl=A off=5) assign (__rt.1834) <707>;
(__ptr_output_port.883 var=77 stl=__spill_WDMA off=0) assign (__ct_8388624.76) <708>;
(__link.887 var=247 stl=LR off=0) assign (__link.886) <712>;
(_ZL10input_port.888 var=48 _ZL11output_port.889 var=50 _ZL17c_sensor_signal_t.890 var=37 _ZL19acc_sensor_signal_t.891 var=39 __extDM.892 var=32 __extDM_SingleSignalPath.893 var=38 __extDM_int16_.894 var=49 __extDM_int32_.895 var=57 __extDM_int64_.896 var=54 __extDM_int8_.897 var=55 __extDM_void.898 var=52 __extPM.899 var=33 __extPM_FILE.900 var=56 __extPM_void.901 var=53 b0.902 var=35 b1.903 var=36 d0.904 var=46 d1.905 var=47 __vola.906 var=29) F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ (__link.887 __ptr_c_sensor_signal_t.873 __ptr_acc_sensor_signal_t.874 __tmp.878 __tmp.882 __ptr_output_port.883 _ZL10input_port.738 _ZL11output_port.701 _ZL17c_sensor_signal_t.702 _ZL19acc_sensor_signal_t.703 __extDM.704 __extDM_SingleSignalPath.705 __extDM_int16_.706 __extDM_int32_.707 __extDM_int64_.708 __extDM_int8_.709 __extDM_void.710 __extPM.711 __extPM_FILE.712 __extPM_void.713 b0.714 b1.715 d0.716 d1.717 __vola.739) <713>;
(_ZL10input_port.888 var=48 _ZL11output_port.889 var=50 _ZL17c_sensor_signal_t.890 var=37 _ZL19acc_sensor_signal_t.891 var=39 __extDM.892 var=32 __extDM_SingleSignalPath.893 var=38 __extDM_int16_.894 var=49 __extDM_int32_.895 var=57 __extDM_int64_.896 var=54 __extDM_int8_.897 var=55 __extDM_void.898 var=52 __extPM.899 var=33 __extPM_FILE.900 var=56 __extPM_void.901 var=53 b0.902 var=35 b1.903 var=36 d0.904 var=46 d1.905 var=47 __vola.906 var=29) F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ (__link.887 __ptr_c_sensor_signal_t.873 __ptr_acc_sensor_signal_t.874 __tmp.878 __tmp.882 __ptr_output_port.883 _ZL10input_port.738 _ZL11output_port.701 _ZL17c_sensor_signal_t.702 _ZL19acc_sensor_signal_t.703 __extDM.704 __extDM_SingleSignalPath.705 __extDM_int16_.706 __extDM_int32_.707 __extDM_int64_.708 __extDM_int8_.709 __extDM_void.710 __extPM.711 __extPM_FILE.712 __extPM_void.713 b0.714 b1.715 d0.716 d1.717 __vola.739) <713>;
} #45 off=20
#53 off=21
(__fch__ZL11output_port.1025 var=257 _ZL11output_port.1026 var=50 __vola.1027 var=29) load (__M_SDMB.6 __ct_8388624.76 _ZL11output_port.889 __vola.906) <834>;
@@ -508,17 +506,17 @@ F_main {
(__tmp.1194 var=272 stl=RA off=0 _ZL10input_port.1197 var=48 _ZL11output_port.1198 var=50 _ZL17c_sensor_signal_t.1199 var=37 _ZL19acc_sensor_signal_t.1200 var=39 __extDM.1201 var=32 __extDM_SingleSignalPath.1202 var=38 __extDM_int16_.1203 var=49 __extDM_int32_.1204 var=57 __extDM_int64_.1205 var=54 __extDM_int8_.1206 var=55 __extDM_void.1207 var=52 __extPM.1208 var=33 __extPM_FILE.1209 var=56 __extPM_void.1210 var=53 b0.1211 var=35 b1.1212 var=36 d0.1213 var=46 d1.1214 var=47 __vola.1215 var=29) Ffeof (__link.1193 fp1.1189 _ZL10input_port.1037 _ZL11output_port.1038 _ZL17c_sensor_signal_t.1039 _ZL19acc_sensor_signal_t.1040 __extDM.1041 __extDM_SingleSignalPath.1042 __extDM_int16_.1043 __extDM_int32_.1044 __extDM_int64_.1045 __extDM_int8_.1046 __extDM_void.1047 __extPM.1048 __extPM_FILE.1049 __extPM_void.1050 b0.1051 b1.1052 d0.1053 d1.1054 __vola.1055) <930>;
(__tmp.1195 var=272) deassign (__tmp.1194) <931>;
} #60 off=24
#722 off=25
(__tmp.2100 var=439) uint3__cmp_int72__int72_ (__tmp.1195 __ct_0.122) <2038>;
(__tmp.2106 var=382) bool_nequal_uint3_ (__tmp.2100) <2089>;
() void_jump_bool_int10_ (__tmp.2106 __trgt.2116) <2187>;
(__either.2117 var=452) undefined () <2188>;
#720 off=25
(__tmp.2100 var=439) uint3__cmp_int72__int72_ (__tmp.1195 __ct_0.122) <2034>;
(__tmp.2106 var=382) bool_nequal_uint3_ (__tmp.2100) <2084>;
() void_jump_bool_int10_ (__tmp.2106 __trgt.2116) <2180>;
(__either.2117 var=452) undefined () <2181>;
if {
{
() if_expr (__either.2117) <989>;
} #63
{
(__false.2118 var=451) const () <2189>;
(__false.2118 var=451) const () <2182>;
} #64
{
#66 off=26
@@ -529,11 +527,11 @@ F_main {
(__tmp.1279 var=281 stl=RA off=0 _ZL10input_port.1282 var=48 _ZL11output_port.1283 var=50 _ZL17c_sensor_signal_t.1284 var=37 _ZL19acc_sensor_signal_t.1285 var=39 __extDM.1286 var=32 __extDM_SingleSignalPath.1287 var=38 __extDM_int16_.1288 var=49 __extDM_int32_.1289 var=57 __extDM_int64_.1290 var=54 __extDM_int8_.1291 var=55 __extDM_void.1292 var=52 __extPM.1293 var=33 __extPM_FILE.1294 var=56 __extPM_void.1295 var=53 b0.1296 var=35 b1.1297 var=36 d0.1298 var=46 d1.1299 var=47 __vola.1300 var=29) Ffeof (__link.1278 fp2.1274 _ZL10input_port.1197 _ZL11output_port.1198 _ZL17c_sensor_signal_t.1199 _ZL19acc_sensor_signal_t.1200 __extDM.1201 __extDM_SingleSignalPath.1202 __extDM_int16_.1203 __extDM_int32_.1204 __extDM_int64_.1205 __extDM_int8_.1206 __extDM_void.1207 __extPM.1208 __extPM_FILE.1209 __extPM_void.1210 b0.1211 b1.1212 d0.1213 d1.1214 __vola.1215) <997>;
(__tmp.1280 var=281) deassign (__tmp.1279) <998>;
} #67 off=27
#714 off=28
(__tmp.2090 var=439) uint3__cmp_int72__int72_ (__tmp.1280 __ct_0.122) <2022>;
(__tmp.2091 var=284) bool_equal_uint3_ (__tmp.2090) <2023>;
() void_jump_bool_int10_ (__tmp.2091 __trgt.2119) <2191>;
(__either.2120 var=452) undefined () <2192>;
#712 off=28
(__tmp.2090 var=439) uint3__cmp_int72__int72_ (__tmp.1280 __ct_0.122) <2018>;
(__tmp.2091 var=284) bool_equal_uint3_ (__tmp.2090) <2019>;
() void_jump_bool_int10_ (__tmp.2091 __trgt.2119) <2184>;
(__either.2120 var=452) undefined () <2185>;
} #65
{
(__vola.1305 var=29) merge (__vola.1215 __vola.1300) <1004>;
@@ -555,7 +553,7 @@ F_main {
(__extDM_int8_.1321 var=55) merge (__extDM_int8_.1206 __extDM_int8_.1291) <1020>;
(__extPM_FILE.1322 var=56) merge (__extPM_FILE.1209 __extPM_FILE.1294) <1021>;
(__extDM_int32_.1323 var=57) merge (__extDM_int32_.1204 __extDM_int32_.1289) <1022>;
(__tmp.1604 var=285) merge (__false.2118 __either.2120) <1299>;
(__tmp.1604 var=285) merge (__false.2118 __either.2120) <1297>;
} #69
} #62
} #28
@@ -580,7 +578,7 @@ F_main {
(__extDM_int8_.1377 var=55 __extDM_int8_.1378 var=55) exit (__extDM_int8_.1321) <1051>;
(__extPM_FILE.1379 var=56 __extPM_FILE.1380 var=56) exit (__extPM_FILE.1322) <1052>;
(__extDM_int32_.1381 var=57 __extDM_int32_.1382 var=57) exit (__extDM_int32_.1323) <1053>;
(__shv___ptr_input_port.1644 var=333 __shv___ptr_input_port.1645 var=333) exit (__rt.1856) <1337>;
(__shv___ptr_input_port.1644 var=333 __shv___ptr_input_port.1645 var=333) exit (__rt.1856) <1335>;
} #71
} #26 rng=[1,65535]
} #25
@@ -650,8 +648,8 @@ F_main {
() sink (__extPM_FILE.1528) <1158>;
() sink (__extDM_int32_.1523) <1159>;
() sink (__ct_0.81) <1160>;
(__rt.1812 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_88s0.2046) <1595>;
(__ct_88s0.2046 var=399) const () <1937>;
(__rt.1812 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_88s0.2046) <1592>;
(__ct_88s0.2046 var=399) const () <1933>;
} #0
0 : 'main.c';
----------
@@ -696,12 +694,12 @@ F_main {
78 : (0,70:11,64);
79 : (0,70:4,64);
82 : (0,71:0,65);
368 : (0,37:4,14);
490 : (0,62:8,39);
711 : (0,55:4,21);
714 : (0,55:23,55);
717 : (0,55:4,19);
722 : (0,55:23,53);
366 : (0,37:4,14);
488 : (0,62:8,39);
709 : (0,55:4,21);
712 : (0,55:23,55);
715 : (0,55:4,19);
720 : (0,55:23,53);
----------
85 : (0,49:22,0);
87 : (0,49:71,0);
@@ -714,16 +712,16 @@ F_main {
144 : (0,31:18,0);
146 : (0,31:18,0);
149 : (0,31:18,1);
150 : (0,31:24,0);
155 : (0,31:24,2);
161 : (0,31:28,3);
167 : (0,31:32,4);
173 : (0,31:36,5);
150 : (0,31:22,0);
155 : (0,31:22,2);
161 : (0,31:26,3);
167 : (0,31:30,4);
173 : (0,31:34,5);
179 : (0,32:18,7);
185 : (0,32:24,8);
191 : (0,32:28,9);
197 : (0,32:32,10);
203 : (0,32:36,11);
185 : (0,32:22,8);
191 : (0,32:26,9);
197 : (0,32:30,10);
203 : (0,32:34,11);
204 : (0,38:8,0);
205 : (0,38:28,0);
206 : (0,39:8,0);
@@ -731,9 +729,8 @@ F_main {
208 : (0,41:8,0);
210 : (0,41:8,0);
213 : (0,42:8,0);
214 : (0,43:8,0);
216 : (0,43:8,0);
219 : (0,44:8,0);
216 : (0,38:8,0);
219 : (0,38:8,0);
220 : (0,45:8,0);
222 : (0,45:8,0);
223 : (0,46:8,0);
@@ -917,48 +914,48 @@ F_main {
1131 : (0,71:0,65);
1132 : (0,71:0,65);
1133 : (0,71:0,0);
1299 : (0,55:23,56);
1439 : (0,28:4,0);
1467 : (0,31:11,0);
1495 : (0,32:11,0);
1523 : (0,53:8,0);
1551 : (0,53:12,0);
1595 : (0,71:0,0);
1623 : (0,63:81,0);
1679 : (0,31:24,0);
1707 : (0,31:28,0);
1735 : (0,31:32,0);
1763 : (0,31:36,0);
1791 : (0,32:24,0);
1819 : (0,32:28,0);
1847 : (0,32:32,0);
1875 : (0,32:36,0);
1935 : (0,28:4,0);
1937 : (0,28:4,0);
1939 : (0,31:11,0);
1941 : (0,32:11,0);
1947 : (0,53:8,0);
1953 : (0,53:12,0);
1959 : (0,63:81,0);
1963 : (0,31:24,0);
1969 : (0,31:28,0);
1975 : (0,31:32,0);
1981 : (0,31:36,0);
1987 : (0,32:24,0);
1993 : (0,32:28,0);
1999 : (0,32:32,0);
2005 : (0,32:36,0);
2014 : (0,55:4,21);
2022 : (0,55:23,55);
2023 : (0,55:23,55);
2030 : (0,55:4,19);
2038 : (0,55:23,53);
2088 : (0,55:4,19);
2089 : (0,55:23,53);
2136 : (0,55:4,21);
2137 : (0,55:4,22);
2184 : (0,55:4,19);
2187 : (0,55:23,53);
2191 : (0,55:4,57);
2195 : (0,55:4,23);
1297 : (0,55:23,56);
1436 : (0,28:4,0);
1464 : (0,31:11,0);
1492 : (0,32:11,0);
1520 : (0,53:8,0);
1548 : (0,53:12,0);
1592 : (0,71:0,0);
1620 : (0,63:81,0);
1676 : (0,31:22,0);
1704 : (0,31:26,0);
1732 : (0,31:30,0);
1760 : (0,31:34,0);
1788 : (0,32:22,0);
1816 : (0,32:26,0);
1844 : (0,32:30,0);
1872 : (0,32:34,0);
1931 : (0,28:4,0);
1933 : (0,28:4,0);
1935 : (0,31:11,0);
1937 : (0,32:11,0);
1943 : (0,53:8,0);
1949 : (0,53:12,0);
1955 : (0,63:81,0);
1959 : (0,31:22,0);
1965 : (0,31:26,0);
1971 : (0,31:30,0);
1977 : (0,31:34,0);
1983 : (0,32:22,0);
1989 : (0,32:26,0);
1995 : (0,32:30,0);
2001 : (0,32:34,0);
2010 : (0,55:4,21);
2018 : (0,55:23,55);
2019 : (0,55:23,55);
2026 : (0,55:4,19);
2034 : (0,55:23,53);
2083 : (0,55:4,19);
2084 : (0,55:23,53);
2130 : (0,55:4,21);
2131 : (0,55:4,22);
2177 : (0,55:4,19);
2180 : (0,55:23,53);
2184 : (0,55:4,57);
2188 : (0,55:4,23);

2
simulation/Release/chesswork/main.ctt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

2
simulation/Release/chesswork/main.dti
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

14
simulation/Release/chesswork/main.fnm
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -12,18 +12,18 @@
: _main
: "main" global "main.c" 28 Ofile
(
_Z4initP16SingleSignalPathS0_PdS1_iidddi
_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi
fopen
feof
fscanf
_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
fprintf
fclose
)
""
: _Z4initP16SingleSignalPathS0_PdS1_iidddi
: "init" global "signal_processing\\include\\signal_path.h" 121 Ofile
: _Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi
: "initialize_signal" global "signal_processing\\include\\signal_path.h" 119 Ofile
(
)
@@ -46,8 +46,8 @@
)
""
: _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
: "calc" global "signal_processing\\include\\signal_path.h" 124 Ofile
: _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
: "calculate_output" global "signal_processing\\include\\signal_path.h" 122 Ofile
(
)

2
simulation/Release/chesswork/main.gvt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

2
simulation/Release/chesswork/main.ini
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

14
simulation/Release/chesswork/main.lib
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -56,17 +56,17 @@ Ffeof : user_defined, called {
llv : 0 0 0 0 0 ;
}
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
// void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "initialize_signal" 'void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
}
// void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
// void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calculate_output" 'void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );

2
simulation/Release/chesswork/main.tof
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

14
simulation/Release/chesswork/signal_path-153c75.# Normal file
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@@ -0,0 +1,14 @@
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
503ae4d73e93bb915986f701ba648e61d4fba522
da39a3ee5e6b4b0d3255bfef95601890afd80709
10c48845c23af1ea3697b85410ff32a41b00302e
206
0
0
0
0
0
0
0

BIN
simulation/Release/chesswork/signal_path-153c75.o Normal file
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Binary file not shown.

369
simulation/Release/chesswork/signal_path-153c75.sfg Normal file
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@@ -0,0 +1,369 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! void set_weight(SingleSignalPath *, double, int)
F_Z10set_weightP16SingleSignalPathdi : user_defined, called {
fnm : "set_weight" 'void set_weight(SingleSignalPath *, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] RA[0] );
vac : ( srIM[0] );
frm : ( );
}
****
!! extern double ff_pow(double, double)
Fff_pow : user_defined, called {
fnm : "ff_pow" 'double ff_pow(double, double)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int float64_eq(float64, float64)
F_Z10float64_eqyy : user_defined, called {
fnm : "float64_eq" 'int float64_eq(float64, float64)';
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
loc : ( LR[0] RA[0] AX[0] AX[1] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 int32_to_float64(int)
F_Z16int32_to_float64i : user_defined, called {
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
arg : ( dmaddr_:i int64_:r int32_:i );
loc : ( LR[0] AX[0] RA[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 float64_sub(float64, float64)
F_Z11float64_subyy : user_defined, called {
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! int float64_to_int32_round_to_zero(float64)
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
arg : ( dmaddr_:i int32_:r int64_:i );
loc : ( LR[0] RA[0] AX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 float64_mul(float64, float64)
F_Z11float64_mulyy : user_defined, called {
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
***/
[
0 : _Z10set_weightP16SingleSignalPathdi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___fdouble___sint__
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __extDM_SingleSignalPath_weight_actived typ=int8_ bnd=b stl=DM
38 : __extDM_SingleSignalPath_weight typ=int8_ bnd=b stl=DM
39 : __extDM_SingleSignalPath__weight_scale_nbits typ=int8_ bnd=b stl=DM
40 : __rd___sp typ=dmaddr_ bnd=m
41 : __ct_0 typ=uint1_ val=0f bnd=m
42 : __la typ=dmaddr_ bnd=p tref=dmaddr___
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
44 : weight typ=int64_ bnd=p tref=__fdouble__
45 : scale_nbits typ=int32_ bnd=p tref=__sint__
49 : __tmpb0_F_Z10set_weightP16SingleSignalPathdi typ=int64_ bnd=m lscp=181 tref=__fdouble__
50 : __tmpb2_F_Z10set_weightP16SingleSignalPathdi typ=int64_ bnd=m lscp=181 tref=__fdouble__
52 : scale typ=int32_ bnd=m lscp=181 tref=__sint__
53 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
56 : __ct_0 typ=int32_ val=0f bnd=m
61 : __ct_1 typ=int32_ val=1f bnd=m
67 : __ct_4611686018427387904 typ=int64_ val=4611686018427387904f bnd=m
72 : __tmp typ=int64_ bnd=m
74 : __tmp typ=int64_ bnd=m
75 : __tmp typ=int64_ bnd=m
76 : __tmp typ=int32_ bnd=m
96 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
117 : __tmp typ=int32_ bnd=m
126 : __ct_0S0 typ=int18_ val=0S0 bnd=m
127 : __ct_132 typ=int18_ val=132f bnd=m
130 : __ct_0s0 typ=int18_ val=0s0 bnd=m
131 : __ct_4 typ=int18_ val=4f bnd=m
135 : __tmp typ=bool bnd=m
142 : __a0 typ=int64_ bnd=m tref=__atp0___48
144 : ff_pow typ=dmaddr_ val=0r bnd=m
145 : __link typ=dmaddr_ bnd=m
162 : __a1 typ=int64_ bnd=m tref=__atp1___12
163 : _Z10float64_eqyy typ=dmaddr_ val=0r bnd=m
164 : __link typ=dmaddr_ bnd=m
170 : __tmp typ=uint3_ bnd=m
175 : _Z16int32_to_float64i typ=dmaddr_ val=0r bnd=m
176 : __link typ=dmaddr_ bnd=m
178 : __tmpb2_F_Z10set_weightP16SingleSignalPathdi typ=int64_ bnd=m
180 : __a1 typ=int64_ bnd=m tref=__atp1___9
181 : _Z11float64_subyy typ=dmaddr_ val=0r bnd=m
182 : __link typ=dmaddr_ bnd=m
184 : __tmp typ=int64_ bnd=m
186 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
187 : __link typ=dmaddr_ bnd=m
190 : __tmp typ=int64_ bnd=m
193 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
194 : __link typ=dmaddr_ bnd=m
196 : __tmp typ=int64_ bnd=m
206 : __either typ=bool bnd=m
207 : __trgt typ=int10_ val=0j bnd=m
208 : __trgt typ=int10_ val=0j bnd=m
]
F_Z10set_weightP16SingleSignalPathdi {
#272 off=0
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__extDM_SingleSignalPath_weight_actived.34 var=36) source () <58>;
(__extDM_SingleSignalPath_weight.36 var=38) source () <60>;
(__extDM_SingleSignalPath__weight_scale_nbits.37 var=39) source () <61>;
(__ct_0.39 var=41) const () <63>;
(__la.41 var=42 stl=LR off=0) inp () <65>;
(__la.42 var=42) deassign (__la.41) <66>;
(signal.44 var=43 stl=A off=0) inp () <68>;
(signal.45 var=43) deassign (signal.44) <69>;
(weight.47 var=44 stl=AX off=0) inp () <71>;
(weight.48 var=44) deassign (weight.47) <72>;
(scale_nbits.50 var=45 stl=RA off=0) inp () <74>;
(scale_nbits.51 var=45) deassign (scale_nbits.50) <75>;
(__rd___sp.53 var=40) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.177 __sp.32) <81>;
(__ct_4607182418800017408.63 var=53) const () <87>;
(__rt.177 var=96) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.284) <249>;
(__ct_0S0.284 var=126) const () <398>;
(_Z10float64_eqyy.329 var=163) const () <485>;
(__link.330 var=164) dmaddr__call_dmaddr_ (_Z10float64_eqyy.329) <486>;
call {
(weight.331 var=44 stl=AX off=0) assign (weight.48) <487>;
(__a1.332 var=162 stl=AX off=1) assign (__ct_4607182418800017408.63) <488>;
(__link.333 var=164 stl=LR off=0) assign (__link.330) <489>;
(__tmp.334 var=117 stl=RA off=0) F_Z10float64_eqyy (__link.333 weight.331 __a1.332) <490>;
(__tmp.335 var=117) deassign (__tmp.334) <491>;
} #273 off=1
#269 off=2
(__ct_0.85 var=56) const () <110>;
(__rt.205 var=96) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_132.285) <286>;
(__ct_132.285 var=127) const () <400>;
(__tmp.339 var=170) uint3__cmp_int72__int72_ (__tmp.335 __ct_0.85) <498>;
(__tmp.344 var=135) bool_nequal_uint3_ (__tmp.339) <518>;
(__trgt.403 var=207) const () <646>;
() void_jump_bool_int10_ (__tmp.344 __trgt.403) <647>;
(__either.404 var=206) undefined () <648>;
if {
{
() if_expr (__either.404) <109>;
} #5
{
(__M_WDMA.90 var=11 __extDM_SingleSignalPath_weight_actived.91 var=36) store (__ct_0.85 __rt.205 __extDM_SingleSignalPath_weight_actived.34) <115>;
} #6 off=18
{
#285 off=3
(__ct_1.92 var=61) const () <116>;
(__M_WDMA.97 var=11 __extDM_SingleSignalPath_weight_actived.98 var=36) store (__ct_1.92 __rt.205 __extDM_SingleSignalPath_weight_actived.34) <121>;
(__rt.249 var=96) __Pvoid__pl___Pvoid_int18_ (__rt.205 __ct_4.289) <342>;
(__ct_4.289 var=131) const () <408>;
(_Z16int32_to_float64i.346 var=175) const () <521>;
(__link.347 var=176) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.346) <522>;
call {
(scale_nbits.348 var=45 stl=RA off=0) assign (scale_nbits.51) <523>;
(__link.349 var=176 stl=LR off=0) assign (__link.347) <524>;
(__tmpb2_F_Z10set_weightP16SingleSignalPathdi.350 var=178 stl=AX off=0) F_Z16int32_to_float64i (__link.349 scale_nbits.348) <525>;
(__tmpb2_F_Z10set_weightP16SingleSignalPathdi.351 var=50) deassign (__tmpb2_F_Z10set_weightP16SingleSignalPathdi.350) <526>;
} #286 off=4
#282 off=5
(__ct_4611686018427387904.104 var=67) const () <127>;
(ff_pow.302 var=144) const () <440>;
(__link.303 var=145) dmaddr__call_dmaddr_ (ff_pow.302) <441>;
call {
(__a0.304 var=142 stl=AX off=1) assign (__ct_4611686018427387904.104) <442>;
(__tmpb2_F_Z10set_weightP16SingleSignalPathdi.305 var=50 stl=BX off=0) assign (__tmpb2_F_Z10set_weightP16SingleSignalPathdi.351) <443>;
(__link.306 var=145 stl=LR off=0) assign (__link.303) <444>;
(__tmpb0_F_Z10set_weightP16SingleSignalPathdi.307 var=49 stl=AX off=0) Fff_pow (__link.306 __a0.304 __tmpb2_F_Z10set_weightP16SingleSignalPathdi.305) <445>;
(__tmpb0_F_Z10set_weightP16SingleSignalPathdi.308 var=49) deassign (__tmpb0_F_Z10set_weightP16SingleSignalPathdi.307) <446>;
} #248 off=6
#299 off=7
(_Z11float64_subyy.355 var=181) const () <533>;
(__link.356 var=182) dmaddr__call_dmaddr_ (_Z11float64_subyy.355) <534>;
call {
(__tmpb0_F_Z10set_weightP16SingleSignalPathdi.357 var=49 stl=AX off=1) assign (__tmpb0_F_Z10set_weightP16SingleSignalPathdi.308) <535>;
(__a1.358 var=180 stl=BX off=0) assign (__ct_4607182418800017408.63) <536>;
(__link.359 var=182 stl=LR off=0) assign (__link.356) <537>;
(__tmp.360 var=184 stl=AX off=0) F_Z11float64_subyy (__link.359 __tmpb0_F_Z10set_weightP16SingleSignalPathdi.357 __a1.358) <538>;
(__tmp.361 var=72) deassign (__tmp.360) <539>;
} #300 off=8
#305 off=9
(_Z30float64_to_int32_round_to_zeroy.364 var=186) const () <545>;
(__link.365 var=187) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.364) <546>;
call {
(__tmp.366 var=72 stl=AX off=0) assign (__tmp.361) <547>;
(__link.367 var=187 stl=LR off=0) assign (__link.365) <548>;
(scale.368 var=52 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.367 __tmp.366) <549>;
(scale.369 var=52) deassign (scale.368) <550>;
} #306 off=10
#311 off=11
(__link.373 var=176) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.346) <557>;
call {
(scale.374 var=52 stl=RA off=0) assign (scale.369) <558>;
(__link.375 var=176 stl=LR off=0) assign (__link.373) <559>;
(__tmp.376 var=190 stl=AX off=0) F_Z16int32_to_float64i (__link.375 scale.374) <560>;
(__tmp.377 var=74) deassign (__tmp.376) <561>;
} #312 off=12
#317 off=13
(_Z11float64_mulyy.381 var=193) const () <568>;
(__link.382 var=194) dmaddr__call_dmaddr_ (_Z11float64_mulyy.381) <569>;
call {
(weight.383 var=44 stl=AX off=1) assign (weight.48) <570>;
(__tmp.384 var=74 stl=BX off=0) assign (__tmp.377) <571>;
(__link.385 var=194 stl=LR off=0) assign (__link.382) <572>;
(__tmp.386 var=196 stl=AX off=0) F_Z11float64_mulyy (__link.385 weight.383 __tmp.384) <573>;
(__tmp.387 var=75) deassign (__tmp.386) <574>;
} #318 off=14
#323 off=15
(__link.391 var=187) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.364) <581>;
call {
(__tmp.392 var=75 stl=AX off=0) assign (__tmp.387) <582>;
(__link.393 var=187 stl=LR off=0) assign (__link.391) <583>;
(__tmp.394 var=76 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.393 __tmp.392) <584>;
(__tmp.395 var=76) deassign (__tmp.394) <585>;
} #324 off=16
#296 off=17
(__M_WDMA.117 var=11 __extDM_SingleSignalPath_weight.118 var=38) store (__tmp.395 __rt.249 __extDM_SingleSignalPath_weight.36) <140>;
(__M_WDMA.122 var=11 __extDM_SingleSignalPath__weight_scale_nbits.123 var=39) store (scale_nbits.51 __rt.271 __extDM_SingleSignalPath__weight_scale_nbits.37) <144>;
(__rt.271 var=96) __Pvoid__pl___Pvoid_int18_ (__rt.249 __ct_4.289) <370>;
(__trgt.405 var=208) const () <649>;
() void_jump_int10_ (__trgt.405) <650>;
} #181
{
(__extDM_SingleSignalPath_weight_actived.124 var=36) merge (__extDM_SingleSignalPath_weight_actived.91 __extDM_SingleSignalPath_weight_actived.98) <145>;
(__extDM_SingleSignalPath_weight.125 var=38) merge (__extDM_SingleSignalPath_weight.36 __extDM_SingleSignalPath_weight.118) <146>;
(__extDM_SingleSignalPath__weight_scale_nbits.126 var=39) merge (__extDM_SingleSignalPath__weight_scale_nbits.37 __extDM_SingleSignalPath__weight_scale_nbits.123) <147>;
} #8
} #4
#10 off=19 nxt=-2
(__rd___sp.131 var=40) rd_res_reg (__R_SP.24 __sp.58) <152>;
(__R_SP.135 var=26 __sp.136 var=34) wr_res_reg (__rt.227 __sp.58) <156>;
() void_ret_dmaddr_ (__la.42) <157>;
() sink (__sp.136) <163>;
() sink (__extDM_SingleSignalPath_weight_actived.124) <165>;
() sink (__extDM_SingleSignalPath_weight.125) <167>;
() sink (__extDM_SingleSignalPath__weight_scale_nbits.126) <168>;
() sink (__ct_0.39) <169>;
(__rt.227 var=96) __Pvoid__pl___Pvoid_int18_ (__rd___sp.131 __ct_0s0.288) <314>;
(__ct_0s0.288 var=130) const () <406>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,206:0,0);
4 : (0,208:4,1);
6 : (0,208:22,2);
10 : (0,218:0,22);
181 : (0,216:14,18);
248 : (0,214:20,13);
269 : (0,208:15,1);
272 : (0,208:15,1);
273 : (0,208:15,1);
282 : (0,214:20,13);
285 : (0,214:25,10);
286 : (0,214:25,10);
296 : (0,216:14,18);
299 : (0,214:40,16);
300 : (0,214:40,16);
305 : (0,214:40,16);
306 : (0,214:40,16);
311 : (0,215:32,17);
312 : (0,215:32,17);
317 : (0,215:32,17);
318 : (0,215:32,17);
323 : (0,215:23,17);
324 : (0,215:23,17);
----------
77 : (0,206:5,0);
81 : (0,206:5,0);
87 : (0,208:18,0);
109 : (0,208:4,1);
110 : (0,209:33,0);
115 : (0,209:14,2);
116 : (0,213:33,0);
121 : (0,213:14,5);
127 : (0,214:20,0);
140 : (0,215:14,17);
144 : (0,216:14,18);
145 : (0,208:4,21);
146 : (0,208:4,21);
147 : (0,208:4,21);
152 : (0,218:0,0);
156 : (0,218:0,22);
157 : (0,218:0,22);
249 : (0,206:5,0);
286 : (0,209:14,2);
314 : (0,218:0,0);
342 : (0,215:14,0);
370 : (0,216:14,0);
398 : (0,206:5,0);
400 : (0,209:14,0);
406 : (0,218:0,0);
408 : (0,215:14,0);
440 : (0,214:20,0);
441 : (0,214:20,13);
442 : (0,214:20,13);
443 : (0,214:20,13);
444 : (0,214:20,13);
445 : (0,214:20,13);
446 : (0,214:20,13);
485 : (0,208:15,0);
486 : (0,208:15,1);
487 : (0,208:15,1);
488 : (0,208:15,1);
489 : (0,208:15,1);
490 : (0,208:15,1);
491 : (0,208:15,1);
498 : (0,208:15,1);
518 : (0,208:15,1);
521 : (0,214:25,0);
522 : (0,214:25,10);
523 : (0,214:25,10);
524 : (0,214:25,10);
525 : (0,214:25,10);
526 : (0,214:25,10);
533 : (0,214:40,0);
534 : (0,214:40,16);
535 : (0,214:40,16);
536 : (0,214:40,16);
537 : (0,214:40,16);
538 : (0,214:40,16);
539 : (0,214:40,16);
545 : (0,214:40,0);
546 : (0,214:40,16);
547 : (0,214:40,16);
548 : (0,214:40,16);
549 : (0,214:40,16);
550 : (0,214:40,16);
557 : (0,215:32,17);
558 : (0,215:32,17);
559 : (0,215:32,17);
560 : (0,215:32,17);
561 : (0,215:32,17);
568 : (0,215:32,0);
569 : (0,215:32,17);
570 : (0,215:32,17);
571 : (0,215:32,17);
572 : (0,215:32,17);
573 : (0,215:32,17);
574 : (0,215:32,17);
581 : (0,215:23,17);
582 : (0,215:23,17);
583 : (0,215:23,17);
584 : (0,215:23,17);
585 : (0,215:23,17);
647 : (0,208:4,1);

8
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "initialize_signal" 'void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
frm : ( b=8 );
}
****
!! void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
F_Z20scale_preemph_filterP16SingleSignalPathdddddi : user_defined, called {
fnm : "scale_preemph_filter" 'void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int set_delay(SingleSignalPath *, int)
F_Z9set_delayP16SingleSignalPathi : user_defined, called {
fnm : "set_delay" 'int set_delay(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! void set_weight(SingleSignalPath *, double, int)
F_Z10set_weightP16SingleSignalPathdi : user_defined, called {
fnm : "set_weight" 'void set_weight(SingleSignalPath *, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] RA[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int initialize_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii : user_defined, called {
fnm : "initialize_buffer_dmb" 'int initialize_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
loc : ( LR[0] RA[0] A[4] A[5] RA[1] RB[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int initialize_buffer(BufferPtr *, int *, int, int)
F_Z17initialize_bufferP9BufferPtrPiii : user_defined, called {
fnm : "initialize_buffer" 'int initialize_buffer(BufferPtr *, int *, int, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! float64 float64_mul(float64, float64)
F_Z11float64_mulyy : user_defined, called {
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! int float64_to_int32_round_to_zero(float64)
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
arg : ( dmaddr_:i int32_:r int64_:i );
loc : ( LR[0] RA[0] AX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
***/
[
0 : _Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___PSingleSignalPath___P__fdouble___P__fdouble___sint___sint___fdouble___fdouble___fdouble___sint__
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
29 : __vola typ=uint20_ bnd=b stl=PM
32 : __extDM typ=int8_ bnd=b stl=DM
33 : __extPM typ=uint20_ bnd=b stl=PM
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
37 : pointer_sample_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
38 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
39 : sample_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
40 : pointer_coefficient_line typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
41 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
42 : coefficient_line typ=int8_ bnd=e sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
43 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
44 : __extDM_int64_ typ=int8_ bnd=b stl=DM
45 : __extDM_void typ=int8_ bnd=b stl=DM
46 : __extPM_void typ=uint20_ bnd=b stl=PM
47 : pointer_sample_line_ptr_start typ=int8_ bnd=b stl=DM
48 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
49 : pointer_coefficient_line_ptr_start typ=int8_ bnd=b stl=DM
50 : __rd___sp typ=dmaddr_ bnd=m
52 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=35
53 : __ptr_pointer_sample_line typ=dmaddr_ bnd=m
54 : __ptr_pointer_sample_line typ=dmaddr_ val=0a bnd=m adro=37
55 : __ptr_sample_line typ=dmaddr_ bnd=m
56 : __ptr_sample_line typ=dmaddr_ val=0a bnd=m adro=39
57 : __ptr_pointer_coefficient_line typ=dmaddr_ bnd=m
58 : __ptr_pointer_coefficient_line typ=dmaddr_ val=0a bnd=m adro=40
59 : __ptr_coefficient_line typ=dmaddr_ bnd=m
60 : __ptr_coefficient_line typ=dmaddr_ val=0a bnd=m adro=42
61 : __ct_0 typ=uint1_ val=0f bnd=m
62 : __la typ=dmaddr_ bnd=p tref=dmaddr___
63 : c_sensor_signal_t typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
64 : acc_sensor_signal_t typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
65 : b_c typ=dmaddr_ bnd=p tref=__P__fdouble__
66 : b_acc typ=dmaddr_ bnd=p tref=__P__fdouble__
67 : delay_c typ=int32_ bnd=p tref=__sint__
68 : delay_acc typ=int32_ bnd=p tref=__sint__
69 : weight_c typ=int64_ bnd=p tref=__fdouble__
70 : weight_acc typ=int64_ bnd=p tref=__fdouble__
71 : lms_mu typ=int64_ bnd=p tref=__fdouble__
72 : number_coefficients typ=int32_ bnd=p tref=__sint__
78 : __ct_0 typ=int32_ val=0f bnd=m
81 : __fch___extDM_int64_ typ=int64_ bnd=m
85 : __fch___extDM_int64_ typ=int64_ bnd=m
89 : __fch___extDM_int64_ typ=int64_ bnd=m
93 : __fch___extDM_int64_ typ=int64_ bnd=m
97 : __fch___extDM_int64_ typ=int64_ bnd=m
98 : __ct_31 typ=int32_ val=31f bnd=m
99 : __ct typ=int32_ bnd=m
100 : _Z20scale_preemph_filterP16SingleSignalPathdddddi typ=dmaddr_ val=0r bnd=m
102 : __link typ=dmaddr_ bnd=m
103 : _Z9set_delayP16SingleSignalPathi typ=dmaddr_ val=0r bnd=m
105 : __link typ=dmaddr_ bnd=m
106 : __tmp typ=int32_ bnd=m
108 : __ct typ=int32_ bnd=m
109 : _Z10set_weightP16SingleSignalPathdi typ=dmaddr_ val=0r bnd=m
111 : __link typ=dmaddr_ bnd=m
115 : __fch___extDM_int64_ typ=int64_ bnd=m
119 : __fch___extDM_int64_ typ=int64_ bnd=m
123 : __fch___extDM_int64_ typ=int64_ bnd=m
127 : __fch___extDM_int64_ typ=int64_ bnd=m
131 : __fch___extDM_int64_ typ=int64_ bnd=m
133 : __ct typ=int32_ bnd=m
136 : __link typ=dmaddr_ bnd=m
139 : __link typ=dmaddr_ bnd=m
140 : __tmp typ=int32_ bnd=m
142 : __ct typ=int32_ bnd=m
145 : __link typ=dmaddr_ bnd=m
146 : __ct_4746794007244308480 typ=int64_ val=4746794007244308480f bnd=m
148 : __tmp typ=int64_ bnd=m
149 : __tmp typ=int32_ bnd=m
150 : __ct_64 typ=int32_ val=64f bnd=m
151 : __ct typ=int32_ bnd=m
152 : _Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii typ=dmaddr_ val=0r bnd=m
154 : __link typ=dmaddr_ bnd=m
155 : __tmp typ=int32_ bnd=m
157 : __ct typ=int32_ bnd=m
158 : _Z17initialize_bufferP9BufferPtrPiii typ=dmaddr_ val=0r bnd=m
160 : __link typ=dmaddr_ bnd=m
161 : __tmp typ=int32_ bnd=m
164 : __tmp typ=bool bnd=m
170 : __fch_pointer_sample_line_ptr_start typ=dmaddr_ bnd=m
180 : __fch_pointer_coefficient_line_ptr_start typ=dmaddr_ bnd=m
201 : __iv1_i typ=dmaddr_ bnd=m
202 : __iv2_i typ=dmaddr_ bnd=m
205 : __cv typ=uint16_ bnd=m
213 : __ptr_pointer_sample_line__a4 typ=dmaddr_ val=4a bnd=m adro=37
214 : __ptr_pointer_coefficient_line__a4 typ=dmaddr_ val=4a bnd=m adro=40
217 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
248 : __ct_0S0 typ=int18_ val=-8S0 bnd=m
249 : __ct_0s0 typ=int18_ val=8s0 bnd=m
250 : __ct_4 typ=int18_ val=4f bnd=m
251 : __ct_8 typ=int18_ val=8f bnd=m
262 : __tmp typ=uint3_ bnd=m
267 : __a1 typ=int64_ bnd=m tref=__atp1___10
268 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
269 : __link typ=dmaddr_ bnd=m
271 : __tmp typ=int64_ bnd=m
273 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
274 : __link typ=dmaddr_ bnd=m
285 : __either typ=bool bnd=m
286 : __trgt typ=int10_ val=0j bnd=m
287 : __trgt typ=int10_ val=0j bnd=m
288 : __trgt typ=uint16_ val=0j bnd=m
289 : __vcnt typ=uint16_ bnd=m
]
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
#276 off=0
(__M_WDMA.9 var=11) st_def () <18>;
(__M_WDMB.10 var=12) st_def () <20>;
(__M_LDMA.12 var=14) st_def () <24>;
(__R_SP.24 var=26) st_def () <48>;
(__vola.27 var=29) source () <51>;
(__extDM.30 var=32) source () <54>;
(__extPM.31 var=33) source () <55>;
(__sp.32 var=34) source () <56>;
(_ZL2mu.33 var=35) source () <57>;
(__extDM_int32_.34 var=36) source () <58>;
(pointer_sample_line.35 var=37) source () <59>;
(__extDM_BufferPtrDMB.36 var=38) source () <60>;
(sample_line.37 var=39) source () <61>;
(pointer_coefficient_line.38 var=40) source () <62>;
(__extDM_BufferPtr.39 var=41) source () <63>;
(coefficient_line.40 var=42) source () <64>;
(__extDM_SingleSignalPath.41 var=43) source () <65>;
(__extDM_int64_.42 var=44) source () <66>;
(__extDM_void.43 var=45) source () <67>;
(__extPM_void.44 var=46) source () <68>;
(pointer_sample_line_ptr_start.45 var=47) source () <69>;
(__extDM___PDMint32_.46 var=48) source () <70>;
(pointer_coefficient_line_ptr_start.47 var=49) source () <71>;
(__ct_0.59 var=61) const () <83>;
(__la.61 var=62 stl=LR off=0) inp () <85>;
(__la.62 var=62) deassign (__la.61) <86>;
(c_sensor_signal_t.64 var=63 stl=A off=0) inp () <88>;
(c_sensor_signal_t.65 var=63) deassign (c_sensor_signal_t.64) <89>;
(acc_sensor_signal_t.67 var=64 stl=A off=1) inp () <91>;
(acc_sensor_signal_t.68 var=64) deassign (acc_sensor_signal_t.67) <92>;
(b_c.70 var=65 stl=A off=2) inp () <94>;
(b_c.71 var=65) deassign (b_c.70) <95>;
(b_acc.73 var=66 stl=A off=3) inp () <97>;
(b_acc.74 var=66) deassign (b_acc.73) <98>;
(delay_c.76 var=67 stl=RA off=0) inp () <100>;
(delay_c.77 var=67) deassign (delay_c.76) <101>;
(delay_acc.79 var=68 stl=RA off=1) inp () <103>;
(delay_acc.80 var=68) deassign (delay_acc.79) <104>;
(weight_c.82 var=69 stl=AX off=0) inp () <106>;
(weight_c.83 var=69) deassign (weight_c.82) <107>;
(weight_acc.85 var=70 stl=AX off=1) inp () <109>;
(weight_acc.86 var=70) deassign (weight_acc.85) <110>;
(lms_mu.88 var=71 stl=BX off=0) inp () <112>;
(lms_mu.89 var=71) deassign (lms_mu.88) <113>;
(number_coefficients.91 var=72 stl=RB off=0) inp () <115>;
(number_coefficients.92 var=72) deassign (number_coefficients.91) <116>;
(__rd___sp.94 var=50) rd_res_reg (__R_SP.24 __sp.32) <118>;
(__R_SP.98 var=26 __sp.99 var=34) wr_res_reg (__rt.679 __sp.32) <122>;
(__fch___extDM_int64_.106 var=81) load (__M_LDMA.12 b_c.71 __extDM_int64_.42) <130>;
(__fch___extDM_int64_.111 var=85) load (__M_LDMA.12 __rt.767 __extDM_int64_.42) <135>;
(__fch___extDM_int64_.116 var=89) load (__M_LDMA.12 __rt.789 __extDM_int64_.42) <140>;
(__fch___extDM_int64_.121 var=93) load (__M_LDMA.12 __rt.811 __extDM_int64_.42) <145>;
(__fch___extDM_int64_.126 var=97) load (__M_LDMA.12 __rt.833 __extDM_int64_.42) <150>;
(__ct_31.128 var=98) const () <152>;
(_Z20scale_preemph_filterP16SingleSignalPathdddddi.131 var=100) const () <155>;
(__link.133 var=102) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <157>;
(__rt.679 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.94 __ct_0S0.934) <617>;
(__rt.767 var=217) __Pvoid__pl___Pvoid_int18_ (b_c.71 __ct_8.937) <729>;
(__rt.789 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.767 __ct_8.937) <757>;
(__rt.811 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.789 __ct_8.937) <785>;
(__rt.833 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.811 __ct_8.937) <813>;
(__ct_0S0.934 var=248) const () <965>;
(__ct_8.937 var=251) const () <971>;
call {
(c_sensor_signal_t.102 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <126>;
(__fch___extDM_int64_.107 var=81 stl=AX off=0) assign (__fch___extDM_int64_.106) <131>;
(__fch___extDM_int64_.112 var=85 stl=AX off=1) assign (__fch___extDM_int64_.111) <136>;
(__fch___extDM_int64_.117 var=89 stl=BX off=0) assign (__fch___extDM_int64_.116) <141>;
(__fch___extDM_int64_.122 var=93 stl=BX off=1) assign (__fch___extDM_int64_.121) <146>;
(__fch___extDM_int64_.127 var=97 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.126) <151>;
(__ct.130 var=99 stl=RA off=0) assign (__ct_31.128) <154>;
(__link.134 var=102 stl=LR off=0) assign (__link.133) <158>;
(_ZL2mu.135 var=35 __extDM.136 var=32 __extDM_BufferPtr.137 var=41 __extDM_BufferPtrDMB.138 var=38 __extDM_SingleSignalPath.139 var=43 __extDM___PDMint32_.140 var=48 __extDM_int32_.141 var=36 __extDM_int64_.142 var=44 __extDM_void.143 var=45 __extPM.144 var=33 __extPM_void.145 var=46 coefficient_line.146 var=42 pointer_coefficient_line.147 var=40 pointer_coefficient_line_ptr_start.148 var=49 pointer_sample_line.149 var=37 pointer_sample_line_ptr_start.150 var=47 sample_line.151 var=39 __vola.152 var=29) F_Z20scale_preemph_filterP16SingleSignalPathdddddi (__link.134 c_sensor_signal_t.102 __fch___extDM_int64_.107 __fch___extDM_int64_.112 __fch___extDM_int64_.117 __fch___extDM_int64_.122 __fch___extDM_int64_.127 __ct.130 _ZL2mu.33 __extDM.30 __extDM_BufferPtr.39 __extDM_BufferPtrDMB.36 __extDM_SingleSignalPath.41 __extDM___PDMint32_.46 __extDM_int32_.34 __extDM_int64_.42 __extDM_void.43 __extPM.31 __extPM_void.44 coefficient_line.40 pointer_coefficient_line.38 pointer_coefficient_line_ptr_start.47 pointer_sample_line.35 pointer_sample_line_ptr_start.45 sample_line.37 __vola.27) <159>;
} #4 off=1
#5 off=2
(_Z9set_delayP16SingleSignalPathi.155 var=103) const () <162>;
(__link.157 var=105) dmaddr__call_dmaddr_ (_Z9set_delayP16SingleSignalPathi.155) <164>;
call {
(c_sensor_signal_t.153 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <160>;
(delay_c.154 var=67 stl=RA off=1) assign (delay_c.77) <161>;
(__link.158 var=105 stl=LR off=0) assign (__link.157) <165>;
(__tmp.159 var=106 stl=RA off=0 _ZL2mu.162 var=35 __extDM.163 var=32 __extDM_BufferPtr.164 var=41 __extDM_BufferPtrDMB.165 var=38 __extDM_SingleSignalPath.166 var=43 __extDM___PDMint32_.167 var=48 __extDM_int32_.168 var=36 __extDM_int64_.169 var=44 __extDM_void.170 var=45 __extPM.171 var=33 __extPM_void.172 var=46 coefficient_line.173 var=42 pointer_coefficient_line.174 var=40 pointer_coefficient_line_ptr_start.175 var=49 pointer_sample_line.176 var=37 pointer_sample_line_ptr_start.177 var=47 sample_line.178 var=39 __vola.179 var=29) F_Z9set_delayP16SingleSignalPathi (__link.158 c_sensor_signal_t.153 delay_c.154 _ZL2mu.135 __extDM.136 __extDM_BufferPtr.137 __extDM_BufferPtrDMB.138 __extDM_SingleSignalPath.139 __extDM___PDMint32_.140 __extDM_int32_.141 __extDM_int64_.142 __extDM_void.143 __extPM.144 __extPM_void.145 coefficient_line.146 pointer_coefficient_line.147 pointer_coefficient_line_ptr_start.148 pointer_sample_line.149 pointer_sample_line_ptr_start.150 sample_line.151 __vola.152) <166>;
} #6 off=3
#7 off=4
(_Z10set_weightP16SingleSignalPathdi.185 var=109) const () <174>;
(__link.187 var=111) dmaddr__call_dmaddr_ (_Z10set_weightP16SingleSignalPathdi.185) <176>;
call {
(c_sensor_signal_t.180 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <169>;
(weight_c.181 var=69 stl=AX off=0) assign (weight_c.83) <170>;
(__ct.184 var=108 stl=RA off=0) assign (__ct_31.128) <173>;
(__link.188 var=111 stl=LR off=0) assign (__link.187) <177>;
(_ZL2mu.189 var=35 __extDM.190 var=32 __extDM_BufferPtr.191 var=41 __extDM_BufferPtrDMB.192 var=38 __extDM_SingleSignalPath.193 var=43 __extDM___PDMint32_.194 var=48 __extDM_int32_.195 var=36 __extDM_int64_.196 var=44 __extDM_void.197 var=45 __extPM.198 var=33 __extPM_void.199 var=46 coefficient_line.200 var=42 pointer_coefficient_line.201 var=40 pointer_coefficient_line_ptr_start.202 var=49 pointer_sample_line.203 var=37 pointer_sample_line_ptr_start.204 var=47 sample_line.205 var=39 __vola.206 var=29) F_Z10set_weightP16SingleSignalPathdi (__link.188 c_sensor_signal_t.180 weight_c.181 __ct.184 _ZL2mu.162 __extDM.163 __extDM_BufferPtr.164 __extDM_BufferPtrDMB.165 __extDM_SingleSignalPath.166 __extDM___PDMint32_.167 __extDM_int32_.168 __extDM_int64_.169 __extDM_void.170 __extPM.171 __extPM_void.172 coefficient_line.173 pointer_coefficient_line.174 pointer_coefficient_line_ptr_start.175 pointer_sample_line.176 pointer_sample_line_ptr_start.177 sample_line.178 __vola.179) <178>;
} #8 off=5
#370 off=6
(__fch___extDM_int64_.211 var=115) load (__M_LDMA.12 b_acc.74 __extDM_int64_.196) <183>;
(__fch___extDM_int64_.216 var=119) load (__M_LDMA.12 __rt.855 __extDM_int64_.196) <188>;
(__fch___extDM_int64_.221 var=123) load (__M_LDMA.12 __rt.877 __extDM_int64_.196) <193>;
(__fch___extDM_int64_.226 var=127) load (__M_LDMA.12 __rt.899 __extDM_int64_.196) <198>;
(__fch___extDM_int64_.231 var=131) load (__M_LDMA.12 __rt.921 __extDM_int64_.196) <203>;
(__link.238 var=136) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <210>;
(__rt.855 var=217) __Pvoid__pl___Pvoid_int18_ (b_acc.74 __ct_8.937) <841>;
(__rt.877 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.855 __ct_8.937) <869>;
(__rt.899 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.877 __ct_8.937) <897>;
(__rt.921 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.899 __ct_8.937) <925>;
call {
(acc_sensor_signal_t.207 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <179>;
(__fch___extDM_int64_.212 var=115 stl=AX off=0) assign (__fch___extDM_int64_.211) <184>;
(__fch___extDM_int64_.217 var=119 stl=AX off=1) assign (__fch___extDM_int64_.216) <189>;
(__fch___extDM_int64_.222 var=123 stl=BX off=0) assign (__fch___extDM_int64_.221) <194>;
(__fch___extDM_int64_.227 var=127 stl=BX off=1) assign (__fch___extDM_int64_.226) <199>;
(__fch___extDM_int64_.232 var=131 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.231) <204>;
(__ct.235 var=133 stl=RA off=0) assign (__ct_31.128) <207>;
(__link.239 var=136 stl=LR off=0) assign (__link.238) <211>;
(_ZL2mu.240 var=35 __extDM.241 var=32 __extDM_BufferPtr.242 var=41 __extDM_BufferPtrDMB.243 var=38 __extDM_SingleSignalPath.244 var=43 __extDM___PDMint32_.245 var=48 __extDM_int32_.246 var=36 __extDM_int64_.247 var=44 __extDM_void.248 var=45 __extPM.249 var=33 __extPM_void.250 var=46 coefficient_line.251 var=42 pointer_coefficient_line.252 var=40 pointer_coefficient_line_ptr_start.253 var=49 pointer_sample_line.254 var=37 pointer_sample_line_ptr_start.255 var=47 sample_line.256 var=39 __vola.257 var=29) F_Z20scale_preemph_filterP16SingleSignalPathdddddi (__link.239 acc_sensor_signal_t.207 __fch___extDM_int64_.212 __fch___extDM_int64_.217 __fch___extDM_int64_.222 __fch___extDM_int64_.227 __fch___extDM_int64_.232 __ct.235 _ZL2mu.189 __extDM.190 __extDM_BufferPtr.191 __extDM_BufferPtrDMB.192 __extDM_SingleSignalPath.193 __extDM___PDMint32_.194 __extDM_int32_.195 __extDM_int64_.196 __extDM_void.197 __extPM.198 __extPM_void.199 coefficient_line.200 pointer_coefficient_line.201 pointer_coefficient_line_ptr_start.202 pointer_sample_line.203 pointer_sample_line_ptr_start.204 sample_line.205 __vola.206) <212>;
} #10 off=7
#11 off=8
(__link.262 var=139) dmaddr__call_dmaddr_ (_Z9set_delayP16SingleSignalPathi.155) <217>;
call {
(acc_sensor_signal_t.258 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <213>;
(delay_acc.259 var=68 stl=RA off=1) assign (delay_acc.80) <214>;
(__link.263 var=139 stl=LR off=0) assign (__link.262) <218>;
(__tmp.264 var=140 stl=RA off=0 _ZL2mu.267 var=35 __extDM.268 var=32 __extDM_BufferPtr.269 var=41 __extDM_BufferPtrDMB.270 var=38 __extDM_SingleSignalPath.271 var=43 __extDM___PDMint32_.272 var=48 __extDM_int32_.273 var=36 __extDM_int64_.274 var=44 __extDM_void.275 var=45 __extPM.276 var=33 __extPM_void.277 var=46 coefficient_line.278 var=42 pointer_coefficient_line.279 var=40 pointer_coefficient_line_ptr_start.280 var=49 pointer_sample_line.281 var=37 pointer_sample_line_ptr_start.282 var=47 sample_line.283 var=39 __vola.284 var=29) F_Z9set_delayP16SingleSignalPathi (__link.263 acc_sensor_signal_t.258 delay_acc.259 _ZL2mu.240 __extDM.241 __extDM_BufferPtr.242 __extDM_BufferPtrDMB.243 __extDM_SingleSignalPath.244 __extDM___PDMint32_.245 __extDM_int32_.246 __extDM_int64_.247 __extDM_void.248 __extPM.249 __extPM_void.250 coefficient_line.251 pointer_coefficient_line.252 pointer_coefficient_line_ptr_start.253 pointer_sample_line.254 pointer_sample_line_ptr_start.255 sample_line.256 __vola.257) <219>;
} #12 off=9
#13 off=10
(__link.292 var=145) dmaddr__call_dmaddr_ (_Z10set_weightP16SingleSignalPathdi.185) <229>;
call {
(acc_sensor_signal_t.285 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <222>;
(weight_acc.286 var=70 stl=AX off=0) assign (weight_acc.86) <223>;
(__ct.289 var=142 stl=RA off=0) assign (__ct_31.128) <226>;
(__link.293 var=145 stl=LR off=0) assign (__link.292) <230>;
(_ZL2mu.294 var=35 __extDM.295 var=32 __extDM_BufferPtr.296 var=41 __extDM_BufferPtrDMB.297 var=38 __extDM_SingleSignalPath.298 var=43 __extDM___PDMint32_.299 var=48 __extDM_int32_.300 var=36 __extDM_int64_.301 var=44 __extDM_void.302 var=45 __extPM.303 var=33 __extPM_void.304 var=46 coefficient_line.305 var=42 pointer_coefficient_line.306 var=40 pointer_coefficient_line_ptr_start.307 var=49 pointer_sample_line.308 var=37 pointer_sample_line_ptr_start.309 var=47 sample_line.310 var=39 __vola.311 var=29) F_Z10set_weightP16SingleSignalPathdi (__link.293 acc_sensor_signal_t.285 weight_acc.286 __ct.289 _ZL2mu.267 __extDM.268 __extDM_BufferPtr.269 __extDM_BufferPtrDMB.270 __extDM_SingleSignalPath.271 __extDM___PDMint32_.272 __extDM_int32_.273 __extDM_int64_.274 __extDM_void.275 __extPM.276 __extPM_void.277 coefficient_line.278 pointer_coefficient_line.279 pointer_coefficient_line_ptr_start.280 pointer_sample_line.281 pointer_sample_line_ptr_start.282 sample_line.283 __vola.284) <231>;
} #14 off=11
#474 off=12
(__ct_4746794007244308480.312 var=146) const () <232>;
(_Z11float64_mulyy.954 var=268) const () <1022>;
(__link.955 var=269) dmaddr__call_dmaddr_ (_Z11float64_mulyy.954) <1023>;
call {
(lms_mu.956 var=71 stl=AX off=1) assign (lms_mu.89) <1024>;
(__a1.957 var=267 stl=BX off=0) assign (__ct_4746794007244308480.312) <1025>;
(__link.958 var=269 stl=LR off=0) assign (__link.955) <1026>;
(__tmp.959 var=271 stl=AX off=0) F_Z11float64_mulyy (__link.958 lms_mu.956 __a1.957) <1027>;
(__tmp.960 var=148) deassign (__tmp.959) <1028>;
} #475 off=13
#480 off=14
(_Z30float64_to_int32_round_to_zeroy.963 var=273) const () <1034>;
(__link.964 var=274) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.963) <1035>;
call {
(__tmp.965 var=148 stl=AX off=0) assign (__tmp.960) <1036>;
(__link.966 var=274 stl=LR off=0) assign (__link.964) <1037>;
(__tmp.967 var=149 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.966 __tmp.965) <1038>;
(__tmp.968 var=149) deassign (__tmp.967) <1039>;
} #481 off=15
#471 off=16
(__ptr_mu.49 var=52) const () <73>;
(__ptr_pointer_sample_line.51 var=54) const () <75>;
(__ptr_sample_line.53 var=56) const () <77>;
(__M_WDMA.316 var=11 _ZL2mu.317 var=35) store (__tmp.968 __ptr_mu.49 _ZL2mu.294) <236>;
(__ct_64.321 var=150) const () <240>;
(_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324 var=152) const () <243>;
(__link.326 var=154) dmaddr__call_dmaddr_ (_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324) <245>;
call {
(__ptr_pointer_sample_line.318 var=53 stl=A off=4) assign (__ptr_pointer_sample_line.51) <237>;
(__ptr_sample_line.319 var=55 stl=A off=5) assign (__ptr_sample_line.53) <238>;
(number_coefficients.320 var=72 stl=RA off=1) assign (number_coefficients.92) <239>;
(__ct.323 var=151 stl=RB off=0) assign (__ct_64.321) <242>;
(__link.327 var=154 stl=LR off=0) assign (__link.326) <246>;
(__tmp.328 var=155 stl=RA off=0 _ZL2mu.331 var=35 __extDM.332 var=32 __extDM_BufferPtr.333 var=41 __extDM_BufferPtrDMB.334 var=38 __extDM_SingleSignalPath.335 var=43 __extDM___PDMint32_.336 var=48 __extDM_int32_.337 var=36 __extDM_int64_.338 var=44 __extDM_void.339 var=45 __extPM.340 var=33 __extPM_void.341 var=46 coefficient_line.342 var=42 pointer_coefficient_line.343 var=40 pointer_coefficient_line_ptr_start.344 var=49 pointer_sample_line.345 var=37 pointer_sample_line_ptr_start.346 var=47 sample_line.347 var=39 __vola.348 var=29) F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii (__link.327 __ptr_pointer_sample_line.318 __ptr_sample_line.319 number_coefficients.320 __ct.323 _ZL2mu.317 __extDM.295 __extDM_BufferPtr.296 __extDM_BufferPtrDMB.297 __extDM_SingleSignalPath.298 __extDM___PDMint32_.299 __extDM_int32_.300 __extDM_int64_.301 __extDM_void.302 __extPM.303 __extPM_void.304 coefficient_line.305 pointer_coefficient_line.306 pointer_coefficient_line_ptr_start.307 pointer_sample_line.308 pointer_sample_line_ptr_start.309 sample_line.310 __vola.311) <247>;
} #16 off=17
#17 off=18
(__ptr_pointer_coefficient_line.55 var=58) const () <79>;
(__ptr_coefficient_line.57 var=60) const () <81>;
(_Z17initialize_bufferP9BufferPtrPiii.355 var=158) const () <256>;
(__link.357 var=160) dmaddr__call_dmaddr_ (_Z17initialize_bufferP9BufferPtrPiii.355) <258>;
call {
(__ptr_pointer_coefficient_line.349 var=57 stl=A off=0) assign (__ptr_pointer_coefficient_line.55) <250>;
(__ptr_coefficient_line.350 var=59 stl=A off=1) assign (__ptr_coefficient_line.57) <251>;
(number_coefficients.351 var=72 stl=RA off=1) assign (number_coefficients.92) <252>;
(__ct.354 var=157 stl=RB off=0) assign (__ct_64.321) <255>;
(__link.358 var=160 stl=LR off=0) assign (__link.357) <259>;
(__tmp.359 var=161 stl=RA off=0 _ZL2mu.362 var=35 __extDM.363 var=32 __extDM_BufferPtr.364 var=41 __extDM_BufferPtrDMB.365 var=38 __extDM_SingleSignalPath.366 var=43 __extDM___PDMint32_.367 var=48 __extDM_int32_.368 var=36 __extDM_int64_.369 var=44 __extDM_void.370 var=45 __extPM.371 var=33 __extPM_void.372 var=46 coefficient_line.373 var=42 pointer_coefficient_line.374 var=40 pointer_coefficient_line_ptr_start.375 var=49 pointer_sample_line.376 var=37 pointer_sample_line_ptr_start.377 var=47 sample_line.378 var=39 __vola.379 var=29) F_Z17initialize_bufferP9BufferPtrPiii (__link.358 __ptr_pointer_coefficient_line.349 __ptr_coefficient_line.350 number_coefficients.351 __ct.354 _ZL2mu.331 __extDM.332 __extDM_BufferPtr.333 __extDM_BufferPtrDMB.334 __extDM_SingleSignalPath.335 __extDM___PDMint32_.336 __extDM_int32_.337 __extDM_int64_.338 __extDM_void.339 __extPM.340 __extPM_void.341 coefficient_line.342 pointer_coefficient_line.343 pointer_coefficient_line_ptr_start.344 pointer_sample_line.345 pointer_sample_line_ptr_start.346 sample_line.347 __vola.348) <260>;
} #18 off=19
#466 off=20
(__ct_0.103 var=78) const () <127>;
(__tmp.947 var=262) uint3__cmp_int72__int72_ (number_coefficients.92 __ct_0.103) <989>;
(__tmp.975 var=164) bool_nplus_uint3_ (__tmp.947) <1098>;
(__trgt.978 var=286) const () <1126>;
() void_jump_bool_int10_ (__tmp.975 __trgt.978) <1127>;
(__either.979 var=285) undefined () <1128>;
if {
{
() if_expr (__either.979) <306>;
() chess_frequent_else () <307>;
() chess_rear_then () <1129>;
} #21
{
(__trgt.980 var=287) const () <1130>;
() void_jump_int10_ (__trgt.980) <1131>;
} #27 off=24
{
#34 off=21
(__fch_pointer_sample_line_ptr_start.467 var=170) load (__M_WDMB.10 __ptr_pointer_sample_line__a4.664 pointer_sample_line_ptr_start.377) <352>;
(__fch_pointer_coefficient_line_ptr_start.482 var=180) load (__M_WDMA.9 __ptr_pointer_coefficient_line__a4.665 pointer_coefficient_line_ptr_start.375) <363>;
(__cv.649 var=205) uint16__uint16____sint (number_coefficients.92) <558>;
(__ptr_pointer_sample_line__a4.664 var=213) const () <574>;
(__ptr_pointer_coefficient_line__a4.665 var=214) const () <576>;
(__ct_4.936 var=250) const () <969>;
(__trgt.981 var=288) const () <1132>;
() void_doloop_uint16__uint16_ (__cv.649 __trgt.981) <1133>;
(__vcnt.982 var=289) undefined () <1134>;
for {
{
(_ZL2mu.429 var=35) entry (_ZL2mu.508 _ZL2mu.362) <314>;
(__extDM_int32_.430 var=36) entry (__extDM_int32_.510 __extDM_int32_.368) <315>;
(sample_line.433 var=39) entry (sample_line.516 sample_line.378) <318>;
(coefficient_line.436 var=42) entry (coefficient_line.522 coefficient_line.373) <321>;
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_pointer_sample_line_ptr_start.467) <545>;
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_pointer_coefficient_line_ptr_start.482) <549>;
} #24
{
(__M_WDMB.472 var=12 _ZL2mu.473 var=35 __extDM_int32_.474 var=36 coefficient_line.475 var=42 sample_line.476 var=39) store (__ct_0.103 __iv1_i.635 _ZL2mu.429 __extDM_int32_.430 coefficient_line.436 sample_line.433) <357>;
(__M_WDMA.487 var=11 _ZL2mu.488 var=35 __extDM_int32_.489 var=36 coefficient_line.490 var=42 sample_line.491 var=39) store (__ct_0.103 __iv2_i.640 _ZL2mu.473 __extDM_int32_.474 coefficient_line.475 sample_line.476) <368>;
(__rt.723 var=217) __Pvoid__pl___Pvoid_int18_ (__iv1_i.635 __ct_4.936) <673>;
(__rt.745 var=217) __Pvoid__pl___Pvoid_int18_ (__iv2_i.640 __ct_4.936) <701>;
} #256 off=22
{
() for_count (__vcnt.982) <373>;
(_ZL2mu.508 var=35 _ZL2mu.509 var=35) exit (_ZL2mu.488) <380>;
(__extDM_int32_.510 var=36 __extDM_int32_.511 var=36) exit (__extDM_int32_.489) <381>;
(sample_line.516 var=39 sample_line.517 var=39) exit (sample_line.491) <384>;
(coefficient_line.522 var=42 coefficient_line.523 var=42) exit (coefficient_line.490) <387>;
(__iv1_i.636 var=201 __iv1_i.637 var=201) exit (__rt.723) <546>;
(__iv2_i.641 var=202 __iv2_i.642 var=202) exit (__rt.745) <550>;
} #26
} #23 rng=[1,65535]
} #22
{
(_ZL2mu.574 var=35) merge (_ZL2mu.362 _ZL2mu.509) <413>;
(__extDM_int32_.575 var=36) merge (__extDM_int32_.368 __extDM_int32_.511) <414>;
(sample_line.576 var=39) merge (sample_line.378 sample_line.517) <415>;
(coefficient_line.577 var=42) merge (coefficient_line.373 coefficient_line.523) <416>;
} #28
} #20
#30 off=25 nxt=-2
(__rd___sp.580 var=50) rd_res_reg (__R_SP.24 __sp.99) <419>;
(__R_SP.584 var=26 __sp.585 var=34) wr_res_reg (__rt.701 __sp.99) <423>;
() void_ret_dmaddr_ (__la.62) <424>;
() sink (__vola.379) <425>;
() sink (__extDM.363) <428>;
() sink (__extPM.371) <429>;
() sink (__sp.585) <430>;
() sink (_ZL2mu.574) <431>;
() sink (__extDM_int32_.575) <432>;
() sink (pointer_sample_line.376) <433>;
() sink (__extDM_BufferPtrDMB.365) <434>;
() sink (sample_line.576) <435>;
() sink (pointer_coefficient_line.374) <436>;
() sink (__extDM_BufferPtr.364) <437>;
() sink (coefficient_line.577) <438>;
() sink (__extDM_SingleSignalPath.366) <439>;
() sink (__extDM_int64_.369) <440>;
() sink (__extDM_void.370) <441>;
() sink (__extPM_void.372) <442>;
() sink (pointer_sample_line_ptr_start.377) <443>;
() sink (__extDM___PDMint32_.367) <444>;
() sink (pointer_coefficient_line_ptr_start.375) <445>;
() sink (__ct_0.59) <446>;
(__rt.701 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.580 __ct_0s0.935) <645>;
(__ct_0s0.935 var=249) const () <967>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,291:0,0);
4 : (0,306:4,2);
5 : (0,307:33,3);
6 : (0,307:4,3);
7 : (0,308:44,4);
8 : (0,308:4,4);
10 : (0,311:4,5);
11 : (0,312:35,6);
12 : (0,312:4,6);
13 : (0,313:48,7);
14 : (0,313:4,7);
16 : (0,319:4,10);
17 : (0,320:88,11);
18 : (0,320:4,11);
20 : (0,323:4,13);
22 : (0,323:4,14);
23 : (0,323:4,14);
27 : (0,323:4,22);
30 : (0,327:0,25);
256 : (0,323:50,14);
276 : (0,306:4,2);
370 : (0,311:4,5);
466 : (0,323:4,13);
471 : (0,319:4,10);
474 : (0,317:16,9);
475 : (0,317:16,9);
480 : (0,317:7,9);
481 : (0,317:7,9);
----------
77 : (0,319:48,0);
81 : (0,320:49,0);
118 : (0,291:5,0);
122 : (0,291:5,0);
126 : (0,306:25,0);
127 : (0,306:48,0);
130 : (0,306:47,2);
131 : (0,306:47,0);
135 : (0,306:55,2);
136 : (0,306:55,0);
140 : (0,306:63,2);
141 : (0,306:63,0);
145 : (0,306:71,2);
146 : (0,306:71,0);
150 : (0,306:79,2);
151 : (0,306:79,0);
152 : (0,306:84,0);
154 : (0,306:84,0);
157 : (0,306:4,2);
158 : (0,306:4,0);
159 : (0,306:4,2);
160 : (0,307:14,0);
161 : (0,307:33,0);
164 : (0,307:4,3);
165 : (0,307:4,0);
166 : (0,307:4,3);
169 : (0,308:15,0);
170 : (0,308:34,0);
173 : (0,308:44,0);
176 : (0,308:4,4);
177 : (0,308:4,0);
178 : (0,308:4,4);
179 : (0,311:25,0);
183 : (0,311:51,5);
184 : (0,311:51,0);
188 : (0,311:61,5);
189 : (0,311:61,0);
193 : (0,311:71,5);
194 : (0,311:71,0);
198 : (0,311:81,5);
199 : (0,311:81,0);
203 : (0,311:91,5);
204 : (0,311:91,0);
207 : (0,311:96,0);
210 : (0,311:4,5);
211 : (0,311:4,0);
212 : (0,311:4,5);
213 : (0,312:14,0);
214 : (0,312:35,0);
217 : (0,312:4,6);
218 : (0,312:4,0);
219 : (0,312:4,6);
222 : (0,313:15,0);
223 : (0,313:36,0);
226 : (0,313:48,0);
229 : (0,313:4,7);
230 : (0,313:4,0);
231 : (0,313:4,7);
232 : (0,317:16,0);
236 : (0,317:4,9);
237 : (0,319:26,0);
238 : (0,319:48,0);
239 : (0,319:61,0);
240 : (0,319:82,0);
242 : (0,319:82,0);
245 : (0,319:4,10);
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250 : (0,320:22,0);
251 : (0,320:49,0);
252 : (0,320:67,0);
255 : (0,320:88,0);
258 : (0,320:4,11);
259 : (0,320:4,0);
260 : (0,320:4,11);
306 : (0,323:4,13);
314 : (0,323:4,14);
315 : (0,323:4,14);
318 : (0,323:4,14);
321 : (0,323:4,14);
352 : (0,324:27,14);
357 : (0,324:37,14);
363 : (0,325:32,15);
368 : (0,325:42,15);
373 : (0,323:4,20);
380 : (0,323:4,20);
381 : (0,323:4,20);
384 : (0,323:4,20);
387 : (0,323:4,20);
413 : (0,323:4,24);
414 : (0,323:4,24);
415 : (0,323:4,24);
416 : (0,323:4,24);
419 : (0,327:0,0);
423 : (0,327:0,25);
424 : (0,327:0,25);
574 : (0,324:27,0);
576 : (0,325:32,0);
617 : (0,291:5,0);
645 : (0,327:0,0);
729 : (0,306:55,0);
757 : (0,306:63,0);
785 : (0,306:71,0);
813 : (0,306:79,0);
841 : (0,311:61,0);
869 : (0,311:71,0);
897 : (0,311:81,0);
925 : (0,311:91,0);
965 : (0,291:5,0);
967 : (0,327:0,0);
971 : (0,306:55,0);
989 : (0,323:4,13);
1022 : (0,317:16,0);
1023 : (0,317:16,9);
1024 : (0,317:16,9);
1025 : (0,317:16,9);
1026 : (0,317:16,9);
1027 : (0,317:16,9);
1028 : (0,317:16,9);
1034 : (0,317:7,0);
1035 : (0,317:7,9);
1036 : (0,317:7,9);
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7
simulation/Release/chesswork/signal_path-4df6b6.#
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@@ -1,10 +1,11 @@
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
f120f5de328ad64582ff8b5317653c8c0e1bc5a4
0af2c45e33552c5c7b753a0927f528cf9623362c
da39a3ee5e6b4b0d3255bfef95601890afd80709
d14eceba62157a1c418a76571f06326e1f2b1b57
120
105965f0f4bb5e0aac52292eaeab8be33ff2810a
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simulation/Release/chesswork/signal_path-4df6b6.o
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52
simulation/Release/chesswork/signal_path-4df6b6.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -17,7 +17,7 @@ F_Z12write_bufferP9BufferPtri : user_defined, called {
***/
[
0 : _Z12write_bufferP9BufferPtri typ=uint20_ bnd=e stl=PM tref=void_____PBufferPtr___sint___1
0 : _Z12write_bufferP9BufferPtri typ=uint20_ bnd=e stl=PM tref=void_____PBufferPtr___sint__
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
@@ -90,29 +90,29 @@ F_Z12write_bufferP9BufferPtri {
} #5 off=0 nxt=-2
0 : 'signal_processing\\signal_path.c';
----------
5 : (0,120:0,3);
5 : (0,173:0,3);
----------
75 : (0,117:5,0);
79 : (0,117:5,0);
84 : (0,118:11,1);
85 : (0,118:4,1);
95 : (0,119:67,2);
99 : (0,119:86,2);
107 : (0,119:10,2);
108 : (0,120:0,0);
112 : (0,120:0,3);
113 : (0,120:0,3);
159 : (0,119:26,2);
173 : (0,119:26,0);
181 : (0,119:86,0);
208 : (0,117:5,0);
236 : (0,118:11,1);
264 : (0,120:0,0);
292 : (0,119:67,0);
348 : (0,118:11,0);
375 : (0,117:5,0);
377 : (0,118:11,0);
383 : (0,120:0,0);
390 : (0,119:86,0);
391 : (0,119:86,2);
75 : (0,170:5,0);
79 : (0,170:5,0);
84 : (0,171:11,1);
85 : (0,171:4,1);
95 : (0,172:67,2);
99 : (0,172:86,2);
107 : (0,172:10,2);
108 : (0,173:0,0);
112 : (0,173:0,3);
113 : (0,173:0,3);
159 : (0,172:26,2);
173 : (0,172:26,0);
181 : (0,172:86,0);
208 : (0,170:5,0);
236 : (0,171:11,1);
264 : (0,173:0,0);
292 : (0,172:67,0);
348 : (0,171:11,0);
375 : (0,170:5,0);
377 : (0,171:11,0);
383 : (0,173:0,0);
390 : (0,172:86,0);
391 : (0,172:86,2);

14
simulation/Release/chesswork/signal_path-52b1a0.# Normal file
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42695db990e5aaff0b9f36d25938c80e96ce47cc
d43e60573dff41d7caa6843aab76050d392fca8b
da39a3ee5e6b4b0d3255bfef95601890afd80709
a110a3232e8d964969476fdb921cbf3cc58da017
331
0
0
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simulation/Release/chesswork/signal_path-52b1a0.o Normal file
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513
simulation/Release/chesswork/signal_path-52b1a0.sfg Normal file
View File

@@ -0,0 +1,513 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calculate_output" 'void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );
frm : ( );
}
****
!! void write_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int)
F_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called {
fnm : "write_buffer_dmb" 'void write_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int)';
arg : ( dmaddr_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[4] RA[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
***/
[
0 : _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___PSingleSignalPath___PDMB__sshort___PDMB__sshort___PDMB__sshort__
8 : __M_SDMB typ=int16_ bnd=d stl=SDMB
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
29 : __vola typ=uint20_ bnd=b stl=PM
32 : __extDM typ=int8_ bnd=b stl=DM
33 : __extPM typ=uint20_ bnd=b stl=PM
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
36 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
37 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
38 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
39 : pointer_sample_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
40 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
41 : pointer_coefficient_line typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
42 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
43 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
44 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
45 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
46 : __extDM_int32_ typ=int8_ bnd=b stl=DM
47 : __extDM_int16_ typ=int8_ bnd=b stl=DM
48 : __extDM_void typ=int8_ bnd=b stl=DM
49 : __extPM_void typ=uint20_ bnd=b stl=PM
50 : pointer_sample_line_ptr_current typ=int8_ bnd=b stl=DM
51 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
52 : pointer_sample_line_ptr_start typ=int8_ bnd=b stl=DM
53 : pointer_coefficient_line_ptr_current typ=int8_ bnd=b stl=DM
54 : pointer_sample_line_buffer_len typ=int8_ bnd=b stl=DM
55 : pointer_coefficient_line_buffer_len typ=int8_ bnd=b stl=DM
56 : pointer_coefficient_line_ptr_start typ=int8_ bnd=b stl=DM
57 : __extDM_int64_ typ=int8_ bnd=b stl=DM
58 : __rd___sp typ=dmaddr_ bnd=m
60 : __ptr_c_sensor_32 typ=dmaddr_ val=0a bnd=m adro=35
62 : __ptr_acc_sensor_32 typ=dmaddr_ val=0a bnd=m adro=36
64 : __ptr_c_sensor_pre typ=dmaddr_ val=0a bnd=m adro=37
66 : __ptr_acc_sensor_pre typ=dmaddr_ val=0a bnd=m adro=38
67 : __ptr_pointer_sample_line typ=dmaddr_ bnd=m
68 : __ptr_pointer_sample_line typ=dmaddr_ val=0a bnd=m adro=39
70 : __ptr_pointer_coefficient_line typ=dmaddr_ val=0a bnd=m adro=41
72 : __ptr_filter_accumulator typ=dmaddr_ val=0a bnd=m adro=43
74 : __ptr_output_32 typ=dmaddr_ val=0a bnd=m adro=44
76 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=45
77 : __ct_0 typ=uint1_ val=0f bnd=m
78 : __la typ=dmaddr_ bnd=p tref=dmaddr___
79 : c_sensor_signal_t typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
80 : acc_sensor_signal_t typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
81 : c_sensor_input typ=dmaddr_ bnd=p tref=__PDMB__sshort__
82 : acc_sensor_input typ=dmaddr_ bnd=p tref=__PDMB__sshort__
83 : output_port typ=dmaddr_ bnd=p tref=__PDMB__sshort__
91 : __tmpb0_F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=int32_ bnd=m tref=__sint__
96 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__
98 : __inl_p_w typ=dmaddr_ bnd=m tref=__P__sint__
101 : __inl_acc_fir_1 typ=int72_ bnd=m tref=accum_t__
102 : __inl_acc_fir_2 typ=int72_ bnd=m tref=accum_t__
110 : __inl_acc_fir typ=int72_ bnd=m tref=accum_t__
117 : __inl_p_w0 typ=dmaddr_ bnd=m tref=__P__sint__
118 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__
119 : __inl_p_x1 typ=dmaddr_ bnd=m tref=__PDMB__sint__
123 : __inl_product typ=int72_ bnd=m tref=accum_t__
124 : __inl_correction typ=int32_ bnd=m tref=__sint__
126 : __inl_w0 typ=int32_ bnd=m tref=__sint__
127 : __inl_w1 typ=int32_ bnd=m tref=__sint__
128 : __inl_acc_w0 typ=int72_ bnd=m tref=accum_t__
129 : __inl_acc_w1 typ=int72_ bnd=m tref=accum_t__
136 : __ct_2 typ=int32_ val=2f bnd=m
140 : __fch___extDM_int16_ typ=int16_ bnd=m
142 : __ct_16 typ=int32_ val=16f bnd=m
144 : __tmp typ=int32_ bnd=m
155 : __fch___extDM_int16_ typ=int16_ bnd=m
159 : __tmp typ=int32_ bnd=m
201 : __ct_0 typ=int32_ val=0f bnd=m
204 : __fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre typ=int32_ bnd=m
205 : _Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi typ=dmaddr_ val=0r bnd=m
207 : __link typ=dmaddr_ bnd=m
211 : __fch_pointer_sample_line_ptr_current typ=dmaddr_ bnd=m
215 : __fch_pointer_sample_line_ptr_start typ=dmaddr_ bnd=m
219 : __fch_pointer_coefficient_line_ptr_current typ=dmaddr_ bnd=m
223 : __fch_pointer_sample_line_buffer_len typ=int32_ bnd=m
227 : __fch_pointer_coefficient_line_buffer_len typ=int32_ bnd=m
236 : __fchtmp typ=int32_ bnd=m
237 : __fchtmp typ=int32_ bnd=m
247 : __fchtmp typ=int32_ bnd=m
248 : __fchtmp typ=int32_ bnd=m
258 : __tmp typ=int72_ bnd=m
260 : __tmp typ=int72_ bnd=m
274 : __fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre typ=int32_ bnd=m
279 : __tmp typ=int32_ bnd=m
290 : __fch_pointer_coefficient_line_ptr_start typ=dmaddr_ bnd=m
327 : __fch__ZL2mu typ=int32_ bnd=m
332 : __fchtmp typ=int64_ bnd=m
338 : __fchtmp typ=int32_ bnd=m
339 : __tmp typ=int72_ bnd=m
341 : __fchtmp typ=int32_ bnd=m
342 : __tmp typ=int72_ bnd=m
356 : __tmp typ=int32_ bnd=m
357 : __tmp typ=int32_ bnd=m
358 : __tmp typ=int64_ bnd=m
377 : __fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32 typ=int32_ bnd=m
381 : __tmp typ=int72_ bnd=m
382 : __tmp typ=int32_ bnd=m
383 : __tmp typ=int16_ bnd=m
423 : __ct_m4 typ=int18_ val=-4f bnd=m
424 : __ct_m8 typ=int18_ val=-8f bnd=m
448 : __vcnt typ=int32_ bnd=m
449 : __ct_m1 typ=int32_ val=-1f bnd=m
450 : __ct_1 typ=int32_ val=1f bnd=m
451 : __cv typ=uint16_ bnd=m
477 : __ptr_pointer_coefficient_line__a8 typ=dmaddr_ val=8a bnd=m adro=41
480 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
508 : __ct_0S0 typ=int18_ val=0S0 bnd=m
509 : __ct_0s0 typ=int18_ val=0s0 bnd=m
510 : __ct_4 typ=int18_ val=4f bnd=m
511 : __ct_8 typ=int18_ val=8f bnd=m
515 : __ct_2 typ=uint2_ val=2f bnd=m
522 : __ct_1 typ=uint2_ val=1f bnd=m
527 : __tmp typ=int72_ bnd=m
532 : __tmp typ=int18_ bnd=m
540 : __trgt typ=uint16_ val=0j bnd=m
541 : __vcnt typ=uint16_ bnd=m
542 : __trgt typ=uint16_ val=0j bnd=m
543 : __vcnt typ=uint16_ bnd=m
]
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ {
#593 off=0
(__M_SDMB.6 var=8) st_def () <12>;
(__M_WDMA.9 var=11) st_def () <18>;
(__M_WDMB.10 var=12) st_def () <20>;
(__M_LDMA.12 var=14) st_def () <24>;
(__R_SP.24 var=26) st_def () <48>;
(__vola.27 var=29) source () <51>;
(__extDM.30 var=32) source () <54>;
(__extPM.31 var=33) source () <55>;
(__sp.32 var=34) source () <56>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32.33 var=35) source () <57>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32.34 var=36) source () <58>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.35 var=37) source () <59>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.36 var=38) source () <60>;
(pointer_sample_line.37 var=39) source () <61>;
(__extDM_BufferPtrDMB.38 var=40) source () <62>;
(pointer_coefficient_line.39 var=41) source () <63>;
(__extDM_BufferPtr.40 var=42) source () <64>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator.41 var=43) source () <65>;
(_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.42 var=44) source () <66>;
(_ZL2mu.43 var=45) source () <67>;
(__extDM_int32_.44 var=46) source () <68>;
(__extDM_int16_.45 var=47) source () <69>;
(__extDM_void.46 var=48) source () <70>;
(__extPM_void.47 var=49) source () <71>;
(pointer_sample_line_ptr_current.48 var=50) source () <72>;
(__extDM___PDMint32_.49 var=51) source () <73>;
(pointer_sample_line_ptr_start.50 var=52) source () <74>;
(pointer_coefficient_line_ptr_current.51 var=53) source () <75>;
(pointer_sample_line_buffer_len.52 var=54) source () <76>;
(pointer_coefficient_line_buffer_len.53 var=55) source () <77>;
(pointer_coefficient_line_ptr_start.54 var=56) source () <78>;
(__extDM_int64_.55 var=57) source () <79>;
(__ptr_c_sensor_32.57 var=60) const () <81>;
(__ptr_acc_sensor_32.59 var=62) const () <83>;
(__ptr_c_sensor_pre.61 var=64) const () <85>;
(__ptr_acc_sensor_pre.63 var=66) const () <87>;
(__ptr_pointer_sample_line.65 var=68) const () <89>;
(__ct_0.75 var=77) const () <99>;
(__la.77 var=78 stl=LR off=0) inp () <101>;
(__la.78 var=78) deassign (__la.77) <102>;
(c_sensor_signal_t.80 var=79 stl=A off=0) inp () <104>;
(acc_sensor_signal_t.83 var=80 stl=A off=1) inp () <107>;
(c_sensor_input.86 var=81 stl=A off=4) inp () <110>;
(c_sensor_input.87 var=81) deassign (c_sensor_input.86) <111>;
(acc_sensor_input.89 var=82 stl=A off=5) inp () <113>;
(acc_sensor_input.90 var=82) deassign (acc_sensor_input.89) <114>;
(output_port.92 var=83 stl=__spill_WDMA off=0) inp () <116>;
(output_port.93 var=83) deassign (output_port.92) <117>;
(__rd___sp.95 var=58) rd_res_reg (__R_SP.24 __sp.32) <119>;
(__R_SP.99 var=26 __sp.100 var=34) wr_res_reg (__rt.2216 __sp.32) <123>;
(__fch___extDM_int16_.243 var=140 __extDM_int16_.244 var=47 __vola.245 var=29) load (__M_SDMB.6 c_sensor_input.87 __extDM_int16_.45 __vola.27) <267>;
(__ct_16.247 var=142) const () <269>;
(__M_WDMA.255 var=11 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32.256 var=35) store (__tmp.2412 __ptr_c_sensor_32.57 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32.33) <277>;
(__fch___extDM_int16_.262 var=155 __extDM_int16_.263 var=47 __vola.264 var=29) load (__M_SDMB.6 acc_sensor_input.90 __extDM_int16_.244 __vola.245) <283>;
(__M_WDMA.274 var=11 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32.275 var=36) store (__tmp.2417 __ptr_acc_sensor_32.59 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32.34) <293>;
(__M_WDMA.560 var=11 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.561 var=37) store (__tmp.2412 __ptr_c_sensor_pre.61 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.35) <491>;
(__M_WDMA.573 var=11 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.574 var=38) store (__tmp.2417 __ptr_acc_sensor_pre.63 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.36) <503>;
(_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi.763 var=205) const () <605>;
(__link.765 var=207) dmaddr__call_dmaddr_ (_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi.763) <607>;
(__rt.2216 var=480) __Pvoid__pl___Pvoid_int18_ (__rd___sp.95 __ct_0S0.2405) <1902>;
(__ct_0S0.2405 var=508) const () <2169>;
(__ct_2.2411 var=515) const () <2180>;
(__tmp.2412 var=144) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.243 __ct_16.247 __ct_2.2411) <2181>;
(__tmp.2417 var=159) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.262 __ct_16.247 __ct_2.2411) <2189>;
call {
(__ptr_pointer_sample_line.757 var=67 stl=A off=4) assign (__ptr_pointer_sample_line.65) <599>;
(__fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.762 var=204 stl=RA off=0) assign (__tmp.2417) <604>;
(__link.766 var=207 stl=LR off=0) assign (__link.765) <608>;
(_ZL2mu.767 var=45 __extDM.768 var=32 __extDM_BufferPtr.769 var=42 __extDM_BufferPtrDMB.770 var=40 __extDM___PDMint32_.771 var=51 __extDM_int16_.772 var=47 __extDM_int32_.773 var=46 __extDM_int64_.774 var=57 __extDM_void.775 var=48 __extPM.776 var=33 __extPM_void.777 var=49 pointer_coefficient_line.778 var=41 pointer_coefficient_line_buffer_len.779 var=55 pointer_coefficient_line_ptr_current.780 var=53 pointer_coefficient_line_ptr_start.781 var=56 pointer_sample_line.782 var=39 pointer_sample_line_buffer_len.783 var=54 pointer_sample_line_ptr_current.784 var=50 pointer_sample_line_ptr_start.785 var=52 __vola.786 var=29) F_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi (__link.766 __ptr_pointer_sample_line.757 __fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.762 _ZL2mu.43 __extDM.30 __extDM_BufferPtr.40 __extDM_BufferPtrDMB.38 __extDM___PDMint32_.49 __extDM_int16_.263 __extDM_int32_.44 __extDM_int64_.55 __extDM_void.46 __extPM.31 __extPM_void.47 pointer_coefficient_line.39 pointer_coefficient_line_buffer_len.53 pointer_coefficient_line_ptr_current.51 pointer_coefficient_line_ptr_start.54 pointer_sample_line.37 pointer_sample_line_buffer_len.52 pointer_sample_line_ptr_current.48 pointer_sample_line_ptr_start.50 __vola.264) <609>;
} #14 off=1
#615 off=2
(__ptr_pointer_coefficient_line.67 var=70) const () <91>;
(__ct_2.239 var=136) const () <263>;
(__ct_0.758 var=201) const () <600>;
(__fch_pointer_sample_line_ptr_current.796 var=211) load (__M_WDMB.10 __rt.2326 pointer_sample_line_ptr_current.784) <619>;
(__fch_pointer_sample_line_ptr_start.801 var=215) load (__M_WDMB.10 __rt.2348 pointer_sample_line_ptr_start.785) <624>;
(__fch_pointer_coefficient_line_ptr_current.806 var=219) load (__M_WDMA.9 __ptr_pointer_coefficient_line__a8.2202 pointer_coefficient_line_ptr_current.780) <629>;
(__fch_pointer_sample_line_buffer_len.811 var=223) load (__M_WDMB.10 __rt.2370 pointer_sample_line_buffer_len.783) <634>;
(__fch_pointer_coefficient_line_buffer_len.816 var=227) load (__M_WDMA.9 __ptr_pointer_coefficient_line.67 pointer_coefficient_line_buffer_len.779) <639>;
(__ct_m4.2073 var=423) const () <1735>;
(__ct_m1.2134 var=449) const () <1787>;
(__vcnt.2135 var=448) __sint__pl___sint___sint (__fch_pointer_coefficient_line_buffer_len.816 __ct_m1.2134) <1789>;
(__ct_1.2137 var=450) const () <1791>;
(__vcnt.2138 var=448) __sint__pl___sint___sint (__vcnt.2433 __ct_1.2137) <1793>;
(__cv.2139 var=451) uint16__uint16____sint (__vcnt.2138) <1794>;
(__ptr_pointer_coefficient_line__a8.2202 var=477) const () <1858>;
(__rt.2326 var=480) __Pvoid__pl___Pvoid_int18_ (__ptr_pointer_sample_line.65 __ct_8.2408) <2042>;
(__rt.2348 var=480) __Pvoid__mi___Pvoid_int18_ (__rt.2326 __ct_4.2407) <2070>;
(__rt.2370 var=480) __Pvoid__mi___Pvoid_int18_ (__rt.2348 __ct_4.2407) <2098>;
(__rt.2392 var=480) __Pvoid__pl___Pvoid_int18_ (__ptr_pointer_coefficient_line.67 __ct_4.2407) <2126>;
(__ct_4.2407 var=510) const () <2173>;
(__ct_8.2408 var=511) const () <2175>;
(__tmp.2422 var=532) int72__shift_int72__int72__uint2_ (__fch_pointer_sample_line_buffer_len.811 __ct_2.239 __ct_2.2411) <2197>;
(__ct_1.2426 var=522) const () <2204>;
(__tmp.2432 var=527) int72__shift_int72__int72__uint2_ (__vcnt.2135 __ct_1.2137 __ct_1.2426) <2213>;
(__vcnt.2433 var=448) int32__extract_high_int72_ (__tmp.2432) <2214>;
(__trgt.2441 var=540) const () <2305>;
() void_doloop_uint16__uint16_ (__cv.2139 __trgt.2441) <2306>;
(__vcnt.2442 var=541) undefined () <2307>;
for {
{
(__inl_p_x0.880 var=96) entry (__inl_p_x0.1045 __fch_pointer_sample_line_ptr_current.796) <703>;
(__inl_p_w.882 var=98) entry (__inl_p_w.1049 __fch_pointer_coefficient_line_ptr_current.806) <705>;
(__inl_acc_fir_1.885 var=101) entry (__inl_acc_fir_1.1055 __ct_0.758) <708>;
(__inl_acc_fir_2.886 var=102) entry (__inl_acc_fir_2.1057 __ct_0.758) <709>;
} #17
{
(__fchtmp.921 var=236) load (__M_WDMB.10 __inl_p_x0.880 _ZL2mu.767 __extDM_int32_.773 pointer_coefficient_line_buffer_len.779 pointer_sample_line_buffer_len.783) <744>;
(__fchtmp.922 var=237) load (__M_WDMA.9 __inl_p_w.882 _ZL2mu.767 __extDM_int32_.773 pointer_coefficient_line_buffer_len.779 pointer_sample_line_buffer_len.783) <745>;
(__fchtmp.932 var=247) load (__M_WDMB.10 __inl_p_x0.2012 _ZL2mu.767 __extDM_int32_.773 pointer_coefficient_line_buffer_len.779 pointer_sample_line_buffer_len.783) <755>;
(__fchtmp.933 var=248) load (__M_WDMA.9 __rt.2260 _ZL2mu.767 __extDM_int32_.773 pointer_coefficient_line_buffer_len.779 pointer_sample_line_buffer_len.783) <756>;
(__inl_acc_fir_1.944 var=101) accum_t__pl_accum_t_accum_t (__inl_acc_fir_1.885 __tmp.2025) <767>;
(__inl_acc_fir_2.946 var=102) accum_t__pl_accum_t_accum_t (__inl_acc_fir_2.886 __tmp.2030) <769>;
(__inl_p_x0.2012 var=96) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.880 __ct_m4.2073 __fch_pointer_sample_line_ptr_start.801 __tmp.2422) <1621>;
(__inl_p_x0.2020 var=96) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.2012 __ct_m4.2073 __fch_pointer_sample_line_ptr_start.801 __tmp.2422) <1632>;
(__tmp.2025 var=258) int72__multss_int32__int32__uint1_ (__fchtmp.921 __fchtmp.922 __ct_0.75) <1640>;
(__tmp.2030 var=260) int72__multss_int32__int32__uint1_ (__fchtmp.932 __fchtmp.933 __ct_0.75) <1648>;
(__rt.2260 var=480) __Pvoid__pl___Pvoid_int18_ (__inl_p_w.882 __ct_4.2407) <1958>;
(__rt.2282 var=480) __Pvoid__pl___Pvoid_int18_ (__rt.2260 __ct_4.2407) <1986>;
} #403 off=3
{
() for_count (__vcnt.2442) <774>;
(__inl_p_x0.1045 var=96 __inl_p_x0.1046 var=96) exit (__inl_p_x0.2020) <822>;
(__inl_p_w.1049 var=98 __inl_p_w.1050 var=98) exit (__rt.2282) <824>;
(__inl_acc_fir_1.1055 var=101 __inl_acc_fir_1.1056 var=101) exit (__inl_acc_fir_1.944) <827>;
(__inl_acc_fir_2.1057 var=102 __inl_acc_fir_2.1058 var=102) exit (__inl_acc_fir_2.946) <828>;
} #19
} #16 rng=[1,65535]
#99 off=4
(__ptr_filter_accumulator.69 var=72) const () <93>;
(__ptr_output_32.71 var=74) const () <95>;
(__ptr_mu.73 var=76) const () <97>;
(__inl_acc_fir.1127 var=110) accum_t__pl_accum_t_accum_t (__inl_acc_fir_1.1056 __inl_acc_fir_2.1058) <863>;
(__tmpb0_F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.1128 var=91) __sint_rnd_saturate_accum_t (__inl_acc_fir.1127) <864>;
(__M_WDMB.1132 var=12 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator.1133 var=43) store (__tmpb0_F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.1128 __ptr_filter_accumulator.69 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator.41) <868>;
(__fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.1137 var=274) load (__M_WDMA.9 __ptr_c_sensor_pre.61 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.561) <872>;
(__tmp.1142 var=279) __sint__mi___sint___sint (__fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.1137 __tmpb0_F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.1128) <877>;
(__M_WDMB.1146 var=12 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.1147 var=44) store (__tmp.1142 __ptr_output_32.71 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.42) <881>;
(__fch_pointer_coefficient_line_ptr_start.1163 var=290) load (__M_WDMA.9 __rt.2392 pointer_coefficient_line_ptr_start.781) <897>;
(__fch__ZL2mu.1211 var=327) load (__M_WDMA.9 __ptr_mu.73 _ZL2mu.767) <945>;
(__inl_correction.1213 var=124) __sint_rnd_saturate_accum_t (__inl_product.2043) <947>;
(__inl_p_x1.2038 var=119) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch_pointer_sample_line_ptr_current.796 __ct_m4.2073 __fch_pointer_sample_line_ptr_start.801 __tmp.2422) <1659>;
(__inl_product.2043 var=123) int72__multss_int32__int32__uint1_ (__fch__ZL2mu.1211 __tmp.1142 __ct_0.75) <1667>;
(__ct_m8.2074 var=424) const () <1737>;
(__trgt.2443 var=542) const () <2308>;
() void_doloop_uint16__uint16_ (__cv.2139 __trgt.2443) <2309>;
(__vcnt.2444 var=543) undefined () <2310>;
for {
{
(_ZL2mu.1233 var=45) entry (_ZL2mu.1378 _ZL2mu.767) <967>;
(__extDM_int32_.1234 var=46) entry (__extDM_int32_.1380 __extDM_int32_.773) <968>;
(pointer_sample_line_buffer_len.1242 var=54) entry (pointer_sample_line_buffer_len.1396 pointer_sample_line_buffer_len.783) <976>;
(pointer_coefficient_line_buffer_len.1243 var=55) entry (pointer_coefficient_line_buffer_len.1398 pointer_coefficient_line_buffer_len.779) <977>;
(__extDM_int64_.1245 var=57) entry (__extDM_int64_.1402 __extDM_int64_.774) <979>;
(__inl_p_w0.1287 var=117) entry (__inl_p_w0.1486 __fch_pointer_coefficient_line_ptr_start.1163) <1021>;
(__inl_p_x0.1288 var=118) entry (__inl_p_x0.1488 __fch_pointer_sample_line_ptr_current.796) <1022>;
(__inl_p_x1.1289 var=119) entry (__inl_p_x1.1490 __inl_p_x1.2038) <1023>;
} #22
{
(__fchtmp.1305 var=332) load (__M_LDMA.12 __inl_p_w0.1287 _ZL2mu.1233 __extDM_int32_.1234 __extDM_int64_.1245 pointer_coefficient_line_buffer_len.1243 pointer_sample_line_buffer_len.1242) <1039>;
(__inl_w0.1307 var=126 __inl_w1.1308 var=127) void_lldecompose___ulonglong___sint___sint (__fchtmp.1305) <1041>;
(__fchtmp.1311 var=338) load (__M_WDMB.10 __inl_p_x0.1288 _ZL2mu.1233 __extDM_int32_.1234 pointer_coefficient_line_buffer_len.1243 pointer_sample_line_buffer_len.1242) <1044>;
(__inl_acc_w0.1313 var=128) accum_t__pl_accum_t_accum_t (__inl_w0.1307 __tmp.2048) <1046>;
(__fchtmp.1314 var=341) load (__M_WDMB.10 __inl_p_x1.1289 _ZL2mu.1233 __extDM_int32_.1234 pointer_coefficient_line_buffer_len.1243 pointer_sample_line_buffer_len.1242) <1047>;
(__inl_acc_w1.1316 var=129) accum_t__pl_accum_t_accum_t (__inl_w1.1308 __tmp.2053) <1049>;
(__tmp.1329 var=356) __sint_rnd_saturate_accum_t (__inl_acc_w0.1313) <1062>;
(__tmp.1330 var=357) __sint_rnd_saturate_accum_t (__inl_acc_w1.1316) <1063>;
(__tmp.1331 var=358) __ulonglong_llcompose___sint___sint (__tmp.1329 __tmp.1330) <1064>;
(__M_LDMA.1333 var=14 _ZL2mu.1334 var=45 __extDM_int32_.1335 var=46 __extDM_int64_.1336 var=57 pointer_coefficient_line_buffer_len.1337 var=55 pointer_sample_line_buffer_len.1338 var=54) store (__tmp.1331 __inl_p_w0.1287 _ZL2mu.1233 __extDM_int32_.1234 __extDM_int64_.1245 pointer_coefficient_line_buffer_len.1243 pointer_sample_line_buffer_len.1242) <1066>;
(__tmp.2048 var=339) int72__multss_int32__int32__uint1_ (__inl_correction.1213 __fchtmp.1311 __ct_0.75) <1675>;
(__tmp.2053 var=342) int72__multss_int32__int32__uint1_ (__inl_correction.1213 __fchtmp.1314 __ct_0.75) <1683>;
(__inl_p_x0.2061 var=118) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.1288 __ct_m8.2074 __fch_pointer_sample_line_ptr_start.801 __tmp.2422) <1694>;
(__inl_p_x1.2069 var=119) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x1.1289 __ct_m8.2074 __fch_pointer_sample_line_ptr_start.801 __tmp.2422) <1705>;
(__rt.2304 var=480) __Pvoid__pl___Pvoid_int18_ (__inl_p_w0.1287 __ct_8.2408) <2014>;
} #473 off=5
{
() for_count (__vcnt.2444) <1074>;
(_ZL2mu.1378 var=45 _ZL2mu.1379 var=45) exit (_ZL2mu.1334) <1091>;
(__extDM_int32_.1380 var=46 __extDM_int32_.1381 var=46) exit (__extDM_int32_.1335) <1092>;
(pointer_sample_line_buffer_len.1396 var=54 pointer_sample_line_buffer_len.1397 var=54) exit (pointer_sample_line_buffer_len.1338) <1100>;
(pointer_coefficient_line_buffer_len.1398 var=55 pointer_coefficient_line_buffer_len.1399 var=55) exit (pointer_coefficient_line_buffer_len.1337) <1101>;
(__extDM_int64_.1402 var=57 __extDM_int64_.1403 var=57) exit (__extDM_int64_.1336) <1103>;
(__inl_p_w0.1486 var=117 __inl_p_w0.1487 var=117) exit (__rt.2304) <1145>;
(__inl_p_x0.1488 var=118 __inl_p_x0.1489 var=118) exit (__inl_p_x0.2061) <1146>;
(__inl_p_x1.1490 var=119 __inl_p_x1.1491 var=119) exit (__inl_p_x1.2069) <1147>;
} #24
} #21 rng=[1,65535]
#36 off=6 nxt=-2
(__fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.1709 var=377) load (__M_WDMB.10 __ptr_output_32.71 _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.1147) <1352>;
(__tmp.1714 var=382) __sint_rnd_saturate_accum_t (__tmp.2427) <1357>;
(__tmp.1715 var=383) __sshort___sshort___sint (__tmp.1714) <1358>;
(__M_SDMB.1721 var=8 __extDM_int16_.1722 var=47 __vola.1723 var=29) store (__tmp.1715 output_port.93 __extDM_int16_.772 __vola.786) <1364>;
(__rd___sp.1910 var=58) rd_res_reg (__R_SP.24 __sp.100) <1464>;
(__R_SP.1914 var=26 __sp.1915 var=34) wr_res_reg (__rt.2238 __sp.100) <1468>;
() void_ret_dmaddr_ (__la.78) <1469>;
() sink (__vola.1723) <1470>;
() sink (__extDM.768) <1473>;
() sink (__extPM.776) <1474>;
() sink (__sp.1915) <1475>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32.256) <1476>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32.275) <1477>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre.561) <1478>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre.574) <1479>;
() sink (pointer_sample_line.782) <1480>;
() sink (__extDM_BufferPtrDMB.770) <1481>;
() sink (pointer_coefficient_line.778) <1482>;
() sink (__extDM_BufferPtr.769) <1483>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator.1133) <1484>;
() sink (_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.1147) <1485>;
() sink (_ZL2mu.1379) <1486>;
() sink (__extDM_int32_.1381) <1487>;
() sink (__extDM_int16_.1722) <1488>;
() sink (__extDM_void.775) <1489>;
() sink (__extPM_void.777) <1490>;
() sink (pointer_sample_line_ptr_current.784) <1491>;
() sink (__extDM___PDMint32_.771) <1492>;
() sink (pointer_sample_line_ptr_start.785) <1493>;
() sink (pointer_coefficient_line_ptr_current.780) <1494>;
() sink (pointer_sample_line_buffer_len.1397) <1495>;
() sink (pointer_coefficient_line_buffer_len.1399) <1496>;
() sink (pointer_coefficient_line_ptr_start.781) <1497>;
() sink (__extDM_int64_.1403) <1498>;
() sink (__ct_0.75) <1499>;
(__rt.2238 var=480) __Pvoid__pl___Pvoid_int18_ (__rd___sp.1910 __ct_0s0.2406) <1930>;
(__ct_0s0.2406 var=509) const () <2171>;
(__tmp.2427 var=381) int72__shift_int72__int72__uint2_ (__fch__ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32.1709 __ct_16.247 __ct_1.2426) <2205>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,331:0,0);
14 : (0,367:4,23);
16 : (0,370:28,40);
21 : (0,374:4,82);
36 : (0,381:0,110);
99 : (0,374:4,80);
403 : (0,370:28,53);
473 : (0,374:4,0);
593 : (0,367:4,23);
615 : (0,370:28,40);
----------
85 : (0,372:19,0);
87 : (0,367:43,0);
89 : (0,370:28,0);
91 : (0,370:28,0);
93 : (0,370:4,0);
95 : (0,372:4,0);
119 : (0,331:5,0);
123 : (0,331:5,0);
263 : (0,355:47,0);
267 : (0,355:47,8);
269 : (0,355:55,0);
277 : (0,355:19,8);
283 : (0,356:50,9);
293 : (0,356:21,9);
491 : (0,360:21,16);
503 : (0,361:23,17);
599 : (0,367:21,0);
600 : (0,367:58,0);
604 : (0,367:57,0);
607 : (0,367:4,23);
608 : (0,367:4,0);
609 : (0,367:4,23);
619 : (0,370:28,30);
624 : (0,370:28,31);
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705 : (0,370:28,40);
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744 : (0,370:28,40);
745 : (0,370:28,41);
755 : (0,370:28,46);
756 : (0,370:28,47);
767 : (0,370:28,52);
769 : (0,370:28,53);
774 : (0,370:28,56);
822 : (0,370:28,56);
824 : (0,370:28,56);
827 : (0,370:28,56);
828 : (0,370:28,56);
863 : (0,370:28,57);
864 : (0,370:28,58);
868 : (0,370:22,61);
872 : (0,372:31,62);
877 : (0,372:35,62);
881 : (0,372:13,62);
897 : (0,374:4,70);
945 : (0,374:4,79);
947 : (0,374:4,80);
967 : (0,374:4,82);
968 : (0,374:4,82);
976 : (0,374:4,82);
977 : (0,374:4,82);
979 : (0,374:4,82);
1021 : (0,374:4,82);
1022 : (0,374:4,82);
1023 : (0,374:4,82);
1039 : (0,374:4,82);
1041 : (0,374:4,82);
1044 : (0,374:4,85);
1046 : (0,374:4,85);
1047 : (0,374:4,86);
1049 : (0,374:4,86);
1062 : (0,374:4,89);
1063 : (0,374:4,89);
1064 : (0,374:4,89);
1066 : (0,374:4,89);
1074 : (0,374:4,93);
1091 : (0,374:4,93);
1092 : (0,374:4,93);
1100 : (0,374:4,93);
1101 : (0,374:4,93);
1103 : (0,374:4,93);
1145 : (0,374:4,93);
1146 : (0,374:4,93);
1147 : (0,374:4,93);
1352 : (0,378:56,100);
1357 : (0,378:25,100);
1358 : (0,378:23,100);
1364 : (0,378:19,100);
1464 : (0,381:0,0);
1468 : (0,381:0,110);
1469 : (0,381:0,110);
1621 : (0,370:28,45);
1632 : (0,370:28,51);
1640 : (0,370:28,52);
1648 : (0,370:28,53);
1659 : (0,374:4,78);
1667 : (0,374:4,79);
1675 : (0,374:4,85);
1683 : (0,374:4,86);
1694 : (0,374:4,87);
1705 : (0,374:4,88);
1735 : (0,370:28,0);
1737 : (0,374:4,0);
1858 : (0,370:28,0);
1902 : (0,331:5,0);
1930 : (0,381:0,0);
1958 : (0,370:28,0);
1986 : (0,370:28,0);
2014 : (0,374:4,0);
2042 : (0,370:28,0);
2070 : (0,370:28,0);
2098 : (0,370:28,0);
2126 : (0,374:4,0);
2169 : (0,331:5,0);
2171 : (0,381:0,0);
2173 : (0,370:28,0);
2175 : (0,374:4,0);
2180 : (0,355:52,0);
2181 : (0,355:52,8);
2189 : (0,356:55,9);
2197 : (0,370:28,45);
2204 : (0,378:61,0);
2205 : (0,378:61,100);
2306 : (0,370:28,56);
2309 : (0,374:4,93);

2
simulation/Release/chesswork/signal_path-530a42.#
View File

@@ -20,3 +20,5 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
7
7
7
7
7

2
simulation/Release/chesswork/signal_path-530a42.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32

16
simulation/Release/chesswork/signal_path-59265a.#
View File

@@ -3,12 +3,12 @@
42695db990e5aaff0b9f36d25938c80e96ce47cc
7b022b02776bb92fed762bace59f48566912702b
da39a3ee5e6b4b0d3255bfef95601890afd80709
b9e9afcc2aae2fa7eb9404b36c097ce78ba46a5d
73
776a7c2540406a50b5fc8c9e1b9c6777f974f8eb
136
0
0
0
0
0
0
0
1
1
1
1
1
1

BIN
simulation/Release/chesswork/signal_path-59265a.o
View File

Binary file not shown.

96
simulation/Release/chesswork/signal_path-59265a.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -165,52 +165,52 @@ F_Z17initialize_bufferP9BufferPtrPiii {
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,74:0,0);
4 : (0,79:4,5);
6 : (0,79:4,6);
7 : (0,79:4,6);
11 : (0,79:4,13);
14 : (0,82:4,16);
16 : (0,86:8,17);
17 : (0,83:8,21);
20 : (0,82:4,26);
173 : (0,79:37,6);
239 : (0,79:4,5);
242 : (0,82:14,16);
0 : (0,136:0,0);
4 : (0,141:4,5);
6 : (0,141:4,6);
7 : (0,141:4,6);
11 : (0,141:4,13);
14 : (0,144:4,16);
16 : (0,148:8,17);
17 : (0,145:8,21);
20 : (0,144:4,26);
173 : (0,141:37,6);
239 : (0,141:4,5);
242 : (0,144:14,16);
----------
82 : (0,74:4,0);
86 : (0,74:4,0);
90 : (0,75:10,0);
93 : (0,75:10,1);
97 : (0,76:10,2);
101 : (0,77:10,3);
126 : (0,79:4,5);
135 : (0,79:4,6);
136 : (0,79:4,6);
154 : (0,80:24,6);
155 : (0,79:33,0);
159 : (0,79:4,11);
167 : (0,79:4,11);
168 : (0,79:4,11);
180 : (0,79:4,15);
181 : (0,79:4,15);
205 : (0,82:4,16);
210 : (0,82:4,25);
211 : (0,82:4,0);
215 : (0,82:4,26);
216 : (0,82:4,26);
217 : (0,82:4,0);
320 : (0,74:4,0);
348 : (0,82:4,0);
404 : (0,76:10,0);
432 : (0,77:10,0);
457 : (0,74:4,0);
459 : (0,82:4,0);
466 : (0,79:4,5);
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475 : (0,82:14,16);
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135 : (0,141:4,6);
136 : (0,141:4,6);
154 : (0,142:24,6);
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210 : (0,144:4,25);
211 : (0,144:4,0);
215 : (0,144:4,26);
216 : (0,144:4,26);
217 : (0,144:4,0);
320 : (0,136:4,0);
348 : (0,144:4,0);
404 : (0,138:10,0);
432 : (0,139:10,0);
457 : (0,136:4,0);
459 : (0,144:4,0);
466 : (0,141:4,5);
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475 : (0,144:14,16);
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14
simulation/Release/chesswork/signal_path-6dff42.# Normal file
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@@ -0,0 +1,14 @@
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
18b3408058b22f3ae1d43b6d546c2eb1718f55c8
da39a3ee5e6b4b0d3255bfef95601890afd80709
fae7a92977714d9cb361e7ea86077e234c407668
182
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simulation/Release/chesswork/signal_path-6dff42.o Normal file
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736
simulation/Release/chesswork/signal_path-6dff42.sfg Normal file
View File

@@ -0,0 +1,736 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
F_Z20scale_preemph_filterP16SingleSignalPathdddddi : user_defined, called {
fnm : "scale_preemph_filter" 'void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
vac : ( srIM[0] );
frm : ( );
}
****
!! extern double ff_pow(double, double)
Fff_pow : user_defined, called {
fnm : "ff_pow" 'double ff_pow(double, double)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int float64_eq(float64, float64)
F_Z10float64_eqyy : user_defined, called {
fnm : "float64_eq" 'int float64_eq(float64, float64)';
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
loc : ( LR[0] RA[0] AX[0] AX[1] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 int32_to_float64(int)
F_Z16int32_to_float64i : user_defined, called {
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
arg : ( dmaddr_:i int64_:r int32_:i );
loc : ( LR[0] AX[0] RA[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 float64_sub(float64, float64)
F_Z11float64_subyy : user_defined, called {
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! int float64_to_int32_round_to_zero(float64)
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
arg : ( dmaddr_:i int32_:r int64_:i );
loc : ( LR[0] RA[0] AX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! float64 float64_mul(float64, float64)
F_Z11float64_mulyy : user_defined, called {
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
loc : ( LR[0] AX[0] AX[1] BX[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
***/
[
0 : _Z20scale_preemph_filterP16SingleSignalPathdddddi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___fdouble___fdouble___fdouble___fdouble___fdouble___sint__
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __extDM_SingleSignalPath_preemph_activated typ=int8_ bnd=b stl=DM
38 : __extDM_SingleSignalPath__preemph_scale_nbits typ=int8_ bnd=b stl=DM
39 : __extDM_SingleSignalPath_b_preemph typ=int8_ bnd=b stl=DM
40 : __rd___sp typ=dmaddr_ bnd=m
41 : __ct_0 typ=uint1_ val=0f bnd=m
42 : __la typ=dmaddr_ bnd=p tref=dmaddr___
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
44 : b0 typ=int64_ bnd=p tref=__fdouble__
45 : b1 typ=int64_ bnd=p tref=__fdouble__
46 : b2 typ=int64_ bnd=p tref=__fdouble__
47 : a1 typ=int64_ bnd=p tref=__fdouble__
48 : a2 typ=int64_ bnd=p tref=__fdouble__
49 : scale_bits typ=int32_ bnd=p tref=__sint__
53 : __tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
54 : __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
56 : scale typ=int32_ bnd=m lscp=247 tref=__sint__
57 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
60 : __ct_0 typ=uint40_ val=0f bnd=m
65 : __tmp typ=bool bnd=m
71 : __tmp typ=bool bnd=m
77 : __tmp typ=bool bnd=m
83 : __tmp typ=bool bnd=m
84 : __ct_0 typ=int32_ val=0f bnd=m
89 : __ct_1 typ=int32_ val=1f bnd=m
98 : __ct_4611686018427387904 typ=int64_ val=4611686018427387904f bnd=m
103 : __tmp typ=int64_ bnd=m
105 : __tmp typ=int64_ bnd=m
106 : __tmp typ=int64_ bnd=m
107 : __tmp typ=int32_ bnd=m
115 : __tmp typ=int64_ bnd=m
116 : __tmp typ=int32_ bnd=m
124 : __tmp typ=int64_ bnd=m
125 : __tmp typ=int32_ bnd=m
133 : __tmp typ=int64_ bnd=m
134 : __tmp typ=int32_ bnd=m
142 : __tmp typ=int64_ bnd=m
143 : __tmp typ=int32_ bnd=m
164 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
185 : __tmp typ=int32_ bnd=m
202 : __ct_0S0 typ=int18_ val=0S0 bnd=m
203 : __ct_8 typ=int18_ val=8f bnd=m
206 : __ct_0s0 typ=int18_ val=0s0 bnd=m
207 : __ct_24 typ=int18_ val=24f bnd=m
209 : __ct_20 typ=int18_ val=20f bnd=m
210 : __ct_4 typ=int18_ val=4f bnd=m
214 : __tmp typ=bool bnd=m
225 : __a0 typ=int64_ bnd=m tref=__atp0___48
227 : ff_pow typ=dmaddr_ val=0r bnd=m
228 : __link typ=dmaddr_ bnd=m
253 : __a1 typ=int64_ bnd=m tref=__atp1___12
254 : _Z10float64_eqyy typ=dmaddr_ val=0r bnd=m
255 : __link typ=dmaddr_ bnd=m
265 : __tmp typ=uint3_ bnd=m
274 : _Z16int32_to_float64i typ=dmaddr_ val=0r bnd=m
275 : __link typ=dmaddr_ bnd=m
277 : __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m
279 : __a1 typ=int64_ bnd=m tref=__atp1___9
280 : _Z11float64_subyy typ=dmaddr_ val=0r bnd=m
281 : __link typ=dmaddr_ bnd=m
283 : __tmp typ=int64_ bnd=m
285 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
286 : __link typ=dmaddr_ bnd=m
289 : __tmp typ=int64_ bnd=m
292 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
293 : __link typ=dmaddr_ bnd=m
295 : __tmp typ=int64_ bnd=m
297 : __tmp typ=int64_ bnd=m
299 : __tmp typ=int64_ bnd=m
301 : __tmp typ=int64_ bnd=m
303 : __tmp typ=int64_ bnd=m
311 : __true typ=bool val=1f bnd=m
312 : __false typ=bool val=0f bnd=m
313 : __either typ=bool bnd=m
314 : __trgt typ=int10_ val=0j bnd=m
315 : __trgt typ=int10_ val=0j bnd=m
316 : __trgt typ=int10_ val=0j bnd=m
317 : __trgt typ=int10_ val=0j bnd=m
318 : __trgt typ=int10_ val=0j bnd=m
319 : __trgt typ=int10_ val=0j bnd=m
]
F_Z20scale_preemph_filterP16SingleSignalPathdddddi {
#482 off=0
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__extDM_SingleSignalPath_preemph_activated.34 var=36) source () <58>;
(__extDM_SingleSignalPath__preemph_scale_nbits.36 var=38) source () <60>;
(__extDM_SingleSignalPath_b_preemph.37 var=39) source () <61>;
(__ct_0.39 var=41) const () <63>;
(__la.41 var=42 stl=LR off=0) inp () <65>;
(__la.42 var=42) deassign (__la.41) <66>;
(signal.44 var=43 stl=A off=0) inp () <68>;
(signal.45 var=43) deassign (signal.44) <69>;
(b0.47 var=44 stl=AX off=0) inp () <71>;
(b0.48 var=44) deassign (b0.47) <72>;
(b1.50 var=45 stl=AX off=1) inp () <74>;
(b1.51 var=45) deassign (b1.50) <75>;
(b2.53 var=46 stl=BX off=0) inp () <77>;
(b2.54 var=46) deassign (b2.53) <78>;
(a1.56 var=47 stl=BX off=1) inp () <80>;
(a1.57 var=47) deassign (a1.56) <81>;
(a2.59 var=48 stl=__spill_LDMA off=0) inp () <83>;
(a2.60 var=48) deassign (a2.59) <84>;
(scale_bits.62 var=49 stl=RA off=0) inp () <86>;
(scale_bits.63 var=49) deassign (scale_bits.62) <87>;
(__rd___sp.65 var=40) rd_res_reg (__R_SP.24 __sp.32) <89>;
(__R_SP.69 var=26 __sp.70 var=34) wr_res_reg (__rt.365 __sp.32) <93>;
(__ct_4607182418800017408.75 var=57) const () <99>;
(__rt.365 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.65 __ct_0S0.584) <447>;
(__ct_0S0.584 var=202) const () <747>;
(_Z10float64_eqyy.680 var=254) const () <927>;
(__link.681 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <928>;
call {
(b0.682 var=44 stl=AX off=0) assign (b0.48) <929>;
(__a1.683 var=253 stl=AX off=1) assign (__ct_4607182418800017408.75) <930>;
(__link.684 var=255 stl=LR off=0) assign (__link.681) <931>;
(__tmp.685 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.684 b0.682 __a1.683) <932>;
(__tmp.686 var=185) deassign (__tmp.685) <933>;
} #483 off=1
#479 off=2
(__ct_0.101 var=60) const () <126>;
(__ct_0.217 var=84) const () <246>;
(__rt.417 var=164) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_8.585) <520>;
(__ct_8.585 var=203) const () <749>;
(__tmp.730 var=265) uint3__cmp_int72__int72_ (__tmp.686 __ct_0.217) <992>;
(__tmp.888 var=214) bool_equal_uint3_ (__tmp.730) <1262>;
(__trgt.897 var=314) const () <1291>;
() void_jump_bool_int10_ (__tmp.888 __trgt.897) <1292>;
(__either.898 var=313) undefined () <1293>;
if {
{
() if_expr (__either.898) <125>;
} #5
{
(__true.899 var=311) const () <1294>;
} #7
{
#491 off=3
(__link.691 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <941>;
call {
(b1.692 var=45 stl=AX off=0) assign (b1.51) <942>;
(__a1.693 var=253 stl=AX off=1) assign (__ct_0.101) <943>;
(__link.694 var=255 stl=LR off=0) assign (__link.691) <944>;
(__tmp.695 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.694 b1.692 __a1.693) <945>;
(__tmp.696 var=185) deassign (__tmp.695) <946>;
} #492 off=4
#488 off=5
(__tmp.735 var=265) uint3__cmp_int72__int72_ (__tmp.696 __ct_0.217) <1000>;
(__tmp.889 var=214) bool_equal_uint3_ (__tmp.735) <1263>;
(__trgt.900 var=315) const () <1295>;
() void_jump_bool_int10_ (__tmp.889 __trgt.900) <1296>;
(__either.901 var=313) undefined () <1297>;
} #383
{
(__tmp.890 var=65) merge (__true.899 __either.901) <1264>;
} #8
} #4
if {
{
() if_expr (__tmp.890) <155>;
} #11
{
(__true.902 var=311) const () <1298>;
} #13
{
#500 off=6
(__link.701 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <954>;
call {
(b2.702 var=46 stl=AX off=0) assign (b2.54) <955>;
(__a1.703 var=253 stl=AX off=1) assign (__ct_0.101) <956>;
(__link.704 var=255 stl=LR off=0) assign (__link.701) <957>;
(__tmp.705 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.704 b2.702 __a1.703) <958>;
(__tmp.706 var=185) deassign (__tmp.705) <959>;
} #501 off=7
#497 off=8
(__tmp.740 var=265) uint3__cmp_int72__int72_ (__tmp.706 __ct_0.217) <1008>;
(__tmp.891 var=214) bool_equal_uint3_ (__tmp.740) <1265>;
(__trgt.903 var=316) const () <1299>;
() void_jump_bool_int10_ (__tmp.891 __trgt.903) <1300>;
(__either.904 var=313) undefined () <1301>;
} #388
{
(__tmp.892 var=71) merge (__true.902 __either.904) <1266>;
} #14
} #10
if {
{
() if_expr (__tmp.892) <185>;
} #17
{
(__true.905 var=311) const () <1302>;
} #19
{
#509 off=9
(__link.711 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <967>;
call {
(a1.712 var=47 stl=AX off=0) assign (a1.57) <968>;
(__a1.713 var=253 stl=AX off=1) assign (__ct_0.101) <969>;
(__link.714 var=255 stl=LR off=0) assign (__link.711) <970>;
(__tmp.715 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.714 a1.712 __a1.713) <971>;
(__tmp.716 var=185) deassign (__tmp.715) <972>;
} #510 off=10
#506 off=11
(__tmp.745 var=265) uint3__cmp_int72__int72_ (__tmp.716 __ct_0.217) <1016>;
(__tmp.893 var=214) bool_equal_uint3_ (__tmp.745) <1267>;
(__trgt.906 var=317) const () <1303>;
() void_jump_bool_int10_ (__tmp.893 __trgt.906) <1304>;
(__either.907 var=313) undefined () <1305>;
} #393
{
(__tmp.894 var=77) merge (__true.905 __either.907) <1268>;
} #20
} #16
if {
{
() if_expr (__tmp.894) <215>;
} #23
{
(__false.908 var=312) const () <1306>;
} #25
{
#518 off=12
(__link.721 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <980>;
call {
(a2.722 var=48 stl=AX off=0) assign (a2.60) <981>;
(__a1.723 var=253 stl=AX off=1) assign (__ct_0.101) <982>;
(__link.724 var=255 stl=LR off=0) assign (__link.721) <983>;
(__tmp.725 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.724 a2.722 __a1.723) <984>;
(__tmp.726 var=185) deassign (__tmp.725) <985>;
} #519 off=13
#515 off=14
(__tmp.750 var=265) uint3__cmp_int72__int72_ (__tmp.726 __ct_0.217) <1024>;
(__tmp.759 var=214) bool_nequal_uint3_ (__tmp.750) <1051>;
(__trgt.909 var=318) const () <1307>;
() void_jump_bool_int10_ (__tmp.759 __trgt.909) <1308>;
(__either.910 var=313) undefined () <1309>;
} #398
{
(__tmp.193 var=83) merge (__false.908 __either.910) <221>;
} #26
} #22
if {
{
() if_expr (__tmp.193) <245>;
} #29
{
(__M_WDMA.222 var=11 __extDM_SingleSignalPath_preemph_activated.223 var=36) store (__ct_0.217 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <251>;
} #30 off=46
{
#545 off=15
(__ct_1.224 var=89) const () <252>;
(__M_WDMA.229 var=11 __extDM_SingleSignalPath_preemph_activated.230 var=36) store (__ct_1.224 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <257>;
(__M_WDMA.234 var=11 __extDM_SingleSignalPath__preemph_scale_nbits.235 var=38) store (scale_bits.63 __rt.461 __extDM_SingleSignalPath__preemph_scale_nbits.36) <261>;
(__rt.461 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.417 __ct_24.589) <576>;
(__rt.483 var=164) __Pvoid__mi___Pvoid_int18_ (__rt.461 __ct_20.591) <604>;
(__ct_24.589 var=207) const () <757>;
(__ct_20.591 var=209) const () <761>;
(_Z16int32_to_float64i.761 var=274) const () <1054>;
(__link.762 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1055>;
call {
(scale_bits.763 var=49 stl=RA off=0) assign (scale_bits.63) <1056>;
(__link.764 var=275 stl=LR off=0) assign (__link.762) <1057>;
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.765 var=277 stl=AX off=0) F_Z16int32_to_float64i (__link.764 scale_bits.763) <1058>;
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.766 var=54) deassign (__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.765) <1059>;
} #546 off=16
#542 off=17
(__ct_4611686018427387904.241 var=98) const () <267>;
(ff_pow.625 var=227) const () <830>;
(__link.626 var=228) dmaddr__call_dmaddr_ (ff_pow.625) <831>;
call {
(__a0.627 var=225 stl=AX off=1) assign (__ct_4611686018427387904.241) <832>;
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.628 var=54 stl=BX off=0) assign (__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.766) <833>;
(__link.629 var=228 stl=LR off=0) assign (__link.626) <834>;
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.630 var=53 stl=AX off=0) Fff_pow (__link.629 __a0.627 __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.628) <835>;
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.631 var=53) deassign (__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.630) <836>;
} #434 off=18
#573 off=19
(_Z11float64_subyy.770 var=280) const () <1066>;
(__link.771 var=281) dmaddr__call_dmaddr_ (_Z11float64_subyy.770) <1067>;
call {
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.772 var=53 stl=AX off=1) assign (__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.631) <1068>;
(__a1.773 var=279 stl=BX off=0) assign (__ct_4607182418800017408.75) <1069>;
(__link.774 var=281 stl=LR off=0) assign (__link.771) <1070>;
(__tmp.775 var=283 stl=AX off=0) F_Z11float64_subyy (__link.774 __tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.772 __a1.773) <1071>;
(__tmp.776 var=103) deassign (__tmp.775) <1072>;
} #574 off=20
#579 off=21
(_Z30float64_to_int32_round_to_zeroy.779 var=285) const () <1078>;
(__link.780 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1079>;
call {
(__tmp.781 var=103 stl=AX off=0) assign (__tmp.776) <1080>;
(__link.782 var=286 stl=LR off=0) assign (__link.780) <1081>;
(scale.783 var=56 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.782 __tmp.781) <1082>;
(scale.784 var=56) deassign (scale.783) <1083>;
} #580 off=22
#585 off=23
(__link.788 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1090>;
call {
(scale.789 var=56 stl=RA off=0) assign (scale.784) <1091>;
(__link.790 var=275 stl=LR off=0) assign (__link.788) <1092>;
(__tmp.791 var=289 stl=AX off=0) F_Z16int32_to_float64i (__link.790 scale.789) <1093>;
(__tmp.792 var=105) deassign (__tmp.791) <1094>;
} #586 off=24
#591 off=25
(_Z11float64_mulyy.796 var=292) const () <1101>;
(__link.797 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1102>;
call {
(b0.798 var=44 stl=AX off=1) assign (b0.48) <1103>;
(__tmp.799 var=105 stl=BX off=0) assign (__tmp.792) <1104>;
(__link.800 var=293 stl=LR off=0) assign (__link.797) <1105>;
(__tmp.801 var=295 stl=AX off=0) F_Z11float64_mulyy (__link.800 b0.798 __tmp.799) <1106>;
(__tmp.802 var=106) deassign (__tmp.801) <1107>;
} #592 off=26
#597 off=27
(__link.806 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1114>;
call {
(__tmp.807 var=106 stl=AX off=0) assign (__tmp.802) <1115>;
(__link.808 var=286 stl=LR off=0) assign (__link.806) <1116>;
(__tmp.809 var=107 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.808 __tmp.807) <1117>;
(__tmp.810 var=107) deassign (__tmp.809) <1118>;
} #598 off=28
#603 off=29
(__M_WDMA.257 var=11 __extDM_SingleSignalPath_b_preemph.258 var=39) store (__tmp.810 __rt.483 __extDM_SingleSignalPath_b_preemph.37) <283>;
(__rt.505 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.483 __ct_4.592) <632>;
(__ct_4.592 var=210) const () <763>;
(__link.815 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1126>;
call {
(b1.816 var=45 stl=AX off=1) assign (b1.51) <1127>;
(__tmp.817 var=105 stl=BX off=0) assign (__tmp.792) <1128>;
(__link.818 var=293 stl=LR off=0) assign (__link.815) <1129>;
(__tmp.819 var=297 stl=AX off=0) F_Z11float64_mulyy (__link.818 b1.816 __tmp.817) <1130>;
(__tmp.820 var=115) deassign (__tmp.819) <1131>;
} #604 off=30
#609 off=31
(__link.824 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1138>;
call {
(__tmp.825 var=115 stl=AX off=0) assign (__tmp.820) <1139>;
(__link.826 var=286 stl=LR off=0) assign (__link.824) <1140>;
(__tmp.827 var=116 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.826 __tmp.825) <1141>;
(__tmp.828 var=116) deassign (__tmp.827) <1142>;
} #610 off=32
#615 off=33
(__M_WDMA.268 var=11 __extDM_SingleSignalPath_b_preemph.269 var=39) store (__tmp.828 __rt.505 __extDM_SingleSignalPath_b_preemph.258) <293>;
(__rt.527 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.505 __ct_4.592) <660>;
(__link.833 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1150>;
call {
(b2.834 var=46 stl=AX off=1) assign (b2.54) <1151>;
(__tmp.835 var=105 stl=BX off=0) assign (__tmp.792) <1152>;
(__link.836 var=293 stl=LR off=0) assign (__link.833) <1153>;
(__tmp.837 var=299 stl=AX off=0) F_Z11float64_mulyy (__link.836 b2.834 __tmp.835) <1154>;
(__tmp.838 var=124) deassign (__tmp.837) <1155>;
} #616 off=34
#621 off=35
(__link.842 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1162>;
call {
(__tmp.843 var=124 stl=AX off=0) assign (__tmp.838) <1163>;
(__link.844 var=286 stl=LR off=0) assign (__link.842) <1164>;
(__tmp.845 var=125 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.844 __tmp.843) <1165>;
(__tmp.846 var=125) deassign (__tmp.845) <1166>;
} #622 off=36
#627 off=37
(__M_WDMA.279 var=11 __extDM_SingleSignalPath_b_preemph.280 var=39) store (__tmp.846 __rt.527 __extDM_SingleSignalPath_b_preemph.269) <303>;
(__rt.549 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.527 __ct_4.592) <688>;
(__link.851 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1174>;
call {
(a1.852 var=47 stl=AX off=1) assign (a1.57) <1175>;
(__tmp.853 var=105 stl=BX off=0) assign (__tmp.792) <1176>;
(__link.854 var=293 stl=LR off=0) assign (__link.851) <1177>;
(__tmp.855 var=301 stl=AX off=0) F_Z11float64_mulyy (__link.854 a1.852 __tmp.853) <1178>;
(__tmp.856 var=133) deassign (__tmp.855) <1179>;
} #628 off=38
#633 off=39
(__link.860 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1186>;
call {
(__tmp.861 var=133 stl=AX off=0) assign (__tmp.856) <1187>;
(__link.862 var=286 stl=LR off=0) assign (__link.860) <1188>;
(__tmp.863 var=134 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.862 __tmp.861) <1189>;
(__tmp.864 var=134) deassign (__tmp.863) <1190>;
} #634 off=40
#639 off=41
(__M_WDMA.290 var=11 __extDM_SingleSignalPath_b_preemph.291 var=39) store (__tmp.864 __rt.549 __extDM_SingleSignalPath_b_preemph.280) <313>;
(__rt.571 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.549 __ct_4.592) <716>;
(__link.869 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1198>;
call {
(a2.870 var=48 stl=AX off=1) assign (a2.60) <1199>;
(__tmp.871 var=105 stl=BX off=0) assign (__tmp.792) <1200>;
(__link.872 var=293 stl=LR off=0) assign (__link.869) <1201>;
(__tmp.873 var=303 stl=AX off=0) F_Z11float64_mulyy (__link.872 a2.870 __tmp.871) <1202>;
(__tmp.874 var=142) deassign (__tmp.873) <1203>;
} #640 off=42
#645 off=43
(__link.878 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1210>;
call {
(__tmp.879 var=142 stl=AX off=0) assign (__tmp.874) <1211>;
(__link.880 var=286 stl=LR off=0) assign (__link.878) <1212>;
(__tmp.881 var=143 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.880 __tmp.879) <1213>;
(__tmp.882 var=143) deassign (__tmp.881) <1214>;
} #646 off=44
#570 off=45
(__M_WDMA.301 var=11 __extDM_SingleSignalPath_b_preemph.302 var=39) store (__tmp.882 __rt.571 __extDM_SingleSignalPath_b_preemph.291) <323>;
(__trgt.911 var=319) const () <1310>;
() void_jump_int10_ (__trgt.911) <1311>;
} #247
{
(__extDM_SingleSignalPath_preemph_activated.303 var=36) merge (__extDM_SingleSignalPath_preemph_activated.223 __extDM_SingleSignalPath_preemph_activated.230) <324>;
(__extDM_SingleSignalPath__preemph_scale_nbits.304 var=38) merge (__extDM_SingleSignalPath__preemph_scale_nbits.36 __extDM_SingleSignalPath__preemph_scale_nbits.235) <325>;
(__extDM_SingleSignalPath_b_preemph.305 var=39) merge (__extDM_SingleSignalPath_b_preemph.37 __extDM_SingleSignalPath_b_preemph.302) <326>;
} #32
} #28
#34 off=47 nxt=-2
(__rd___sp.310 var=40) rd_res_reg (__R_SP.24 __sp.70) <331>;
(__R_SP.314 var=26 __sp.315 var=34) wr_res_reg (__rt.439 __sp.70) <335>;
() void_ret_dmaddr_ (__la.42) <336>;
() sink (__sp.315) <342>;
() sink (__extDM_SingleSignalPath_preemph_activated.303) <344>;
() sink (__extDM_SingleSignalPath__preemph_scale_nbits.304) <346>;
() sink (__extDM_SingleSignalPath_b_preemph.305) <347>;
() sink (__ct_0.39) <348>;
(__rt.439 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.310 __ct_0s0.588) <548>;
(__ct_0s0.588 var=206) const () <755>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,182:0,0);
4 : (0,184:17,1);
7 : (0,184:17,3);
10 : (0,184:29,5);
13 : (0,184:29,7);
16 : (0,184:41,9);
19 : (0,184:41,11);
22 : (0,184:53,13);
25 : (0,184:53,15);
28 : (0,184:4,17);
30 : (0,184:66,18);
34 : (0,198:0,42);
247 : (0,196:25,38);
383 : (0,184:23,2);
388 : (0,184:35,6);
393 : (0,184:47,10);
398 : (0,184:59,14);
434 : (0,190:20,30);
479 : (0,184:11,1);
482 : (0,184:11,1);
483 : (0,184:11,1);
488 : (0,184:23,2);
491 : (0,184:23,2);
492 : (0,184:23,2);
497 : (0,184:35,6);
500 : (0,184:35,6);
501 : (0,184:35,6);
506 : (0,184:47,10);
509 : (0,184:47,10);
510 : (0,184:47,10);
515 : (0,184:59,14);
518 : (0,184:59,14);
519 : (0,184:59,14);
542 : (0,190:20,30);
545 : (0,190:25,27);
546 : (0,190:25,27);
570 : (0,196:25,38);
573 : (0,190:39,33);
574 : (0,190:39,33);
579 : (0,190:39,33);
580 : (0,190:39,33);
585 : (0,192:34,34);
586 : (0,192:34,34);
591 : (0,192:34,34);
592 : (0,192:34,34);
597 : (0,192:29,34);
598 : (0,192:29,34);
603 : (0,193:34,35);
604 : (0,193:34,35);
609 : (0,193:29,35);
610 : (0,193:29,35);
615 : (0,194:34,36);
616 : (0,194:34,36);
621 : (0,194:29,36);
622 : (0,194:29,36);
627 : (0,195:34,37);
628 : (0,195:34,37);
633 : (0,195:29,37);
634 : (0,195:29,37);
639 : (0,196:34,38);
640 : (0,196:34,38);
645 : (0,196:29,38);
646 : (0,196:29,38);
----------
89 : (0,182:5,0);
93 : (0,182:5,0);
99 : (0,184:14,0);
125 : (0,184:17,1);
126 : (0,184:26,0);
155 : (0,184:29,5);
185 : (0,184:41,9);
215 : (0,184:53,13);
221 : (0,184:53,16);
245 : (0,184:4,17);
246 : (0,185:36,0);
251 : (0,185:14,18);
252 : (0,188:36,0);
257 : (0,188:14,21);
261 : (0,189:14,22);
267 : (0,190:20,0);
283 : (0,192:25,34);
293 : (0,193:25,35);
303 : (0,194:25,36);
313 : (0,195:25,37);
323 : (0,196:25,38);
324 : (0,184:4,41);
325 : (0,184:4,41);
326 : (0,184:4,41);
331 : (0,198:0,0);
335 : (0,198:0,42);
336 : (0,198:0,42);
447 : (0,182:5,0);
520 : (0,185:14,18);
548 : (0,198:0,0);
576 : (0,189:14,0);
604 : (0,192:14,0);
632 : (0,193:25,0);
660 : (0,194:25,0);
688 : (0,195:25,0);
716 : (0,196:25,0);
747 : (0,182:5,0);
749 : (0,185:14,0);
755 : (0,198:0,0);
757 : (0,189:14,0);
761 : (0,192:14,0);
763 : (0,193:25,0);
830 : (0,190:20,0);
831 : (0,190:20,30);
832 : (0,190:20,30);
833 : (0,190:20,30);
834 : (0,190:20,30);
835 : (0,190:20,30);
836 : (0,190:20,30);
927 : (0,184:11,0);
928 : (0,184:11,1);
929 : (0,184:11,1);
930 : (0,184:11,1);
931 : (0,184:11,1);
932 : (0,184:11,1);
933 : (0,184:11,1);
941 : (0,184:23,2);
942 : (0,184:23,2);
943 : (0,184:23,2);
944 : (0,184:23,2);
945 : (0,184:23,2);
946 : (0,184:23,2);
954 : (0,184:35,6);
955 : (0,184:35,6);
956 : (0,184:35,6);
957 : (0,184:35,6);
958 : (0,184:35,6);
959 : (0,184:35,6);
967 : (0,184:47,10);
968 : (0,184:47,10);
969 : (0,184:47,10);
970 : (0,184:47,10);
971 : (0,184:47,10);
972 : (0,184:47,10);
980 : (0,184:59,14);
981 : (0,184:59,14);
982 : (0,184:59,14);
983 : (0,184:59,14);
984 : (0,184:59,14);
985 : (0,184:59,14);
992 : (0,184:11,1);
1000 : (0,184:23,2);
1008 : (0,184:35,6);
1016 : (0,184:47,10);
1024 : (0,184:59,14);
1051 : (0,184:59,14);
1054 : (0,190:25,0);
1055 : (0,190:25,27);
1056 : (0,190:25,27);
1057 : (0,190:25,27);
1058 : (0,190:25,27);
1059 : (0,190:25,27);
1066 : (0,190:39,0);
1067 : (0,190:39,33);
1068 : (0,190:39,33);
1069 : (0,190:39,33);
1070 : (0,190:39,33);
1071 : (0,190:39,33);
1072 : (0,190:39,33);
1078 : (0,190:39,0);
1079 : (0,190:39,33);
1080 : (0,190:39,33);
1081 : (0,190:39,33);
1082 : (0,190:39,33);
1083 : (0,190:39,33);
1090 : (0,192:34,34);
1091 : (0,192:34,34);
1092 : (0,192:34,34);
1093 : (0,192:34,34);
1094 : (0,192:34,34);
1101 : (0,192:34,0);
1102 : (0,192:34,34);
1103 : (0,192:34,34);
1104 : (0,192:34,34);
1105 : (0,192:34,34);
1106 : (0,192:34,34);
1107 : (0,192:34,34);
1114 : (0,192:29,34);
1115 : (0,192:29,34);
1116 : (0,192:29,34);
1117 : (0,192:29,34);
1118 : (0,192:29,34);
1126 : (0,193:34,35);
1127 : (0,193:34,35);
1128 : (0,193:34,35);
1129 : (0,193:34,35);
1130 : (0,193:34,35);
1131 : (0,193:34,35);
1138 : (0,193:29,35);
1139 : (0,193:29,35);
1140 : (0,193:29,35);
1141 : (0,193:29,35);
1142 : (0,193:29,35);
1150 : (0,194:34,36);
1151 : (0,194:34,36);
1152 : (0,194:34,36);
1153 : (0,194:34,36);
1154 : (0,194:34,36);
1155 : (0,194:34,36);
1162 : (0,194:29,36);
1163 : (0,194:29,36);
1164 : (0,194:29,36);
1165 : (0,194:29,36);
1166 : (0,194:29,36);
1174 : (0,195:34,37);
1175 : (0,195:34,37);
1176 : (0,195:34,37);
1177 : (0,195:34,37);
1178 : (0,195:34,37);
1179 : (0,195:34,37);
1186 : (0,195:29,37);
1187 : (0,195:29,37);
1188 : (0,195:29,37);
1189 : (0,195:29,37);
1190 : (0,195:29,37);
1198 : (0,196:34,38);
1199 : (0,196:34,38);
1200 : (0,196:34,38);
1201 : (0,196:34,38);
1202 : (0,196:34,38);
1203 : (0,196:34,38);
1210 : (0,196:29,38);
1211 : (0,196:29,38);
1212 : (0,196:29,38);
1213 : (0,196:29,38);
1214 : (0,196:29,38);
1262 : (0,184:11,1);
1263 : (0,184:23,2);
1264 : (0,184:17,4);
1265 : (0,184:35,6);
1266 : (0,184:29,8);
1267 : (0,184:47,10);
1268 : (0,184:41,12);
1292 : (0,184:17,1);
1296 : (0,184:29,5);
1300 : (0,184:41,9);
1304 : (0,184:53,13);
1308 : (0,184:4,17);

3
simulation/Release/chesswork/signal_path-6fcf7f.#
View File

@@ -12,3 +12,6 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
5
5
5
5
4
4

52
simulation/Release/chesswork/signal_path-6fcf7f.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 10:32:28 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -119,30 +119,30 @@ F_Z14sig_init_delayP16SingleSignalPathi {
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,159:0,0);
4 : (0,160:11,1);
6 : (0,160:4,1);
142 : (0,160:4,1);
0 : (0,158:0,0);
4 : (0,159:11,1);
6 : (0,159:4,1);
142 : (0,159:4,1);
----------
77 : (0,159:4,0);
81 : (0,159:4,0);
86 : (0,160:36,0);
90 : (0,160:58,0);
91 : (0,160:75,0);
92 : (0,160:84,0);
94 : (0,160:84,0);
98 : (0,160:11,0);
99 : (0,160:11,1);
102 : (0,160:4,0);
106 : (0,160:4,1);
108 : (0,160:28,0);
192 : (0,159:4,0);
220 : (0,160:36,1);
248 : (0,160:4,0);
276 : (0,160:58,0);
303 : (0,159:4,0);
305 : (0,160:36,0);
311 : (0,160:4,0);
315 : (0,160:58,0);
339 : (0,160:11,1);
77 : (0,158:4,0);
81 : (0,158:4,0);
86 : (0,159:36,0);
90 : (0,159:58,0);
91 : (0,159:75,0);
92 : (0,159:84,0);
94 : (0,159:84,0);
98 : (0,159:11,0);
99 : (0,159:11,1);
102 : (0,159:4,0);
106 : (0,159:4,1);
108 : (0,159:28,0);
192 : (0,158:4,0);
220 : (0,159:36,1);
248 : (0,159:4,0);
276 : (0,159:58,0);
303 : (0,158:4,0);
305 : (0,159:36,0);
311 : (0,159:4,0);
315 : (0,159:58,0);
339 : (0,159:11,1);

2
simulation/Release/chesswork/signal_path-750458.#
View File

@@ -11,3 +11,5 @@ c32d64301301b61633bc0c543dea27e53e53033a
0
0
0
0
0

2
simulation/Release/chesswork/signal_path-750458.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32

14
simulation/Release/chesswork/signal_path-9c02ae.#
View File

@@ -1,14 +1,10 @@
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
ac11bb208ce215cfbff1d17e7da4a6e4beeb0a71
c71e68f145851206b1c3315ab46f142e48093a19
da39a3ee5e6b4b0d3255bfef95601890afd80709
ba86b497a3de6671eb03ed7e1bc1c184ce6ac84a
301
bbe30e78d0212852e1fe4aeed35110a878ec3dd3
291
0
0
0
5
5
-1
-3
-10
-10

BIN
simulation/Release/chesswork/signal_path-9c02ae.o
View File

Binary file not shown.

294
simulation/Release/chesswork/signal_path-9c02ae.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 11:34:01 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -14,25 +14,25 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
frm : ( b=8 );
}
****
!! void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
fnm : "sig_init_preemph_coef" 'void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)';
!! void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
F_Z20scale_preemph_filterP16SingleSignalPathdddddi : user_defined, called {
fnm : "scale_preemph_filter" 'void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! int sig_init_delay(SingleSignalPath *, int)
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
!! int set_delay(SingleSignalPath *, int)
F_Z9set_delayP16SingleSignalPathi : user_defined, called {
fnm : "set_delay" 'int set_delay(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
!! void sig_init_weight(SingleSignalPath *, double, int)
F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
fnm : "sig_init_weight" 'void sig_init_weight(SingleSignalPath *, double, int)';
!! void set_weight(SingleSignalPath *, double, int)
F_Z10set_weightP16SingleSignalPathdi : user_defined, called {
fnm : "set_weight" 'void set_weight(SingleSignalPath *, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] RA[0] );
vac : ( srIM[0] );
@@ -84,29 +84,29 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
37 : pointer_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
37 : pointer_sample_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
38 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
39 : delay_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
40 : pointer_filter_coefficients typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
39 : sample_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
40 : pointer_coefficient_line typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
41 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
42 : filter_coefficients typ=int8_ bnd=e sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
42 : coefficient_line typ=int8_ bnd=e sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
43 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
44 : __extDM_int64_ typ=int8_ bnd=b stl=DM
45 : __extDM_void typ=int8_ bnd=b stl=DM
46 : __extPM_void typ=uint20_ bnd=b stl=PM
47 : pointer_delay_line_ptr_start typ=int8_ bnd=b stl=DM
47 : pointer_sample_line_ptr_start typ=int8_ bnd=b stl=DM
48 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
49 : pointer_filter_coefficients_ptr_start typ=int8_ bnd=b stl=DM
49 : pointer_coefficient_line_ptr_start typ=int8_ bnd=b stl=DM
50 : __rd___sp typ=dmaddr_ bnd=m
52 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=35
53 : __ptr_pointer_delay_line typ=dmaddr_ bnd=m
54 : __ptr_pointer_delay_line typ=dmaddr_ val=0a bnd=m adro=37
55 : __ptr_delay_line typ=dmaddr_ bnd=m
56 : __ptr_delay_line typ=dmaddr_ val=0a bnd=m adro=39
57 : __ptr_pointer_filter_coefficients typ=dmaddr_ bnd=m
58 : __ptr_pointer_filter_coefficients typ=dmaddr_ val=0a bnd=m adro=40
59 : __ptr_filter_coefficients typ=dmaddr_ bnd=m
60 : __ptr_filter_coefficients typ=dmaddr_ val=0a bnd=m adro=42
53 : __ptr_pointer_sample_line typ=dmaddr_ bnd=m
54 : __ptr_pointer_sample_line typ=dmaddr_ val=0a bnd=m adro=37
55 : __ptr_sample_line typ=dmaddr_ bnd=m
56 : __ptr_sample_line typ=dmaddr_ val=0a bnd=m adro=39
57 : __ptr_pointer_coefficient_line typ=dmaddr_ bnd=m
58 : __ptr_pointer_coefficient_line typ=dmaddr_ val=0a bnd=m adro=40
59 : __ptr_coefficient_line typ=dmaddr_ bnd=m
60 : __ptr_coefficient_line typ=dmaddr_ val=0a bnd=m adro=42
61 : __ct_0 typ=uint1_ val=0f bnd=m
62 : __la typ=dmaddr_ bnd=p tref=dmaddr___
63 : c_sensor_signal_t typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
@@ -127,13 +127,13 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
97 : __fch___extDM_int64_ typ=int64_ bnd=m
98 : __ct_31 typ=int32_ val=31f bnd=m
99 : __ct typ=int32_ bnd=m
100 : _Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=dmaddr_ val=0r bnd=m
100 : _Z20scale_preemph_filterP16SingleSignalPathdddddi typ=dmaddr_ val=0r bnd=m
102 : __link typ=dmaddr_ bnd=m
103 : _Z14sig_init_delayP16SingleSignalPathi typ=dmaddr_ val=0r bnd=m
103 : _Z9set_delayP16SingleSignalPathi typ=dmaddr_ val=0r bnd=m
105 : __link typ=dmaddr_ bnd=m
106 : __tmp typ=int32_ bnd=m
108 : __ct typ=int32_ bnd=m
109 : _Z15sig_init_weightP16SingleSignalPathdi typ=dmaddr_ val=0r bnd=m
109 : _Z10set_weightP16SingleSignalPathdi typ=dmaddr_ val=0r bnd=m
111 : __link typ=dmaddr_ bnd=m
115 : __fch___extDM_int64_ typ=int64_ bnd=m
119 : __fch___extDM_int64_ typ=int64_ bnd=m
@@ -159,13 +159,13 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
160 : __link typ=dmaddr_ bnd=m
161 : __tmp typ=int32_ bnd=m
164 : __tmp typ=bool bnd=m
170 : __fch_pointer_delay_line_ptr_start typ=dmaddr_ bnd=m
180 : __fch_pointer_filter_coefficients_ptr_start typ=dmaddr_ bnd=m
170 : __fch_pointer_sample_line_ptr_start typ=dmaddr_ bnd=m
180 : __fch_pointer_coefficient_line_ptr_start typ=dmaddr_ bnd=m
201 : __iv1_i typ=dmaddr_ bnd=m
202 : __iv2_i typ=dmaddr_ bnd=m
205 : __cv typ=uint16_ bnd=m
213 : __ptr_pointer_delay_line__a4 typ=dmaddr_ val=4a bnd=m adro=37
214 : __ptr_pointer_filter_coefficients__a4 typ=dmaddr_ val=4a bnd=m adro=40
213 : __ptr_pointer_sample_line__a4 typ=dmaddr_ val=4a bnd=m adro=37
214 : __ptr_pointer_coefficient_line__a4 typ=dmaddr_ val=4a bnd=m adro=40
217 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
248 : __ct_0S0 typ=int18_ val=-8S0 bnd=m
249 : __ct_0s0 typ=int18_ val=8s0 bnd=m
@@ -196,19 +196,19 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
(__sp.32 var=34) source () <56>;
(_ZL2mu.33 var=35) source () <57>;
(__extDM_int32_.34 var=36) source () <58>;
(pointer_delay_line.35 var=37) source () <59>;
(pointer_sample_line.35 var=37) source () <59>;
(__extDM_BufferPtrDMB.36 var=38) source () <60>;
(delay_line.37 var=39) source () <61>;
(pointer_filter_coefficients.38 var=40) source () <62>;
(sample_line.37 var=39) source () <61>;
(pointer_coefficient_line.38 var=40) source () <62>;
(__extDM_BufferPtr.39 var=41) source () <63>;
(filter_coefficients.40 var=42) source () <64>;
(coefficient_line.40 var=42) source () <64>;
(__extDM_SingleSignalPath.41 var=43) source () <65>;
(__extDM_int64_.42 var=44) source () <66>;
(__extDM_void.43 var=45) source () <67>;
(__extPM_void.44 var=46) source () <68>;
(pointer_delay_line_ptr_start.45 var=47) source () <69>;
(pointer_sample_line_ptr_start.45 var=47) source () <69>;
(__extDM___PDMint32_.46 var=48) source () <70>;
(pointer_filter_coefficients_ptr_start.47 var=49) source () <71>;
(pointer_coefficient_line_ptr_start.47 var=49) source () <71>;
(__ct_0.59 var=61) const () <83>;
(__la.61 var=62 stl=LR off=0) inp () <85>;
(__la.62 var=62) deassign (__la.61) <86>;
@@ -240,8 +240,8 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
(__fch___extDM_int64_.121 var=93) load (__M_LDMA.12 __rt.811 __extDM_int64_.42) <145>;
(__fch___extDM_int64_.126 var=97) load (__M_LDMA.12 __rt.833 __extDM_int64_.42) <150>;
(__ct_31.128 var=98) const () <152>;
(_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131 var=100) const () <155>;
(__link.133 var=102) dmaddr__call_dmaddr_ (_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131) <157>;
(_Z20scale_preemph_filterP16SingleSignalPathdddddi.131 var=100) const () <155>;
(__link.133 var=102) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <157>;
(__rt.679 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.94 __ct_0S0.934) <617>;
(__rt.767 var=217) __Pvoid__pl___Pvoid_int18_ (b_c.71 __ct_8.937) <729>;
(__rt.789 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.767 __ct_8.937) <757>;
@@ -258,26 +258,26 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
(__fch___extDM_int64_.127 var=97 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.126) <151>;
(__ct.130 var=99 stl=RA off=0) assign (__ct_31.128) <154>;
(__link.134 var=102 stl=LR off=0) assign (__link.133) <158>;
(_ZL2mu.135 var=35 __extDM.136 var=32 __extDM_BufferPtr.137 var=41 __extDM_BufferPtrDMB.138 var=38 __extDM_SingleSignalPath.139 var=43 __extDM___PDMint32_.140 var=48 __extDM_int32_.141 var=36 __extDM_int64_.142 var=44 __extDM_void.143 var=45 __extPM.144 var=33 __extPM_void.145 var=46 delay_line.146 var=39 filter_coefficients.147 var=42 pointer_delay_line.148 var=37 pointer_delay_line_ptr_start.149 var=47 pointer_filter_coefficients.150 var=40 pointer_filter_coefficients_ptr_start.151 var=49 __vola.152 var=29) F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi (__link.134 c_sensor_signal_t.102 __fch___extDM_int64_.107 __fch___extDM_int64_.112 __fch___extDM_int64_.117 __fch___extDM_int64_.122 __fch___extDM_int64_.127 __ct.130 _ZL2mu.33 __extDM.30 __extDM_BufferPtr.39 __extDM_BufferPtrDMB.36 __extDM_SingleSignalPath.41 __extDM___PDMint32_.46 __extDM_int32_.34 __extDM_int64_.42 __extDM_void.43 __extPM.31 __extPM_void.44 delay_line.37 filter_coefficients.40 pointer_delay_line.35 pointer_delay_line_ptr_start.45 pointer_filter_coefficients.38 pointer_filter_coefficients_ptr_start.47 __vola.27) <159>;
(_ZL2mu.135 var=35 __extDM.136 var=32 __extDM_BufferPtr.137 var=41 __extDM_BufferPtrDMB.138 var=38 __extDM_SingleSignalPath.139 var=43 __extDM___PDMint32_.140 var=48 __extDM_int32_.141 var=36 __extDM_int64_.142 var=44 __extDM_void.143 var=45 __extPM.144 var=33 __extPM_void.145 var=46 coefficient_line.146 var=42 pointer_coefficient_line.147 var=40 pointer_coefficient_line_ptr_start.148 var=49 pointer_sample_line.149 var=37 pointer_sample_line_ptr_start.150 var=47 sample_line.151 var=39 __vola.152 var=29) F_Z20scale_preemph_filterP16SingleSignalPathdddddi (__link.134 c_sensor_signal_t.102 __fch___extDM_int64_.107 __fch___extDM_int64_.112 __fch___extDM_int64_.117 __fch___extDM_int64_.122 __fch___extDM_int64_.127 __ct.130 _ZL2mu.33 __extDM.30 __extDM_BufferPtr.39 __extDM_BufferPtrDMB.36 __extDM_SingleSignalPath.41 __extDM___PDMint32_.46 __extDM_int32_.34 __extDM_int64_.42 __extDM_void.43 __extPM.31 __extPM_void.44 coefficient_line.40 pointer_coefficient_line.38 pointer_coefficient_line_ptr_start.47 pointer_sample_line.35 pointer_sample_line_ptr_start.45 sample_line.37 __vola.27) <159>;
} #4 off=1
#5 off=2
(_Z14sig_init_delayP16SingleSignalPathi.155 var=103) const () <162>;
(__link.157 var=105) dmaddr__call_dmaddr_ (_Z14sig_init_delayP16SingleSignalPathi.155) <164>;
(_Z9set_delayP16SingleSignalPathi.155 var=103) const () <162>;
(__link.157 var=105) dmaddr__call_dmaddr_ (_Z9set_delayP16SingleSignalPathi.155) <164>;
call {
(c_sensor_signal_t.153 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <160>;
(delay_c.154 var=67 stl=RA off=1) assign (delay_c.77) <161>;
(__link.158 var=105 stl=LR off=0) assign (__link.157) <165>;
(__tmp.159 var=106 stl=RA off=0 _ZL2mu.162 var=35 __extDM.163 var=32 __extDM_BufferPtr.164 var=41 __extDM_BufferPtrDMB.165 var=38 __extDM_SingleSignalPath.166 var=43 __extDM___PDMint32_.167 var=48 __extDM_int32_.168 var=36 __extDM_int64_.169 var=44 __extDM_void.170 var=45 __extPM.171 var=33 __extPM_void.172 var=46 delay_line.173 var=39 filter_coefficients.174 var=42 pointer_delay_line.175 var=37 pointer_delay_line_ptr_start.176 var=47 pointer_filter_coefficients.177 var=40 pointer_filter_coefficients_ptr_start.178 var=49 __vola.179 var=29) F_Z14sig_init_delayP16SingleSignalPathi (__link.158 c_sensor_signal_t.153 delay_c.154 _ZL2mu.135 __extDM.136 __extDM_BufferPtr.137 __extDM_BufferPtrDMB.138 __extDM_SingleSignalPath.139 __extDM___PDMint32_.140 __extDM_int32_.141 __extDM_int64_.142 __extDM_void.143 __extPM.144 __extPM_void.145 delay_line.146 filter_coefficients.147 pointer_delay_line.148 pointer_delay_line_ptr_start.149 pointer_filter_coefficients.150 pointer_filter_coefficients_ptr_start.151 __vola.152) <166>;
(__tmp.159 var=106 stl=RA off=0 _ZL2mu.162 var=35 __extDM.163 var=32 __extDM_BufferPtr.164 var=41 __extDM_BufferPtrDMB.165 var=38 __extDM_SingleSignalPath.166 var=43 __extDM___PDMint32_.167 var=48 __extDM_int32_.168 var=36 __extDM_int64_.169 var=44 __extDM_void.170 var=45 __extPM.171 var=33 __extPM_void.172 var=46 coefficient_line.173 var=42 pointer_coefficient_line.174 var=40 pointer_coefficient_line_ptr_start.175 var=49 pointer_sample_line.176 var=37 pointer_sample_line_ptr_start.177 var=47 sample_line.178 var=39 __vola.179 var=29) F_Z9set_delayP16SingleSignalPathi (__link.158 c_sensor_signal_t.153 delay_c.154 _ZL2mu.135 __extDM.136 __extDM_BufferPtr.137 __extDM_BufferPtrDMB.138 __extDM_SingleSignalPath.139 __extDM___PDMint32_.140 __extDM_int32_.141 __extDM_int64_.142 __extDM_void.143 __extPM.144 __extPM_void.145 coefficient_line.146 pointer_coefficient_line.147 pointer_coefficient_line_ptr_start.148 pointer_sample_line.149 pointer_sample_line_ptr_start.150 sample_line.151 __vola.152) <166>;
} #6 off=3
#7 off=4
(_Z15sig_init_weightP16SingleSignalPathdi.185 var=109) const () <174>;
(__link.187 var=111) dmaddr__call_dmaddr_ (_Z15sig_init_weightP16SingleSignalPathdi.185) <176>;
(_Z10set_weightP16SingleSignalPathdi.185 var=109) const () <174>;
(__link.187 var=111) dmaddr__call_dmaddr_ (_Z10set_weightP16SingleSignalPathdi.185) <176>;
call {
(c_sensor_signal_t.180 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <169>;
(weight_c.181 var=69 stl=AX off=0) assign (weight_c.83) <170>;
(__ct.184 var=108 stl=RA off=0) assign (__ct_31.128) <173>;
(__link.188 var=111 stl=LR off=0) assign (__link.187) <177>;
(_ZL2mu.189 var=35 __extDM.190 var=32 __extDM_BufferPtr.191 var=41 __extDM_BufferPtrDMB.192 var=38 __extDM_SingleSignalPath.193 var=43 __extDM___PDMint32_.194 var=48 __extDM_int32_.195 var=36 __extDM_int64_.196 var=44 __extDM_void.197 var=45 __extPM.198 var=33 __extPM_void.199 var=46 delay_line.200 var=39 filter_coefficients.201 var=42 pointer_delay_line.202 var=37 pointer_delay_line_ptr_start.203 var=47 pointer_filter_coefficients.204 var=40 pointer_filter_coefficients_ptr_start.205 var=49 __vola.206 var=29) F_Z15sig_init_weightP16SingleSignalPathdi (__link.188 c_sensor_signal_t.180 weight_c.181 __ct.184 _ZL2mu.162 __extDM.163 __extDM_BufferPtr.164 __extDM_BufferPtrDMB.165 __extDM_SingleSignalPath.166 __extDM___PDMint32_.167 __extDM_int32_.168 __extDM_int64_.169 __extDM_void.170 __extPM.171 __extPM_void.172 delay_line.173 filter_coefficients.174 pointer_delay_line.175 pointer_delay_line_ptr_start.176 pointer_filter_coefficients.177 pointer_filter_coefficients_ptr_start.178 __vola.179) <178>;
(_ZL2mu.189 var=35 __extDM.190 var=32 __extDM_BufferPtr.191 var=41 __extDM_BufferPtrDMB.192 var=38 __extDM_SingleSignalPath.193 var=43 __extDM___PDMint32_.194 var=48 __extDM_int32_.195 var=36 __extDM_int64_.196 var=44 __extDM_void.197 var=45 __extPM.198 var=33 __extPM_void.199 var=46 coefficient_line.200 var=42 pointer_coefficient_line.201 var=40 pointer_coefficient_line_ptr_start.202 var=49 pointer_sample_line.203 var=37 pointer_sample_line_ptr_start.204 var=47 sample_line.205 var=39 __vola.206 var=29) F_Z10set_weightP16SingleSignalPathdi (__link.188 c_sensor_signal_t.180 weight_c.181 __ct.184 _ZL2mu.162 __extDM.163 __extDM_BufferPtr.164 __extDM_BufferPtrDMB.165 __extDM_SingleSignalPath.166 __extDM___PDMint32_.167 __extDM_int32_.168 __extDM_int64_.169 __extDM_void.170 __extPM.171 __extPM_void.172 coefficient_line.173 pointer_coefficient_line.174 pointer_coefficient_line_ptr_start.175 pointer_sample_line.176 pointer_sample_line_ptr_start.177 sample_line.178 __vola.179) <178>;
} #8 off=5
#370 off=6
(__fch___extDM_int64_.211 var=115) load (__M_LDMA.12 b_acc.74 __extDM_int64_.196) <183>;
@@ -285,7 +285,7 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
(__fch___extDM_int64_.221 var=123) load (__M_LDMA.12 __rt.877 __extDM_int64_.196) <193>;
(__fch___extDM_int64_.226 var=127) load (__M_LDMA.12 __rt.899 __extDM_int64_.196) <198>;
(__fch___extDM_int64_.231 var=131) load (__M_LDMA.12 __rt.921 __extDM_int64_.196) <203>;
(__link.238 var=136) dmaddr__call_dmaddr_ (_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131) <210>;
(__link.238 var=136) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <210>;
(__rt.855 var=217) __Pvoid__pl___Pvoid_int18_ (b_acc.74 __ct_8.937) <841>;
(__rt.877 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.855 __ct_8.937) <869>;
(__rt.899 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.877 __ct_8.937) <897>;
@@ -299,24 +299,24 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
(__fch___extDM_int64_.232 var=131 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.231) <204>;
(__ct.235 var=133 stl=RA off=0) assign (__ct_31.128) <207>;
(__link.239 var=136 stl=LR off=0) assign (__link.238) <211>;
(_ZL2mu.240 var=35 __extDM.241 var=32 __extDM_BufferPtr.242 var=41 __extDM_BufferPtrDMB.243 var=38 __extDM_SingleSignalPath.244 var=43 __extDM___PDMint32_.245 var=48 __extDM_int32_.246 var=36 __extDM_int64_.247 var=44 __extDM_void.248 var=45 __extPM.249 var=33 __extPM_void.250 var=46 delay_line.251 var=39 filter_coefficients.252 var=42 pointer_delay_line.253 var=37 pointer_delay_line_ptr_start.254 var=47 pointer_filter_coefficients.255 var=40 pointer_filter_coefficients_ptr_start.256 var=49 __vola.257 var=29) F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi (__link.239 acc_sensor_signal_t.207 __fch___extDM_int64_.212 __fch___extDM_int64_.217 __fch___extDM_int64_.222 __fch___extDM_int64_.227 __fch___extDM_int64_.232 __ct.235 _ZL2mu.189 __extDM.190 __extDM_BufferPtr.191 __extDM_BufferPtrDMB.192 __extDM_SingleSignalPath.193 __extDM___PDMint32_.194 __extDM_int32_.195 __extDM_int64_.196 __extDM_void.197 __extPM.198 __extPM_void.199 delay_line.200 filter_coefficients.201 pointer_delay_line.202 pointer_delay_line_ptr_start.203 pointer_filter_coefficients.204 pointer_filter_coefficients_ptr_start.205 __vola.206) <212>;
(_ZL2mu.240 var=35 __extDM.241 var=32 __extDM_BufferPtr.242 var=41 __extDM_BufferPtrDMB.243 var=38 __extDM_SingleSignalPath.244 var=43 __extDM___PDMint32_.245 var=48 __extDM_int32_.246 var=36 __extDM_int64_.247 var=44 __extDM_void.248 var=45 __extPM.249 var=33 __extPM_void.250 var=46 coefficient_line.251 var=42 pointer_coefficient_line.252 var=40 pointer_coefficient_line_ptr_start.253 var=49 pointer_sample_line.254 var=37 pointer_sample_line_ptr_start.255 var=47 sample_line.256 var=39 __vola.257 var=29) F_Z20scale_preemph_filterP16SingleSignalPathdddddi (__link.239 acc_sensor_signal_t.207 __fch___extDM_int64_.212 __fch___extDM_int64_.217 __fch___extDM_int64_.222 __fch___extDM_int64_.227 __fch___extDM_int64_.232 __ct.235 _ZL2mu.189 __extDM.190 __extDM_BufferPtr.191 __extDM_BufferPtrDMB.192 __extDM_SingleSignalPath.193 __extDM___PDMint32_.194 __extDM_int32_.195 __extDM_int64_.196 __extDM_void.197 __extPM.198 __extPM_void.199 coefficient_line.200 pointer_coefficient_line.201 pointer_coefficient_line_ptr_start.202 pointer_sample_line.203 pointer_sample_line_ptr_start.204 sample_line.205 __vola.206) <212>;
} #10 off=7
#11 off=8
(__link.262 var=139) dmaddr__call_dmaddr_ (_Z14sig_init_delayP16SingleSignalPathi.155) <217>;
(__link.262 var=139) dmaddr__call_dmaddr_ (_Z9set_delayP16SingleSignalPathi.155) <217>;
call {
(acc_sensor_signal_t.258 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <213>;
(delay_acc.259 var=68 stl=RA off=1) assign (delay_acc.80) <214>;
(__link.263 var=139 stl=LR off=0) assign (__link.262) <218>;
(__tmp.264 var=140 stl=RA off=0 _ZL2mu.267 var=35 __extDM.268 var=32 __extDM_BufferPtr.269 var=41 __extDM_BufferPtrDMB.270 var=38 __extDM_SingleSignalPath.271 var=43 __extDM___PDMint32_.272 var=48 __extDM_int32_.273 var=36 __extDM_int64_.274 var=44 __extDM_void.275 var=45 __extPM.276 var=33 __extPM_void.277 var=46 delay_line.278 var=39 filter_coefficients.279 var=42 pointer_delay_line.280 var=37 pointer_delay_line_ptr_start.281 var=47 pointer_filter_coefficients.282 var=40 pointer_filter_coefficients_ptr_start.283 var=49 __vola.284 var=29) F_Z14sig_init_delayP16SingleSignalPathi (__link.263 acc_sensor_signal_t.258 delay_acc.259 _ZL2mu.240 __extDM.241 __extDM_BufferPtr.242 __extDM_BufferPtrDMB.243 __extDM_SingleSignalPath.244 __extDM___PDMint32_.245 __extDM_int32_.246 __extDM_int64_.247 __extDM_void.248 __extPM.249 __extPM_void.250 delay_line.251 filter_coefficients.252 pointer_delay_line.253 pointer_delay_line_ptr_start.254 pointer_filter_coefficients.255 pointer_filter_coefficients_ptr_start.256 __vola.257) <219>;
(__tmp.264 var=140 stl=RA off=0 _ZL2mu.267 var=35 __extDM.268 var=32 __extDM_BufferPtr.269 var=41 __extDM_BufferPtrDMB.270 var=38 __extDM_SingleSignalPath.271 var=43 __extDM___PDMint32_.272 var=48 __extDM_int32_.273 var=36 __extDM_int64_.274 var=44 __extDM_void.275 var=45 __extPM.276 var=33 __extPM_void.277 var=46 coefficient_line.278 var=42 pointer_coefficient_line.279 var=40 pointer_coefficient_line_ptr_start.280 var=49 pointer_sample_line.281 var=37 pointer_sample_line_ptr_start.282 var=47 sample_line.283 var=39 __vola.284 var=29) F_Z9set_delayP16SingleSignalPathi (__link.263 acc_sensor_signal_t.258 delay_acc.259 _ZL2mu.240 __extDM.241 __extDM_BufferPtr.242 __extDM_BufferPtrDMB.243 __extDM_SingleSignalPath.244 __extDM___PDMint32_.245 __extDM_int32_.246 __extDM_int64_.247 __extDM_void.248 __extPM.249 __extPM_void.250 coefficient_line.251 pointer_coefficient_line.252 pointer_coefficient_line_ptr_start.253 pointer_sample_line.254 pointer_sample_line_ptr_start.255 sample_line.256 __vola.257) <219>;
} #12 off=9
#13 off=10
(__link.292 var=145) dmaddr__call_dmaddr_ (_Z15sig_init_weightP16SingleSignalPathdi.185) <229>;
(__link.292 var=145) dmaddr__call_dmaddr_ (_Z10set_weightP16SingleSignalPathdi.185) <229>;
call {
(acc_sensor_signal_t.285 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <222>;
(weight_acc.286 var=70 stl=AX off=0) assign (weight_acc.86) <223>;
(__ct.289 var=142 stl=RA off=0) assign (__ct_31.128) <226>;
(__link.293 var=145 stl=LR off=0) assign (__link.292) <230>;
(_ZL2mu.294 var=35 __extDM.295 var=32 __extDM_BufferPtr.296 var=41 __extDM_BufferPtrDMB.297 var=38 __extDM_SingleSignalPath.298 var=43 __extDM___PDMint32_.299 var=48 __extDM_int32_.300 var=36 __extDM_int64_.301 var=44 __extDM_void.302 var=45 __extPM.303 var=33 __extPM_void.304 var=46 delay_line.305 var=39 filter_coefficients.306 var=42 pointer_delay_line.307 var=37 pointer_delay_line_ptr_start.308 var=47 pointer_filter_coefficients.309 var=40 pointer_filter_coefficients_ptr_start.310 var=49 __vola.311 var=29) F_Z15sig_init_weightP16SingleSignalPathdi (__link.293 acc_sensor_signal_t.285 weight_acc.286 __ct.289 _ZL2mu.267 __extDM.268 __extDM_BufferPtr.269 __extDM_BufferPtrDMB.270 __extDM_SingleSignalPath.271 __extDM___PDMint32_.272 __extDM_int32_.273 __extDM_int64_.274 __extDM_void.275 __extPM.276 __extPM_void.277 delay_line.278 filter_coefficients.279 pointer_delay_line.280 pointer_delay_line_ptr_start.281 pointer_filter_coefficients.282 pointer_filter_coefficients_ptr_start.283 __vola.284) <231>;
(_ZL2mu.294 var=35 __extDM.295 var=32 __extDM_BufferPtr.296 var=41 __extDM_BufferPtrDMB.297 var=38 __extDM_SingleSignalPath.298 var=43 __extDM___PDMint32_.299 var=48 __extDM_int32_.300 var=36 __extDM_int64_.301 var=44 __extDM_void.302 var=45 __extPM.303 var=33 __extPM_void.304 var=46 coefficient_line.305 var=42 pointer_coefficient_line.306 var=40 pointer_coefficient_line_ptr_start.307 var=49 pointer_sample_line.308 var=37 pointer_sample_line_ptr_start.309 var=47 sample_line.310 var=39 __vola.311 var=29) F_Z10set_weightP16SingleSignalPathdi (__link.293 acc_sensor_signal_t.285 weight_acc.286 __ct.289 _ZL2mu.267 __extDM.268 __extDM_BufferPtr.269 __extDM_BufferPtrDMB.270 __extDM_SingleSignalPath.271 __extDM___PDMint32_.272 __extDM_int32_.273 __extDM_int64_.274 __extDM_void.275 __extPM.276 __extPM_void.277 coefficient_line.278 pointer_coefficient_line.279 pointer_coefficient_line_ptr_start.280 pointer_sample_line.281 pointer_sample_line_ptr_start.282 sample_line.283 __vola.284) <231>;
} #14 off=11
#474 off=12
(__ct_4746794007244308480.312 var=146) const () <232>;
@@ -340,32 +340,32 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
} #481 off=15
#471 off=16
(__ptr_mu.49 var=52) const () <73>;
(__ptr_pointer_delay_line.51 var=54) const () <75>;
(__ptr_delay_line.53 var=56) const () <77>;
(__ptr_pointer_sample_line.51 var=54) const () <75>;
(__ptr_sample_line.53 var=56) const () <77>;
(__M_WDMA.316 var=11 _ZL2mu.317 var=35) store (__tmp.968 __ptr_mu.49 _ZL2mu.294) <236>;
(__ct_64.321 var=150) const () <240>;
(_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324 var=152) const () <243>;
(__link.326 var=154) dmaddr__call_dmaddr_ (_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324) <245>;
call {
(__ptr_pointer_delay_line.318 var=53 stl=A off=4) assign (__ptr_pointer_delay_line.51) <237>;
(__ptr_delay_line.319 var=55 stl=A off=5) assign (__ptr_delay_line.53) <238>;
(__ptr_pointer_sample_line.318 var=53 stl=A off=4) assign (__ptr_pointer_sample_line.51) <237>;
(__ptr_sample_line.319 var=55 stl=A off=5) assign (__ptr_sample_line.53) <238>;
(number_coefficients.320 var=72 stl=RA off=1) assign (number_coefficients.92) <239>;
(__ct.323 var=151 stl=RB off=0) assign (__ct_64.321) <242>;
(__link.327 var=154 stl=LR off=0) assign (__link.326) <246>;
(__tmp.328 var=155 stl=RA off=0 _ZL2mu.331 var=35 __extDM.332 var=32 __extDM_BufferPtr.333 var=41 __extDM_BufferPtrDMB.334 var=38 __extDM_SingleSignalPath.335 var=43 __extDM___PDMint32_.336 var=48 __extDM_int32_.337 var=36 __extDM_int64_.338 var=44 __extDM_void.339 var=45 __extPM.340 var=33 __extPM_void.341 var=46 delay_line.342 var=39 filter_coefficients.343 var=42 pointer_delay_line.344 var=37 pointer_delay_line_ptr_start.345 var=47 pointer_filter_coefficients.346 var=40 pointer_filter_coefficients_ptr_start.347 var=49 __vola.348 var=29) F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii (__link.327 __ptr_pointer_delay_line.318 __ptr_delay_line.319 number_coefficients.320 __ct.323 _ZL2mu.317 __extDM.295 __extDM_BufferPtr.296 __extDM_BufferPtrDMB.297 __extDM_SingleSignalPath.298 __extDM___PDMint32_.299 __extDM_int32_.300 __extDM_int64_.301 __extDM_void.302 __extPM.303 __extPM_void.304 delay_line.305 filter_coefficients.306 pointer_delay_line.307 pointer_delay_line_ptr_start.308 pointer_filter_coefficients.309 pointer_filter_coefficients_ptr_start.310 __vola.311) <247>;
(__tmp.328 var=155 stl=RA off=0 _ZL2mu.331 var=35 __extDM.332 var=32 __extDM_BufferPtr.333 var=41 __extDM_BufferPtrDMB.334 var=38 __extDM_SingleSignalPath.335 var=43 __extDM___PDMint32_.336 var=48 __extDM_int32_.337 var=36 __extDM_int64_.338 var=44 __extDM_void.339 var=45 __extPM.340 var=33 __extPM_void.341 var=46 coefficient_line.342 var=42 pointer_coefficient_line.343 var=40 pointer_coefficient_line_ptr_start.344 var=49 pointer_sample_line.345 var=37 pointer_sample_line_ptr_start.346 var=47 sample_line.347 var=39 __vola.348 var=29) F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii (__link.327 __ptr_pointer_sample_line.318 __ptr_sample_line.319 number_coefficients.320 __ct.323 _ZL2mu.317 __extDM.295 __extDM_BufferPtr.296 __extDM_BufferPtrDMB.297 __extDM_SingleSignalPath.298 __extDM___PDMint32_.299 __extDM_int32_.300 __extDM_int64_.301 __extDM_void.302 __extPM.303 __extPM_void.304 coefficient_line.305 pointer_coefficient_line.306 pointer_coefficient_line_ptr_start.307 pointer_sample_line.308 pointer_sample_line_ptr_start.309 sample_line.310 __vola.311) <247>;
} #16 off=17
#17 off=18
(__ptr_pointer_filter_coefficients.55 var=58) const () <79>;
(__ptr_filter_coefficients.57 var=60) const () <81>;
(__ptr_pointer_coefficient_line.55 var=58) const () <79>;
(__ptr_coefficient_line.57 var=60) const () <81>;
(_Z17initialize_bufferP9BufferPtrPiii.355 var=158) const () <256>;
(__link.357 var=160) dmaddr__call_dmaddr_ (_Z17initialize_bufferP9BufferPtrPiii.355) <258>;
call {
(__ptr_pointer_filter_coefficients.349 var=57 stl=A off=0) assign (__ptr_pointer_filter_coefficients.55) <250>;
(__ptr_filter_coefficients.350 var=59 stl=A off=1) assign (__ptr_filter_coefficients.57) <251>;
(__ptr_pointer_coefficient_line.349 var=57 stl=A off=0) assign (__ptr_pointer_coefficient_line.55) <250>;
(__ptr_coefficient_line.350 var=59 stl=A off=1) assign (__ptr_coefficient_line.57) <251>;
(number_coefficients.351 var=72 stl=RA off=1) assign (number_coefficients.92) <252>;
(__ct.354 var=157 stl=RB off=0) assign (__ct_64.321) <255>;
(__link.358 var=160 stl=LR off=0) assign (__link.357) <259>;
(__tmp.359 var=161 stl=RA off=0 _ZL2mu.362 var=35 __extDM.363 var=32 __extDM_BufferPtr.364 var=41 __extDM_BufferPtrDMB.365 var=38 __extDM_SingleSignalPath.366 var=43 __extDM___PDMint32_.367 var=48 __extDM_int32_.368 var=36 __extDM_int64_.369 var=44 __extDM_void.370 var=45 __extPM.371 var=33 __extPM_void.372 var=46 delay_line.373 var=39 filter_coefficients.374 var=42 pointer_delay_line.375 var=37 pointer_delay_line_ptr_start.376 var=47 pointer_filter_coefficients.377 var=40 pointer_filter_coefficients_ptr_start.378 var=49 __vola.379 var=29) F_Z17initialize_bufferP9BufferPtrPiii (__link.358 __ptr_pointer_filter_coefficients.349 __ptr_filter_coefficients.350 number_coefficients.351 __ct.354 _ZL2mu.331 __extDM.332 __extDM_BufferPtr.333 __extDM_BufferPtrDMB.334 __extDM_SingleSignalPath.335 __extDM___PDMint32_.336 __extDM_int32_.337 __extDM_int64_.338 __extDM_void.339 __extPM.340 __extPM_void.341 delay_line.342 filter_coefficients.343 pointer_delay_line.344 pointer_delay_line_ptr_start.345 pointer_filter_coefficients.346 pointer_filter_coefficients_ptr_start.347 __vola.348) <260>;
(__tmp.359 var=161 stl=RA off=0 _ZL2mu.362 var=35 __extDM.363 var=32 __extDM_BufferPtr.364 var=41 __extDM_BufferPtrDMB.365 var=38 __extDM_SingleSignalPath.366 var=43 __extDM___PDMint32_.367 var=48 __extDM_int32_.368 var=36 __extDM_int64_.369 var=44 __extDM_void.370 var=45 __extPM.371 var=33 __extPM_void.372 var=46 coefficient_line.373 var=42 pointer_coefficient_line.374 var=40 pointer_coefficient_line_ptr_start.375 var=49 pointer_sample_line.376 var=37 pointer_sample_line_ptr_start.377 var=47 sample_line.378 var=39 __vola.379 var=29) F_Z17initialize_bufferP9BufferPtrPiii (__link.358 __ptr_pointer_coefficient_line.349 __ptr_coefficient_line.350 number_coefficients.351 __ct.354 _ZL2mu.331 __extDM.332 __extDM_BufferPtr.333 __extDM_BufferPtrDMB.334 __extDM_SingleSignalPath.335 __extDM___PDMint32_.336 __extDM_int32_.337 __extDM_int64_.338 __extDM_void.339 __extPM.340 __extPM_void.341 coefficient_line.342 pointer_coefficient_line.343 pointer_coefficient_line_ptr_start.344 pointer_sample_line.345 pointer_sample_line_ptr_start.346 sample_line.347 __vola.348) <260>;
} #18 off=19
#466 off=20
(__ct_0.103 var=78) const () <127>;
@@ -386,11 +386,11 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
} #27 off=24
{
#34 off=21
(__fch_pointer_delay_line_ptr_start.467 var=170) load (__M_WDMB.10 __ptr_pointer_delay_line__a4.664 pointer_delay_line_ptr_start.376) <352>;
(__fch_pointer_filter_coefficients_ptr_start.482 var=180) load (__M_WDMA.9 __ptr_pointer_filter_coefficients__a4.665 pointer_filter_coefficients_ptr_start.378) <363>;
(__fch_pointer_sample_line_ptr_start.467 var=170) load (__M_WDMB.10 __ptr_pointer_sample_line__a4.664 pointer_sample_line_ptr_start.377) <352>;
(__fch_pointer_coefficient_line_ptr_start.482 var=180) load (__M_WDMA.9 __ptr_pointer_coefficient_line__a4.665 pointer_coefficient_line_ptr_start.375) <363>;
(__cv.649 var=205) uint16__uint16____sint (number_coefficients.92) <558>;
(__ptr_pointer_delay_line__a4.664 var=213) const () <574>;
(__ptr_pointer_filter_coefficients__a4.665 var=214) const () <576>;
(__ptr_pointer_sample_line__a4.664 var=213) const () <574>;
(__ptr_pointer_coefficient_line__a4.665 var=214) const () <576>;
(__ct_4.936 var=250) const () <969>;
(__trgt.981 var=288) const () <1132>;
() void_doloop_uint16__uint16_ (__cv.649 __trgt.981) <1133>;
@@ -399,14 +399,14 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
{
(_ZL2mu.429 var=35) entry (_ZL2mu.508 _ZL2mu.362) <314>;
(__extDM_int32_.430 var=36) entry (__extDM_int32_.510 __extDM_int32_.368) <315>;
(delay_line.433 var=39) entry (delay_line.516 delay_line.373) <318>;
(filter_coefficients.436 var=42) entry (filter_coefficients.522 filter_coefficients.374) <321>;
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_pointer_delay_line_ptr_start.467) <545>;
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_pointer_filter_coefficients_ptr_start.482) <549>;
(sample_line.433 var=39) entry (sample_line.516 sample_line.378) <318>;
(coefficient_line.436 var=42) entry (coefficient_line.522 coefficient_line.373) <321>;
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_pointer_sample_line_ptr_start.467) <545>;
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_pointer_coefficient_line_ptr_start.482) <549>;
} #24
{
(__M_WDMB.472 var=12 _ZL2mu.473 var=35 __extDM_int32_.474 var=36 delay_line.475 var=39 filter_coefficients.476 var=42) store (__ct_0.103 __iv1_i.635 _ZL2mu.429 __extDM_int32_.430 delay_line.433 filter_coefficients.436) <357>;
(__M_WDMA.487 var=11 _ZL2mu.488 var=35 __extDM_int32_.489 var=36 delay_line.490 var=39 filter_coefficients.491 var=42) store (__ct_0.103 __iv2_i.640 _ZL2mu.473 __extDM_int32_.474 delay_line.475 filter_coefficients.476) <368>;
(__M_WDMB.472 var=12 _ZL2mu.473 var=35 __extDM_int32_.474 var=36 coefficient_line.475 var=42 sample_line.476 var=39) store (__ct_0.103 __iv1_i.635 _ZL2mu.429 __extDM_int32_.430 coefficient_line.436 sample_line.433) <357>;
(__M_WDMA.487 var=11 _ZL2mu.488 var=35 __extDM_int32_.489 var=36 coefficient_line.490 var=42 sample_line.491 var=39) store (__ct_0.103 __iv2_i.640 _ZL2mu.473 __extDM_int32_.474 coefficient_line.475 sample_line.476) <368>;
(__rt.723 var=217) __Pvoid__pl___Pvoid_int18_ (__iv1_i.635 __ct_4.936) <673>;
(__rt.745 var=217) __Pvoid__pl___Pvoid_int18_ (__iv2_i.640 __ct_4.936) <701>;
} #256 off=22
@@ -414,8 +414,8 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
() for_count (__vcnt.982) <373>;
(_ZL2mu.508 var=35 _ZL2mu.509 var=35) exit (_ZL2mu.488) <380>;
(__extDM_int32_.510 var=36 __extDM_int32_.511 var=36) exit (__extDM_int32_.489) <381>;
(delay_line.516 var=39 delay_line.517 var=39) exit (delay_line.490) <384>;
(filter_coefficients.522 var=42 filter_coefficients.523 var=42) exit (filter_coefficients.491) <387>;
(sample_line.516 var=39 sample_line.517 var=39) exit (sample_line.491) <384>;
(coefficient_line.522 var=42 coefficient_line.523 var=42) exit (coefficient_line.490) <387>;
(__iv1_i.636 var=201 __iv1_i.637 var=201) exit (__rt.723) <546>;
(__iv2_i.641 var=202 __iv2_i.642 var=202) exit (__rt.745) <550>;
} #26
@@ -424,8 +424,8 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
{
(_ZL2mu.574 var=35) merge (_ZL2mu.362 _ZL2mu.509) <413>;
(__extDM_int32_.575 var=36) merge (__extDM_int32_.368 __extDM_int32_.511) <414>;
(delay_line.576 var=39) merge (delay_line.373 delay_line.517) <415>;
(filter_coefficients.577 var=42) merge (filter_coefficients.374 filter_coefficients.523) <416>;
(sample_line.576 var=39) merge (sample_line.378 sample_line.517) <415>;
(coefficient_line.577 var=42) merge (coefficient_line.373 coefficient_line.523) <416>;
} #28
} #20
#30 off=25 nxt=-2
@@ -438,19 +438,19 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
() sink (__sp.585) <430>;
() sink (_ZL2mu.574) <431>;
() sink (__extDM_int32_.575) <432>;
() sink (pointer_delay_line.375) <433>;
() sink (pointer_sample_line.376) <433>;
() sink (__extDM_BufferPtrDMB.365) <434>;
() sink (delay_line.576) <435>;
() sink (pointer_filter_coefficients.377) <436>;
() sink (sample_line.576) <435>;
() sink (pointer_coefficient_line.374) <436>;
() sink (__extDM_BufferPtr.364) <437>;
() sink (filter_coefficients.577) <438>;
() sink (coefficient_line.577) <438>;
() sink (__extDM_SingleSignalPath.366) <439>;
() sink (__extDM_int64_.369) <440>;
() sink (__extDM_void.370) <441>;
() sink (__extPM_void.372) <442>;
() sink (pointer_delay_line_ptr_start.376) <443>;
() sink (pointer_sample_line_ptr_start.377) <443>;
() sink (__extDM___PDMint32_.367) <444>;
() sink (pointer_filter_coefficients_ptr_start.378) <445>;
() sink (pointer_coefficient_line_ptr_start.375) <445>;
() sink (__ct_0.59) <446>;
(__rt.701 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.580 __ct_0s0.935) <645>;
(__ct_0s0.935 var=249) const () <967>;
@@ -459,17 +459,17 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
----------
0 : (0,291:0,0);
4 : (0,306:4,2);
5 : (0,307:38,3);
5 : (0,307:33,3);
6 : (0,307:4,3);
7 : (0,308:49,4);
7 : (0,308:44,4);
8 : (0,308:4,4);
10 : (0,311:4,5);
11 : (0,312:40,6);
11 : (0,312:35,6);
12 : (0,312:4,6);
13 : (0,313:53,7);
13 : (0,313:48,7);
14 : (0,313:4,7);
16 : (0,319:4,10);
17 : (0,320:94,11);
17 : (0,320:88,11);
18 : (0,320:4,11);
20 : (0,323:4,13);
22 : (0,323:4,14);
@@ -486,78 +486,78 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
480 : (0,317:7,9);
481 : (0,317:7,9);
----------
77 : (0,319:47,0);
81 : (0,320:52,0);
77 : (0,319:48,0);
81 : (0,320:49,0);
118 : (0,291:5,0);
122 : (0,291:5,0);
126 : (0,306:26,0);
127 : (0,306:49,0);
130 : (0,306:48,2);
131 : (0,306:48,0);
135 : (0,306:56,2);
136 : (0,306:56,0);
140 : (0,306:64,2);
141 : (0,306:64,0);
145 : (0,306:72,2);
146 : (0,306:72,0);
150 : (0,306:80,2);
151 : (0,306:80,0);
152 : (0,306:85,0);
154 : (0,306:85,0);
126 : (0,306:25,0);
127 : (0,306:48,0);
130 : (0,306:47,2);
131 : (0,306:47,0);
135 : (0,306:55,2);
136 : (0,306:55,0);
140 : (0,306:63,2);
141 : (0,306:63,0);
145 : (0,306:71,2);
146 : (0,306:71,0);
150 : (0,306:79,2);
151 : (0,306:79,0);
152 : (0,306:84,0);
154 : (0,306:84,0);
157 : (0,306:4,2);
158 : (0,306:4,0);
159 : (0,306:4,2);
160 : (0,307:19,0);
161 : (0,307:38,0);
160 : (0,307:14,0);
161 : (0,307:33,0);
164 : (0,307:4,3);
165 : (0,307:4,0);
166 : (0,307:4,3);
169 : (0,308:20,0);
170 : (0,308:39,0);
173 : (0,308:49,0);
169 : (0,308:15,0);
170 : (0,308:34,0);
173 : (0,308:44,0);
176 : (0,308:4,4);
177 : (0,308:4,0);
178 : (0,308:4,4);
179 : (0,311:26,0);
183 : (0,311:52,5);
184 : (0,311:52,0);
188 : (0,311:62,5);
189 : (0,311:62,0);
193 : (0,311:72,5);
194 : (0,311:72,0);
198 : (0,311:82,5);
199 : (0,311:82,0);
203 : (0,311:92,5);
204 : (0,311:92,0);
207 : (0,311:97,0);
179 : (0,311:25,0);
183 : (0,311:51,5);
184 : (0,311:51,0);
188 : (0,311:61,5);
189 : (0,311:61,0);
193 : (0,311:71,5);
194 : (0,311:71,0);
198 : (0,311:81,5);
199 : (0,311:81,0);
203 : (0,311:91,5);
204 : (0,311:91,0);
207 : (0,311:96,0);
210 : (0,311:4,5);
211 : (0,311:4,0);
212 : (0,311:4,5);
213 : (0,312:19,0);
214 : (0,312:40,0);
213 : (0,312:14,0);
214 : (0,312:35,0);
217 : (0,312:4,6);
218 : (0,312:4,0);
219 : (0,312:4,6);
222 : (0,313:20,0);
223 : (0,313:41,0);
226 : (0,313:53,0);
222 : (0,313:15,0);
223 : (0,313:36,0);
226 : (0,313:48,0);
229 : (0,313:4,7);
230 : (0,313:4,0);
231 : (0,313:4,7);
232 : (0,317:16,0);
236 : (0,317:4,9);
237 : (0,319:26,0);
238 : (0,319:47,0);
239 : (0,319:59,0);
240 : (0,319:80,0);
242 : (0,319:80,0);
238 : (0,319:48,0);
239 : (0,319:61,0);
240 : (0,319:82,0);
242 : (0,319:82,0);
245 : (0,319:4,10);
246 : (0,319:4,0);
247 : (0,319:4,10);
250 : (0,320:22,0);
251 : (0,320:52,0);
252 : (0,320:73,0);
255 : (0,320:94,0);
251 : (0,320:49,0);
252 : (0,320:67,0);
255 : (0,320:88,0);
258 : (0,320:4,11);
259 : (0,320:4,0);
260 : (0,320:4,11);
@@ -566,10 +566,10 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
315 : (0,323:4,14);
318 : (0,323:4,14);
321 : (0,323:4,14);
352 : (0,324:26,14);
357 : (0,324:36,14);
363 : (0,325:35,15);
368 : (0,325:45,15);
352 : (0,324:27,14);
357 : (0,324:37,14);
363 : (0,325:32,15);
368 : (0,325:42,15);
373 : (0,323:4,20);
380 : (0,323:4,20);
381 : (0,323:4,20);
@@ -582,21 +582,21 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
419 : (0,327:0,0);
423 : (0,327:0,25);
424 : (0,327:0,25);
574 : (0,324:26,0);
576 : (0,325:35,0);
574 : (0,324:27,0);
576 : (0,325:32,0);
617 : (0,291:5,0);
645 : (0,327:0,0);
729 : (0,306:56,0);
757 : (0,306:64,0);
785 : (0,306:72,0);
813 : (0,306:80,0);
841 : (0,311:62,0);
869 : (0,311:72,0);
897 : (0,311:82,0);
925 : (0,311:92,0);
729 : (0,306:55,0);
757 : (0,306:63,0);
785 : (0,306:71,0);
813 : (0,306:79,0);
841 : (0,311:61,0);
869 : (0,311:71,0);
897 : (0,311:81,0);
925 : (0,311:91,0);
965 : (0,291:5,0);
967 : (0,327:0,0);
971 : (0,306:56,0);
971 : (0,306:55,0);
989 : (0,323:4,13);
1022 : (0,317:16,0);
1023 : (0,317:16,9);

14
simulation/Release/chesswork/signal_path-a192c9.# Normal file
View File

@@ -0,0 +1,14 @@
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
a35ee70722a1a9c549d314cfa08fa544db59ee63
da39a3ee5e6b4b0d3255bfef95601890afd80709
0716eac1690ac51c6bb00ab1ce9b1e002c6886d8
201
0
0
0
0
0
0
0

BIN
simulation/Release/chesswork/signal_path-a192c9.o Normal file
View File

Binary file not shown.

148
simulation/Release/chesswork/signal_path-a192c9.sfg Normal file
View File

@@ -0,0 +1,148 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! int set_delay(SingleSignalPath *, int)
F_Z9set_delayP16SingleSignalPathi : user_defined, called {
fnm : "set_delay" 'int set_delay(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
frm : ( );
}
****
!! int initialize_buffer(BufferPtr *, int *, int, int)
F_Z17initialize_bufferP9BufferPtrPiii : user_defined, called {
fnm : "initialize_buffer" 'int initialize_buffer(BufferPtr *, int *, int, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
vac : ( srIM[0] );
llv : 0 1 0 0 0 ;
}
***/
[
0 : _Z9set_delayP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
29 : __vola typ=uint20_ bnd=b stl=PM
32 : __extDM typ=int8_ bnd=b stl=DM
33 : __extPM typ=uint20_ bnd=b stl=PM
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
38 : __extDM_SingleSignalPath__delay_buffer typ=int8_ bnd=b stl=DM
39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
40 : __extDM_void typ=int8_ bnd=b stl=DM
41 : __extPM_void typ=uint20_ bnd=b stl=PM
42 : __rd___sp typ=dmaddr_ bnd=m
43 : __ct_0 typ=uint1_ val=0f bnd=m
44 : __la typ=dmaddr_ bnd=p tref=dmaddr___
45 : __rt typ=int32_ bnd=p tref=__sint__
46 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
47 : n_delay typ=int32_ bnd=p tref=__sint__
53 : __tmp typ=dmaddr_ bnd=m
56 : __tmp typ=dmaddr_ bnd=m
57 : __ct_16 typ=int32_ val=16f bnd=m
58 : __ct typ=int32_ bnd=m
59 : _Z17initialize_bufferP9BufferPtrPiii typ=dmaddr_ val=0r bnd=m
62 : __tmp typ=int32_ bnd=m
76 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
99 : __ct_0S0 typ=int18_ val=0S0 bnd=m
100 : __ct_116 typ=int18_ val=116f bnd=m
103 : __ct_0s0 typ=int18_ val=0s0 bnd=m
105 : __ct_64 typ=int18_ val=64f bnd=m
]
F_Z9set_delayP16SingleSignalPathi {
#142 off=0
(__R_SP.24 var=26) st_def () <48>;
(__vola.27 var=29) source () <51>;
(__extDM.30 var=32) source () <54>;
(__extPM.31 var=33) source () <55>;
(__sp.32 var=34) source () <56>;
(__extDM_SingleSignalPath.33 var=35) source () <57>;
(__extDM_SingleSignalPath_delay_buffer.34 var=36) source () <58>;
(__extDM_BufferPtr.35 var=37) source () <59>;
(__extDM_SingleSignalPath__delay_buffer.36 var=38) source () <60>;
(__extDM_int32_.37 var=39) source () <61>;
(__extDM_void.38 var=40) source () <62>;
(__extPM_void.39 var=41) source () <63>;
(__ct_0.41 var=43) const () <65>;
(__la.43 var=44 stl=LR off=0) inp () <67>;
(__la.44 var=44) deassign (__la.43) <68>;
(signal.47 var=46 stl=A off=0) inp () <71>;
(signal.48 var=46) deassign (signal.47) <72>;
(n_delay.50 var=47 stl=RA off=1) inp () <74>;
(n_delay.51 var=47) deassign (n_delay.50) <75>;
(__rd___sp.53 var=42) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.132 __sp.32) <81>;
(__ct_16.68 var=57) const () <92>;
(_Z17initialize_bufferP9BufferPtrPiii.71 var=59) const () <95>;
(__rd___sp.88 var=42) rd_res_reg (__R_SP.24 __sp.58) <102>;
(__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.176 __sp.58) <106>;
(__rt.132 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.211) <192>;
(__rt.154 var=76) __Pvoid__pl___Pvoid_int18_ (signal.48 __ct_116.212) <220>;
(__rt.176 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.215) <248>;
(__rt.198 var=76) __Pvoid__mi___Pvoid_int18_ (__rt.154 __ct_64.217) <276>;
(__ct_0S0.211 var=99) const () <303>;
(__ct_116.212 var=100) const () <305>;
(__ct_0s0.215 var=103) const () <311>;
(__ct_64.217 var=105) const () <315>;
() void_jump_dmaddr_ (_Z17initialize_bufferP9BufferPtrPiii.71) <339>;
call {
(__tmp.62 var=53 stl=A off=0) assign (__rt.154) <86>;
(__tmp.66 var=56 stl=A off=1) assign (__rt.198) <90>;
(n_delay.67 var=47 stl=RA off=1) assign (n_delay.51) <91>;
(__ct.70 var=58 stl=RB off=0) assign (__ct_16.68) <94>;
(__la.74 var=44 stl=LR off=0) assign (__la.44) <98>;
(__tmp.75 var=62 stl=RA off=0 __extDM.78 var=32 __extDM_BufferPtr.79 var=37 __extDM_SingleSignalPath.80 var=35 __extDM_SingleSignalPath__delay_buffer.81 var=38 __extDM_SingleSignalPath_delay_buffer.82 var=36 __extDM_int32_.83 var=39 __extDM_void.84 var=40 __extPM.85 var=33 __extPM_void.86 var=41 __vola.87 var=29) F_Z17initialize_bufferP9BufferPtrPiii (__la.74 __tmp.62 __tmp.66 n_delay.67 __ct.70 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath__delay_buffer.36 __extDM_SingleSignalPath_delay_buffer.34 __extDM_int32_.37 __extDM_void.38 __extPM.31 __extPM_void.39 __vola.27) <99>;
(__tmp.76 var=62) deassign (__tmp.75) <100>;
} #4 off=1
#6 off=2 nxt=-2
(__rt.94 var=45 stl=RA off=0) assign (__tmp.76) <108>;
() out (__rt.94) <109>;
() sink (__vola.87) <110>;
() sink (__extDM.78) <113>;
() sink (__extPM.85) <114>;
() sink (__sp.93) <115>;
() sink (__extDM_SingleSignalPath.80) <116>;
() sink (__extDM_SingleSignalPath_delay_buffer.82) <117>;
() sink (__extDM_BufferPtr.79) <118>;
() sink (__extDM_SingleSignalPath__delay_buffer.81) <119>;
() sink (__extDM_int32_.83) <120>;
() sink (__extDM_void.84) <121>;
() sink (__extPM_void.86) <122>;
() sink (__ct_0.41) <123>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,201:0,0);
4 : (0,202:11,1);
6 : (0,202:4,1);
142 : (0,202:4,1);
----------
77 : (0,201:4,0);
81 : (0,201:4,0);
86 : (0,202:36,0);
90 : (0,202:58,0);
91 : (0,202:75,0);
92 : (0,202:84,0);
94 : (0,202:84,0);
98 : (0,202:11,0);
99 : (0,202:11,1);
102 : (0,202:4,0);
106 : (0,202:4,1);
108 : (0,202:28,0);
192 : (0,201:4,0);
220 : (0,202:36,1);
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2
simulation/Release/chesswork/signal_path-a30375.#
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2
simulation/Release/chesswork/signal_path-a30375.sfg
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32

5
simulation/Release/chesswork/signal_path-a3616e.#
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simulation/Release/chesswork/signal_path-a3616e.o
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50
simulation/Release/chesswork/signal_path-a3616e.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -90,29 +90,29 @@ F_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi {
} #5 off=0 nxt=-2
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391 : (0,178:86,2);

16
simulation/Release/chesswork/signal_path-a56564.#
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@@ -3,12 +3,12 @@
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96
simulation/Release/chesswork/signal_path-a56564.sfg
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -165,52 +165,52 @@ F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_D
} #0
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2
simulation/Release/chesswork/signal_path-d6dbe4.#
View File

@@ -20,3 +20,5 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
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simulation/Release/chesswork/signal_path-d6dbe4.sfg
View File

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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -171,75 +171,75 @@ F_Z15sig_calc_biquadP16SingleSignalPathi {
} #0
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3
simulation/Release/chesswork/signal_path-d74ce2.#
View File

@@ -20,3 +20,6 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
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simulation/Release/chesswork/signal_path-d74ce2.sfg
View File

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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 10:32:28 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
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2
simulation/Release/chesswork/signal_path-f431c2.#
View File

@@ -11,3 +11,5 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
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2
simulation/Release/chesswork/signal_path-f431c2.sfg
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32

3
simulation/Release/chesswork/signal_path-f8ba01.#
View File

@@ -20,3 +20,6 @@ da39a3ee5e6b4b0d3255bfef95601890afd80709
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simulation/Release/chesswork/signal_path-f8ba01.sfg
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 10:32:28 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
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1296 : (0,141:29,5);
1300 : (0,141:41,9);
1304 : (0,141:53,13);
1308 : (0,141:4,17);

6
simulation/Release/chesswork/signal_path.ctt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -18,7 +18,7 @@
#const ones unsigned 4294967295 (0xffffffff)
#const scale_bits int 31 (0x1f)
#const scale int 2147483647 (0x7fffffff)
#const __tmpb1_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi const double 2.0000000000000000 (0x4000000000000000)
#const __tmpb1_F_Z20scale_preemph_filterP16SingleSignalPathdddddi const double 2.0000000000000000 (0x4000000000000000)
#const __inl_x double 2.0000000000000000 (0x4000000000000000)
#const __tmpb1_F_Z15sig_init_weightP16SingleSignalPathdi const double 2.0000000000000000 (0x4000000000000000)
#const __tmpb1_F_Z10set_weightP16SingleSignalPathdi const double 2.0000000000000000 (0x4000000000000000)
#const __inl_x double 2.0000000000000000 (0x4000000000000000)

14
simulation/Release/chesswork/signal_path.dti
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -202,15 +202,6 @@ __sint_____PBufferPtr___P__sint___sint___sint__ : _function() $__sint__ $__PBuff
__PDMB__sint__ : _pointer() $__Pvoid__ $__sint_DMB;
__sint_____PDMBBufferPtrDMB___PDMB__sint___sint___sint__ : _function() $__sint__ $__PDMBBufferPtrDMB__ $__PDMB__sint__ $__sint__ $__sint__;
void_____PBufferPtr___sint__ : _function() _void $__PBufferPtr__ $__sint__;
__PDMB__sint_DMA : _pointer(DMA,4,4) $__Pvoid_DMA $__sint_DMB;
BufferPtrDMB_DMA : _struct(DMA,12,4) BufferPtrDMB {
buffer_len $__sint_DMA @0;
ptr_start $__PDMB__sint_DMA @4;
ptr_current $__PDMB__sint_DMA @8;
}
__PBufferPtrDMB__ : _pointer() $__Pvoid__ $BufferPtrDMB_DMA;
void_____PBufferPtrDMB___sint__ : _function() _void $__PBufferPtrDMB__ $__sint__;
void_____PBufferPtr___sint___1 : _function() _void $__PBufferPtr__ $__sint__;
void_____PDMBBufferPtrDMB___sint__ : _function() _void $__PDMBBufferPtrDMB__ $__sint__;
__A5__sint_DMA : _array(DMA,20,4) [5] $__sint_DMA;
__A2__sint_DMA : _array(DMA,8,4) [2] $__sint_DMA;
@@ -234,9 +225,6 @@ void_____PDMBBufferPtrDMB___sint__ : _function() _void $__PDMBBufferPtrDMB__ $__
void_____PSingleSignalPath___fdouble___fdouble___fdouble___fdouble___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__fdouble__ $__fdouble__ $__fdouble__ $__fdouble__ $__fdouble__ $__sint__;
__sint_____PSingleSignalPath___sint__ : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
void_____PSingleSignalPath___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__fdouble__ $__sint__;
__sint_____PSingleSignalPath___sint___1 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
__sint_____PSingleSignalPath___sint___2 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
__sint_____PSingleSignalPath___sint___3 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
__fdouble_DMA : _basic(DMA,8,8) __fdouble;
__P__fdouble__ : _pointer() $__Pvoid__ $__fdouble_DMA;
void_____PSingleSignalPath___PSingleSignalPath___P__fdouble___P__fdouble___sint___sint___fdouble___fdouble___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__PSingleSignalPath__ $__P__fdouble__ $__P__fdouble__ $__sint__ $__sint__ $__fdouble__ $__fdouble__ $__fdouble__ $__sint__;

77
simulation/Release/chesswork/signal_path.fnm
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -10,43 +10,31 @@
"signal_path-59265a.sfg"
: _Z17initialize_bufferP9BufferPtrPiii
: "initialize_buffer" global "signal_processing\\signal_path.c" 74 Ofile
: "initialize_buffer" global "signal_processing\\signal_path.c" 136 Ofile
(
)
"signal_path-a56564.sfg"
: _Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii
: "initialize_buffer_dmb" global "signal_processing\\signal_path.c" 91 Ofile
(
)
"signal_path-750458.sfg"
: _Z16increment_bufferP9BufferPtri
: "increment_buffer" global "signal_processing\\signal_path.c" 108 Ofile
(
)
"signal_path-f431c2.sfg"
: _Z21increment_buffert_DMBP12BufferPtrDMBi
: "increment_buffert_DMB" global "signal_processing\\signal_path.c" 113 Ofile
: "initialize_buffer_dmb" global "signal_processing\\signal_path.c" 153 Ofile
(
)
"signal_path-4df6b6.sfg"
: _Z12write_bufferP9BufferPtri
: "write_buffer" global "signal_processing\\signal_path.c" 117 Ofile
: "write_buffer" global "signal_processing\\signal_path.c" 170 Ofile
(
)
"signal_path-a3616e.sfg"
: _Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi
: "write_buffer_dmb" global "signal_processing\\signal_path.c" 123 Ofile
: "write_buffer_dmb" global "signal_processing\\signal_path.c" 176 Ofile
(
)
"signal_path-f8ba01.sfg"
: _Z21sig_init_preemph_coefP16SingleSignalPathdddddi
: "sig_init_preemph_coef" global "signal_processing\\signal_path.c" 140 Ofile
"signal_path-6dff42.sfg"
: _Z20scale_preemph_filterP16SingleSignalPathdddddi
: "scale_preemph_filter" global "signal_processing\\signal_path.c" 182 Ofile
(
ff_pow
_Z10float64_eqyy
@@ -56,16 +44,16 @@
_Z11float64_mulyy
)
"signal_path-6fcf7f.sfg"
: _Z14sig_init_delayP16SingleSignalPathi
: "sig_init_delay" global "signal_processing\\signal_path.c" 159 Ofile
"signal_path-a192c9.sfg"
: _Z9set_delayP16SingleSignalPathi
: "set_delay" global "signal_processing\\signal_path.c" 201 Ofile
(
_Z17initialize_bufferP9BufferPtrPiii
)
"signal_path-d74ce2.sfg"
: _Z15sig_init_weightP16SingleSignalPathdi
: "sig_init_weight" global "signal_processing\\signal_path.c" 164 Ofile
"signal_path-153c75.sfg"
: _Z10set_weightP16SingleSignalPathdi
: "set_weight" global "signal_processing\\signal_path.c" 206 Ofile
(
ff_pow
_Z10float64_eqyy
@@ -75,41 +63,22 @@
_Z11float64_mulyy
)
"signal_path-d6dbe4.sfg"
: _Z15sig_calc_biquadP16SingleSignalPathi
: "sig_calc_biquad" global "signal_processing\\signal_path.c" 180 Ofile
"signal_path-43153a.sfg"
: _Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi
: "initialize_signal" global "signal_processing\\signal_path.c" 291 Ofile
(
)
"signal_path-a30375.sfg"
: _Z29sig_delay_buffer_load_and_getP16SingleSignalPathi
: "sig_delay_buffer_load_and_get" global "signal_processing\\signal_path.c" 201 Ofile
(
_Z16increment_bufferP9BufferPtri
)
"signal_path-530a42.sfg"
: _Z15sig_calc_weightP16SingleSignalPathi
: "sig_calc_weight" global "signal_processing\\signal_path.c" 211 Ofile
(
)
"signal_path-9c02ae.sfg"
: _Z4initP16SingleSignalPathS0_PdS1_iidddi
: "init" global "signal_processing\\signal_path.c" 291 Ofile
(
_Z21sig_init_preemph_coefP16SingleSignalPathdddddi
_Z14sig_init_delayP16SingleSignalPathi
_Z15sig_init_weightP16SingleSignalPathdi
_Z20scale_preemph_filterP16SingleSignalPathdddddi
_Z9set_delayP16SingleSignalPathi
_Z10set_weightP16SingleSignalPathdi
_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii
_Z17initialize_bufferP9BufferPtrPiii
_Z11float64_mulyy
_Z30float64_to_int32_round_to_zeroy
)
"signal_path-a72ab8.sfg"
: _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
: "calc" global "signal_processing\\signal_path.c" 331 Ofile
"signal_path-52b1a0.sfg"
: _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
: "calculate_output" global "signal_processing\\signal_path.c" 331 Ofile
(
_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi
)

22
simulation/Release/chesswork/signal_path.gvt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -9,16 +9,16 @@
6 : _ZL7counter typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
7 : _ZL2mu typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
8 : _ZL4leak typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
9 : delay_line typ=int8_ bnd=g sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
10 : filter_coefficients typ=int8_ bnd=g sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
11 : pointer_delay_line typ=int8_ bnd=g sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
12 : pointer_filter_coefficients typ=int8_ bnd=g sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
13 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
14 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
15 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
16 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
17 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
18 : _ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
9 : sample_line typ=int8_ bnd=g sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
10 : coefficient_line typ=int8_ bnd=g sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
11 : pointer_sample_line typ=int8_ bnd=g sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
12 : pointer_coefficient_line typ=int8_ bnd=g sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
13 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
14 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
15 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
16 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
17 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
18 : _ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
]
__signal_path_sttc {
} #0

2
simulation/Release/chesswork/signal_path.gvt.#
View File

@@ -1,7 +1,7 @@
b94f5e81f66808a8f4f9315bd020e05811fb8d4a
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
49385fd808e0da9ad176cb538c83ecdbdf700e73
5a35cbaeb1a92d8d12c76c3c1dcbb218167684fc
da39a3ee5e6b4b0d3255bfef95601890afd80709
da39a3ee5e6b4b0d3255bfef95601890afd80709
0

BIN
simulation/Release/chesswork/signal_path.gvt.o
View File

Binary file not shown.

14
simulation/Release/chesswork/signal_path.ini
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -7,9 +7,9 @@ _ZL7counter/6 $ counter
_ZL2mu/7 $ mu
_ZL4leak/8 $ leak
_ZL4leak/8 : #1d #ac #ff #7f
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32/13 $ c_sensor_32 _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32/14 $ acc_sensor_32 _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre/15 $ c_sensor_pre _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre/16 $ acc_sensor_pre _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator/17 $ filter_accumulator _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32/18 $ output_32 _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E11c_sensor_32/13 $ c_sensor_32 _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E13acc_sensor_32/14 $ acc_sensor_32 _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E12c_sensor_pre/15 $ c_sensor_pre _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E14acc_sensor_pre/16 $ acc_sensor_pre _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E18filter_accumulator/17 $ filter_accumulator _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_
_ZZ16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_E9output_32/18 $ output_32 _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_

82
simulation/Release/chesswork/signal_path.lib
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -65,9 +65,9 @@ Fff_pow : user_defined, called {
llv : 0 1 0 0 0 ;
}
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
// void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "initialize_signal" 'void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
@@ -75,9 +75,9 @@ F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
llv : 0 1 0 0 0 ;
}
// void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
// void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calculate_output" 'void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );
@@ -105,26 +105,6 @@ F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_D
llv : 0 1 0 0 0 ;
}
// void increment_buffer(BufferPtr *, int)
F_Z16increment_bufferP9BufferPtri : user_defined, called {
fnm : "increment_buffer" 'void increment_buffer(BufferPtr *, int)';
arg : ( dmaddr_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] RA[0] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// void increment_buffert_DMB(BufferPtrDMB *, int)
F_Z21increment_buffert_DMBP12BufferPtrDMBi : user_defined, called {
fnm : "increment_buffert_DMB" 'void increment_buffert_DMB(BufferPtrDMB *, int)';
arg : ( dmaddr_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] RA[0] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// void write_buffer(BufferPtr *, int)
F_Z12write_bufferP9BufferPtri : user_defined, called {
fnm : "write_buffer" 'void write_buffer(BufferPtr *, int)';
@@ -145,9 +125,9 @@ F_Z16write_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called
llv : 0 0 0 0 0 ;
}
// void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
fnm : "sig_init_preemph_coef" 'void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)';
// void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
F_Z20scale_preemph_filterP16SingleSignalPathdddddi : user_defined, called {
fnm : "scale_preemph_filter" 'void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
vac : ( srIM[0] );
@@ -155,9 +135,9 @@ F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
llv : 0 1 0 0 0 ;
}
// int sig_init_delay(SingleSignalPath *, int)
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
// int set_delay(SingleSignalPath *, int)
F_Z9set_delayP16SingleSignalPathi : user_defined, called {
fnm : "set_delay" 'int set_delay(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
@@ -165,9 +145,9 @@ F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
llv : 0 1 0 0 0 ;
}
// void sig_init_weight(SingleSignalPath *, double, int)
F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
fnm : "sig_init_weight" 'void sig_init_weight(SingleSignalPath *, double, int)';
// void set_weight(SingleSignalPath *, double, int)
F_Z10set_weightP16SingleSignalPathdi : user_defined, called {
fnm : "set_weight" 'void set_weight(SingleSignalPath *, double, int)';
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
loc : ( LR[0] A[0] AX[0] RA[0] );
vac : ( srIM[0] );
@@ -175,33 +155,3 @@ F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
llv : 0 1 0 0 0 ;
}
// int sig_calc_biquad(SingleSignalPath *, int)
F_Z15sig_calc_biquadP16SingleSignalPathi : user_defined, called {
fnm : "sig_calc_biquad" 'int sig_calc_biquad(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi : user_defined, called {
fnm : "sig_delay_buffer_load_and_get" 'int sig_delay_buffer_load_and_get(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// int sig_calc_weight(SingleSignalPath *, int)
F_Z15sig_calc_weightP16SingleSignalPathi : user_defined, called {
fnm : "sig_calc_weight" 'int sig_calc_weight(SingleSignalPath *, int)';
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
loc : ( LR[0] RA[0] A[0] RA[1] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}

19
simulation/Release/chesswork/signal_path.objlist
View File

@@ -1,15 +1,10 @@
"signal_path-59265a.o" 1
"signal_path-a56564.o" 2
"signal_path-750458.o" 0
"signal_path-f431c2.o" 0
"signal_path-59265a.o" 0
"signal_path-a56564.o" 0
"signal_path-4df6b6.o" 0
"signal_path-a3616e.o" 0
"signal_path-f8ba01.o" 7
"signal_path-6fcf7f.o" 5
"signal_path-d74ce2.o" 7
"signal_path-d6dbe4.o" 7
"signal_path-a30375.o" 0
"signal_path-530a42.o" 7
"signal_path-9c02ae.o" -10
"signal_path-a72ab8.o" 0
"signal_path-6dff42.o" 0
"signal_path-a192c9.o" 0
"signal_path-153c75.o" 0
"signal_path-43153a.o" 0
"signal_path-52b1a0.o" 0
"signal_path.gvt.o" 0

30
simulation/Release/chesswork/signal_path.tof
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
@@ -10,39 +10,21 @@
// int initialize_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
// void increment_buffer(BufferPtr *, int)
void *cyclic_add(void *, int, void *, int)
// void increment_buffert_DMB(BufferPtrDMB *, int)
void *cyclic_add(void *, int, void *, int)
// void write_buffer(BufferPtr *, int)
void *cyclic_add(void *, int, void *, int)
// void write_buffer_dmb(BufferPtrDMB chess_storage(DMB) *, int)
void *cyclic_add(void *, int, void *, int)
// void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
// void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
// int sig_init_delay(SingleSignalPath *, int)
// int set_delay(SingleSignalPath *, int)
// void sig_init_weight(SingleSignalPath *, double, int)
// void set_weight(SingleSignalPath *, double, int)
// int sig_calc_biquad(SingleSignalPath *, int)
accum_t fract_mult(int, int)
accum_t operator+(accum_t, accum_t)
accum_t operator<<(accum_t, int)
int rnd_saturate(accum_t)
// void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
// int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
// int sig_calc_weight(SingleSignalPath *, int)
accum_t fract_mult(int, int)
int rnd_saturate(accum_t)
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
// void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
// void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
accum_t to_accum(int)
void *cyclic_add(void *, int, void *, int)
accum_t fract_mult(int, int)