138 lines
5.5 KiB
Plaintext
138 lines
5.5 KiB
Plaintext
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026
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// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
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// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
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/***
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!! int sig_calc_weight(SingleSignalPath *, int)
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F_Z15sig_calc_weightP16SingleSignalPathi : user_defined, called {
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fnm : "sig_calc_weight" 'int sig_calc_weight(SingleSignalPath *, int)';
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arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
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loc : ( LR[0] RA[0] A[0] RA[1] );
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vac : ( srIM[0] );
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frm : ( );
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}
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****
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***/
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[
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0 : _Z15sig_calc_weightP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___3
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11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
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26 : __R_SP typ=dmaddr_ bnd=d stl=SP
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34 : __sp typ=dmaddr_ bnd=b stl=SP
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36 : __extDM_SingleSignalPath_weight_actived typ=int8_ bnd=b stl=DM
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38 : __extDM_SingleSignalPath_weight typ=int8_ bnd=b stl=DM
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39 : __rd___sp typ=dmaddr_ bnd=m
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40 : __ct_0 typ=uint1_ val=0f bnd=m
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41 : __la typ=dmaddr_ bnd=p tref=dmaddr___
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42 : __rt typ=int32_ bnd=p tref=__sint__
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43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
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44 : x typ=int32_ bnd=p tref=__sint__
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48 : acc typ=int72_ bnd=m lscp=144 tref=accum_t__
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52 : __fch___extDM_SingleSignalPath_weight_actived typ=int32_ bnd=m
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53 : __ct_0 typ=int32_ val=0f bnd=m
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55 : __tmp typ=bool bnd=m
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59 : __fch___extDM_SingleSignalPath_weight typ=int32_ bnd=m
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77 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
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100 : __ct_0S0 typ=int18_ val=0S0 bnd=m
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101 : __ct_132 typ=int18_ val=132f bnd=m
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104 : __ct_136 typ=int18_ val=136f bnd=m
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107 : __ct_0s0 typ=int18_ val=0s0 bnd=m
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111 : __tmp typ=uint3_ bnd=m
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121 : __either typ=bool bnd=m
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122 : __trgt typ=int10_ val=0j bnd=m
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123 : __trgt typ=int10_ val=0j bnd=m
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]
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F_Z15sig_calc_weightP16SingleSignalPathi {
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#194 off=0
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(__M_WDMA.9 var=11) st_def () <18>;
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(__R_SP.24 var=26) st_def () <48>;
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(__sp.32 var=34) source () <56>;
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(__extDM_SingleSignalPath_weight_actived.34 var=36) source () <58>;
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(__extDM_SingleSignalPath_weight.36 var=38) source () <60>;
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(__ct_0.38 var=40) const () <62>;
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(__la.40 var=41 stl=LR off=0) inp () <64>;
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(__la.41 var=41) deassign (__la.40) <65>;
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(signal.44 var=43 stl=A off=0) inp () <68>;
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(signal.45 var=43) deassign (signal.44) <69>;
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(x.47 var=44 stl=RA off=1) inp () <71>;
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(x.48 var=44) deassign (x.47) <72>;
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(__rd___sp.50 var=39) rd_res_reg (__R_SP.24 __sp.32) <74>;
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(__R_SP.54 var=26 __sp.55 var=34) wr_res_reg (__rt.133 __sp.32) <78>;
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(__fch___extDM_SingleSignalPath_weight_actived.60 var=52) load (__M_WDMA.9 __rt.155 __extDM_SingleSignalPath_weight_actived.34) <84>;
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(__ct_0.61 var=53) const () <85>;
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(__rt.133 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.50 __ct_0S0.212) <200>;
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(__rt.155 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_132.213) <228>;
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(__ct_0S0.212 var=100) const () <309>;
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(__ct_132.213 var=101) const () <311>;
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(__tmp.222 var=111) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_weight_actived.60 __ct_0.61) <328>;
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(__tmp.223 var=55) bool_equal_uint3_ (__tmp.222) <329>;
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(__trgt.231 var=122) const () <363>;
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() void_jump_bool_int10_ (__tmp.223 __trgt.231) <364>;
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(__either.232 var=121) undefined () <365>;
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if {
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{
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() if_expr (__either.232) <103>;
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} #5
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{
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} #6 off=2
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{
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(__fch___extDM_SingleSignalPath_weight.83 var=59) load (__M_WDMA.9 __rt.177 __extDM_SingleSignalPath_weight.36) <108>;
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(__rt.85 var=42) __sint_rnd_saturate_accum_t (acc.115) <110>;
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(acc.115 var=48) int72__multss_int32__int32__uint1_ (x.48 __fch___extDM_SingleSignalPath_weight.83 __ct_0.38) <161>;
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(__rt.177 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_136.216) <256>;
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(__ct_136.216 var=104) const () <317>;
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(__trgt.233 var=123) const () <366>;
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() void_jump_int10_ (__trgt.233) <367>;
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} #144 off=1
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{
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(__rt.86 var=42) merge (x.48 __rt.85) <111>;
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} #8
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} #4
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#10 off=3 nxt=-2
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(__rd___sp.88 var=39) rd_res_reg (__R_SP.24 __sp.55) <113>;
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(__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.199 __sp.55) <117>;
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() void_ret_dmaddr_ (__la.41) <118>;
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(__rt.94 var=42 stl=RA off=0) assign (__rt.86) <119>;
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() out (__rt.94) <120>;
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() sink (__sp.93) <126>;
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() sink (__ct_0.38) <131>;
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(__rt.199 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.219) <284>;
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(__ct_0s0.219 var=107) const () <323>;
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} #0
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0 : 'signal_processing\\signal_path.c';
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----------
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0 : (0,211:0,0);
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4 : (0,212:4,1);
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6 : (0,212:37,2);
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10 : (0,217:4,11);
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144 : (0,217:11,7);
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194 : (0,212:31,1);
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----------
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74 : (0,211:4,0);
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78 : (0,211:4,0);
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84 : (0,212:14,1);
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85 : (0,212:34,0);
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103 : (0,212:4,1);
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108 : (0,215:38,6);
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110 : (0,217:11,7);
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111 : (0,212:4,10);
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113 : (0,217:4,0);
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117 : (0,217:4,11);
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118 : (0,217:4,11);
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119 : (0,217:4,0);
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161 : (0,215:18,6);
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200 : (0,211:4,0);
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228 : (0,212:14,1);
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256 : (0,215:38,6);
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284 : (0,217:4,0);
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309 : (0,211:4,0);
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311 : (0,212:14,0);
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317 : (0,215:38,0);
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323 : (0,217:4,0);
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328 : (0,212:31,1);
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329 : (0,212:31,1);
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364 : (0,212:4,1);
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