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Calc Funktion weitergecoded - kompiliert

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This commit is contained in:
Patrick Hangl
2026-01-27 16:38:58 +01:00
parent 9b09cb21fa
commit 6f52b7ace4
93 changed files with 15970 additions and 14407 deletions
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118
simulation/Release/chesswork/signal_path-f66b97.sfg Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Tue Jan 27 15:57:59 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
!! void write_delay_line(BufferPtrDMB chess_storage(DMB) *, int)
F_Z16write_delay_linePU17chess_storage_DMB12BufferPtrDMBi : user_defined, called {
fnm : "write_delay_line" 'void write_delay_line(BufferPtrDMB chess_storage(DMB) *, int)';
arg : ( dmaddr_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[4] RA[0] );
vac : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : _Z16write_delay_linePU17chess_storage_DMB12BufferPtrDMBi typ=uint20_ bnd=e stl=PM tref=void_____PDMBBufferPtrDMB___sint__
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __extDM_BufferPtrDMB_ptr_current typ=int8_ bnd=b stl=DM
38 : __extDM_BufferPtrDMB_ptr_start typ=int8_ bnd=b stl=DM
39 : __extDM_BufferPtrDMB_buffer_len typ=int8_ bnd=b stl=DM
40 : __extDM_int32_ typ=int8_ bnd=b stl=DM
41 : __rd___sp typ=dmaddr_ bnd=m
42 : __ct_0 typ=uint1_ val=0f bnd=m
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
44 : buffer typ=dmaddr_ bnd=p tref=__PDMBBufferPtrDMB__
45 : sample typ=int32_ bnd=p tref=__sint__
52 : __fch___extDM_BufferPtrDMB_ptr_current typ=dmaddr_ bnd=m
62 : __fch___extDM_BufferPtrDMB_ptr_start typ=dmaddr_ bnd=m
66 : __fch___extDM_BufferPtrDMB_buffer_len typ=int32_ bnd=m
70 : __tmp typ=dmaddr_ bnd=m
89 : __ct_4 typ=int18_ val=4f bnd=m
94 : __ct_2 typ=int32_ val=2f bnd=m
97 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
122 : __ct_0S0 typ=int18_ val=0S0 bnd=m
123 : __ct_8 typ=int18_ val=8f bnd=m
126 : __ct_0s0 typ=int18_ val=0s0 bnd=m
131 : __ct_2 typ=uint2_ val=2f bnd=m
135 : __tmp typ=int18_ bnd=m
]
F_Z16write_delay_linePU17chess_storage_DMB12BufferPtrDMBi {
(__M_WDMB.10 var=12) st_def () <20>;
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__extDM_BufferPtrDMB_ptr_current.34 var=36) source () <58>;
(__extDM_BufferPtrDMB_ptr_start.36 var=38) source () <60>;
(__extDM_BufferPtrDMB_buffer_len.37 var=39) source () <61>;
(__extDM_int32_.38 var=40) source () <62>;
(__ct_0.40 var=42) const () <64>;
(__la.42 var=43 stl=LR off=0) inp () <66>;
(__la.43 var=43) deassign (__la.42) <67>;
(buffer.45 var=44 stl=A off=4) inp () <69>;
(buffer.46 var=44) deassign (buffer.45) <70>;
(sample.48 var=45 stl=RA off=0) inp () <72>;
(sample.49 var=45) deassign (sample.48) <73>;
(__rd___sp.51 var=41) rd_res_reg (__R_SP.24 __sp.32) <75>;
(__R_SP.55 var=26 __sp.56 var=34) wr_res_reg (__rt.140 __sp.32) <79>;
(__fch___extDM_BufferPtrDMB_ptr_current.60 var=52) load (__M_WDMB.10 __rt.162 __extDM_BufferPtrDMB_ptr_current.34) <84>;
(__M_WDMB.61 var=12 __extDM_BufferPtrDMB_buffer_len.62 var=39 __extDM_int32_.63 var=40) store (sample.49 __fch___extDM_BufferPtrDMB_ptr_current.60 __extDM_BufferPtrDMB_buffer_len.37 __extDM_int32_.38) <85>;
(__fch___extDM_BufferPtrDMB_ptr_start.73 var=62) load (__M_WDMB.10 __rt.206 __extDM_BufferPtrDMB_ptr_start.36) <95>;
(__fch___extDM_BufferPtrDMB_buffer_len.77 var=66) load (__M_WDMB.10 __rt.228 __extDM_BufferPtrDMB_buffer_len.62) <99>;
(__M_WDMB.85 var=12 __extDM_BufferPtrDMB_ptr_current.86 var=36) store (__tmp.116 __rt.250 __extDM_BufferPtrDMB_ptr_current.34) <107>;
(__rd___sp.87 var=41) rd_res_reg (__R_SP.24 __sp.56) <108>;
(__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.184 __sp.56) <112>;
() void_ret_dmaddr_ (__la.43) <113>;
() sink (__sp.92) <119>;
() sink (__extDM_BufferPtrDMB_ptr_current.86) <121>;
() sink (__extDM_BufferPtrDMB_buffer_len.62) <124>;
() sink (__extDM_int32_.63) <125>;
() sink (__ct_0.40) <126>;
(__tmp.116 var=70) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch___extDM_BufferPtrDMB_ptr_current.60 __ct_4.120 __fch___extDM_BufferPtrDMB_ptr_start.73 __tmp.272) <159>;
(__ct_4.120 var=89) const () <173>;
(__ct_2.126 var=94) const () <181>;
(__rt.140 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.51 __ct_0S0.263) <208>;
(__rt.162 var=97) __Pvoid__pl___Pvoid_int18_ (buffer.46 __ct_8.264) <236>;
(__rt.184 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_0s0.267) <264>;
(__rt.206 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.162 __ct_4.120) <292>;
(__rt.228 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.206 __ct_4.120) <320>;
(__rt.250 var=97) __Pvoid__pl___Pvoid_int18_ (__rt.228 __ct_8.264) <348>;
(__ct_0S0.263 var=122) const () <375>;
(__ct_8.264 var=123) const () <377>;
(__ct_0s0.267 var=126) const () <383>;
(__ct_2.271 var=131) const () <390>;
(__tmp.272 var=135) int72__shift_int72__int72__uint2_ (__fch___extDM_BufferPtrDMB_buffer_len.77 __ct_2.126 __ct_2.271) <391>;
} #5 off=0 nxt=-2
0 : 'signal_processing\\signal_path.c';
----------
5 : (0,121:0,3);
----------
75 : (0,118:5,0);
79 : (0,118:5,0);
84 : (0,119:11,1);
85 : (0,119:4,1);
95 : (0,120:67,2);
99 : (0,120:86,2);
107 : (0,120:10,2);
108 : (0,121:0,0);
112 : (0,121:0,3);
113 : (0,121:0,3);
159 : (0,120:26,2);
173 : (0,120:26,0);
181 : (0,120:86,0);
208 : (0,118:5,0);
236 : (0,119:11,1);
264 : (0,121:0,0);
292 : (0,120:67,0);
348 : (0,119:11,0);
375 : (0,118:5,0);
377 : (0,119:11,0);
383 : (0,121:0,0);
390 : (0,120:86,0);
391 : (0,120:86,2);