5.4

.gitignore

@@ -13,3 +13,5 @@ main.pdf
 main.toc
 main.run.xml
 main.synctex.gz
+acronyms.aux
+chapter_04.aux

.vscode/ltex.disabledRules.en-US.txt

@@ -1 +1,4 @@
 AFTERWARDS_US
+MORFOLOGIK_RULE_EN_US
+SENTENCE_WHITESPACE
+MORFOLOGIK_RULE_EN_US

acronyms.aux

@@ -17,6 +17,7 @@
 \newacro{ARM}[\AC@hyperlink{ARM}{ARM}]{Advanced RISC Machine}
 \newacro{RISC}[\AC@hyperlink{RISC}{RISC}]{Reduced Instruction Set Computer}
 \newacro{SOC}[\AC@hyperlink{SOC}{SOC}]{System-on-Chip}
+\newacro{SNR}[\AC@hyperlink{SNR}{SNR}]{Signal-to-Noise Ratio}
 \@setckpt{acronyms}{
 \setcounter{page}{5}
 \setcounter{equation}{0}

acronyms.tex

@@ -18,4 +18,5 @@
   \acro{ARM}{Advanced RISC Machine}
   \acro{RISC}{Reduced Instruction Set Computer}
   \acro{SOC}{System-on-Chip}
+  \acro{SNR}{Signal-to-Noise Ratio}
 \end{acronym}

chapter_02.tex

@@ -132,7 +132,6 @@ To reduce the required computing power, a hybrid static/adaptive filter design c
     \caption{Hybrid adaptive filter design for noise reduction with a static part and an adaptive part.}
     \label{fig:fig_anr_hybrid}
 \end{figure}
-\noindent Different approaches of the hybrid static/adaptive filter design will be evaluated and compared in regard of their required computing power in a later chapter of this thesis.
 \subsection{Adaptive optimization strategies}
 In the description of the concept of adaptive filtering above, the adaption of filter coefficients due to an error metric was mentioned but not further explained. The following subchapters shall cover the most important aspects of filter optimization in regard of adaptive noise reduction.
 \subsubsection{Filter optimization and error metrics}
@@ -277,7 +276,7 @@ The following definitions of the involved signals shall help to better understan
 \item Filter output / Cleaned signal: The output signal of the \ac{ANR} algorithm, representing the desired signal after noise reduction. This signal also equals the error signal of the adaptive filter.
 \end{itemize}
 The primary sensor receives the desired- and noise signal over their respective transfer functions and outputs the corrupted signal $d[n]$, which consists out of the recorded desired signal $s[n]$ and the corruption noise signal $n[n]$, whereas the noise signal sensor aims to receive (ideally) only the noise signal $v[n]$ over its transfer function and outputs the reference noise signal $x[n]$, which then feeds the adaptive filter.\\ \\
-Additionally, now the relevant transfer functions of the overall system are illustrated in Figure \ref{fig:fig_anr_implant}. The transfer functions $C_n$, $D_n$, and $E_n$ describe the path from the signal sources to the cochlear implant system. As the sources, the relative location of the user to the sources and the medium between them can vary, these transfer functions are time-variant and unknown. After the signals reached the implant systems, we establish the possibility, that the remaining path of the signals is mainly depended on the sensitivity curve of the respective sensors and therefore can be seen as time-invariant and known. This known transfer functions, which are titled $A$ and $B$, allow us to apply a hybrid static/adaptive filter design for the \ac{ANR} implementation, as described in chapter 2.5.2.\\ \\ 
+Additionally, now the relevant transfer functions of the overall system are illustrated in Figure \ref{fig:fig_anr_implant}. The transfer functions $C_n$, $D_n$, and $E_n$ describe the path from the signal sources to the cochlear implant system. As the sources, the relative location of the user to the sources and the medium between them can vary, these transfer functions are time-variant and unknown. After the signals reached the implant systems, we establish the possibility, that the remaining path of the signals is mainly depended on the sensitivity curve of the respective sensors and therefore can be seen as time-invariant and known.\\ \\ 
 \begin{equation}
 \label{equation_dn}
  d[n] = s[n] + n[n] = t[n] * (C_nA) + v[n] * (D_nA)

chapter_03.tex

@@ -44,11 +44,18 @@ The flow diagram in Figure \ref{fig:fig_anr_logic} illustrates the logical flow
     \caption{High-level implementation of the \ac{ANR} algorithm in Python}
     \label{fig:fig_anr_code}
 \end{figure}
-\noindent The algorithm implementation shall now be put under test by different use cases to demonstrate the functionality and performance under different scenarios, varying from simple to complex ones. Every use case includes graphical representations of the desired signal, the corrupted signal, the reference noise signal, the filter output, the error signal and the evolution of selected filter coefficients over time. In contrary to a realistic setup, the desired signal is available, allowing to evaluate the performance of the algorithm in a clear way. The performance of the \ac{ANR} algorithm is evaluated based on the error between the desired signal and the filter output, complemented with the normalized integrated squared error.
+\noindent The algorithm implementation shall now be put under test by different use cases to demonstrate the functionality and performance under different scenarios, varying from simple to complex ones. Every use case includes graphical representations of the desired signal, the corrupted signal, the reference noise signal, the filter output, the error signal and the evolution of selected filter coefficients over time. In contrary to a realistic setup, the desired signal is available, allowing to evaluate the performance of the algorithm based on the \ac{SNR}-Gain in dB and also visually by the amplitude of the error signal (difference between the desired signal and the filter output). The error signal and the \ac{SNR}-Gain are calculated as follows:
+\begin{gather}
+    \label{equation_snr_gain_error}
+    P_{Error-signal} = P_{Desired-signal} - P_{Filter-output} \\
+\label{equation_snr_gain}
+    SNR\text{-}Gain = 10 \cdot \log_{10}\frac{P_{Desired-signal}}{P_{Noise-signal}} - 10 \cdot \log_{10}\frac{P_{Desired-signal}}{P_{Error-signal}} 
+\end{gather}
+with $P_{Desired-signal}$ being the power of the desired signal, $P_{Noise-signal}$ being the power of the noise signal and $P_{Error-signal}$ being the power of the error signal, which is the difference between the desired signal and the filter output. A positive \ac{SNR}-Gain indicates an improvement in signal quality, while a negative \ac{SNR}-Gain indicates a degradation in signal quality after applying the \ac{ANR} algorithm.
 \subsection{Simple ANR use cases}
 To evaluate the general functionality and performance of the \ac{ANR} algorithm from Figure \ref{fig:fig_anr_code} a set of three simple, artificial scenarios are introduced. These examples shall serve as a showcase to demonstrate the general functionality, the possibilities and the limitations of the \ac{ANR} algorithm.\\ \\
 In all three scenarios, a chirp signal with a frequency range from 100-1000 Hz is used as the desired signal, which is then corrupted with a sine wave (Use case 1 and 2) or a Gaussian white noise (Use case 3) as noise signal respectively. In this simple setup, the corruption noise signal is also available as the reference noise signal. Every approach is conducted with 16 filter coefficients and a step size of 0.01. The four graphs in the respective first plot show the desired signal, the corrupted signal, the reference noise signal and the filter output. The two graphs in the respective second plot show the performance of the filter in form of the resulting error signal and the evolution of three filter coefficients over time.\\ \\
-\noindent This artificial setup could be solved analytically, as the signals do not pass separate, different transfer functions, meaning, that the reference noise signal is the same as the corruption noise signal. Though, this simple setup would not require an adaptive filter approach, it nevertheless allows to clearly evaluate the performance of the \ac{ANR} algorithm in different scenarios. Also, due to the fact that the desired signal is known, it is possible to graphically evaluate the performance of the algorithm in a simple way.
+\noindent This artificial setup could be solved analytically, as the signals do not pass separate, different transfer functions, meaning, that the reference noise signal is the same as the corruption noise signal. Though, this simple setup would not require an adaptive filter approach, it nevertheless allows to clearly evaluate the performance of the \ac{ANR} algorithm in different scenarios. Also, due to the fact that the desired signal is known, it is possible to evaluate the performance of the algorithm in a simple way.
 \subsubsection{Simple use case 1: Sine noise at 2000 Hz}
 In the first use case, a sine wave with a frequency of 2000 Hz, which lies outside the frequency spectrum of the chirp, is used as noise signal to corrupt the desired signal. The shape of the initial desired signal is still clearly recognizable, even if its shape is affected in the higher frequency area. The filter output in Figure \ref{fig:fig_plot_1_sine_1.png} shows a satisfying performance of the \ac{ANR} algorithm, as the noise is almost completely removed from the corrupted signal after the filter coefficients have adapted.
 \begin{figure}[H]
@@ -57,7 +64,7 @@ In the first use case, a sine wave with a frequency of 2000 Hz, which lies outsi
     \caption{Desired signal, corrupted signal, reference noise signal and filter output of simple use case 1}
     \label{fig:fig_plot_1_sine_1.png}
 \end{figure}
-\noindent The error signal in Figure \ref{fig:fig_plot_2_sine_1.png} confirms this observation, as the signal converges basically to zero after 200 ms. The evolution of the filter coefficients also indicates a quick convergence, meaning that the algorithm has adapted effectively to minimize the error over time.
+\noindent The error signal in Figure \ref{fig:fig_plot_2_sine_1.png} confirms this observation, as the signal converges basically to zero after 500 ms. The evolution of the filter coefficients also indicates a quick convergence, meaning that the algorithm has adapted effectively to minimize the error over time.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_2_sine_1.png}
@@ -87,7 +94,7 @@ The last on of our three simplified use cases involves the use of a Gaussian whi
     \caption{Desired signal, corrupted signal, reference noise signal and filter output of simple use case 3}
     \label{fig:fig_plot_1_noise.png}
 \end{figure}
-\noindent The error signal in Figure \ref{fig:fig_plot_2_noise.png} shows a noticeable variance compared to the previous use cases, especially at the beginning of the signal, where low frequencies dominate. The evolution of the filter coefficients show an interesting pattern, as only the coefficient in the beginning adapts significantly, while the others remain relatively stable around zero.
+\noindent The error signal in Figure \ref{fig:fig_plot_2_noise.png} shows a noticeable variance compared to the previous use cases, especially at the beginning of the signal, where low frequencies dominate. The evolution of the filter coefficients show an interesting pattern, as only the coefficient in the beginning adapts significantly, while the others remain relatively stable around zero. Also the \ac{SNR}-Gain of this use case is significantly lower compared to the previous use cases, which can be explained by the fact that the noise signal contains a broad spectrum of frequencies, making it more difficult for the \ac{ANR} algorithm to effectively isolate and reduce the noise from the desired signal.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_2_noise.png}
@@ -109,11 +116,10 @@ After the general functionality of the \ac{ANR} algorithm has been verified with
     \caption{Error signal and filter coefficient evolution of the intermediate \ac{ANR} use case}
     \label{fig:fig_plot_2_wav.png}
 \end{figure}
-\noindent The error signal in Figure \ref{fig:fig_plot_2_wav.png} confirms the function of the algorithm and shows peaks corresponding to the spikes in the breathing noise, indicating the moments, when the \ac{ANR} algorithm is setting its coefficients again to adapt to the changing noise characteristics. It makes sense, that the adaption of the filter coefficients causes repeating spikes in the error signal, as the noise signal now is not static or periodic, but rather dynamic and changing it frequency and amplitude over time. 
+\noindent The error signal in Figure \ref{fig:fig_plot_2_wav.png} confirms the function of the algorithm and shows maxima corresponding to the maxima in the breathing noise, indicating the moments, when the \ac{ANR} algorithm is setting its coefficients again to adapt to the changing noise characteristics. It makes sense, that the adaption of the filter coefficients causes repeating maxima in the error signal, as the noise signal now is not static or periodic, but rather dynamic and changing it frequency and amplitude over time. The \ac{SNR}-Gain of 6.51 dB also indicates a significant improvement in signal quality and can be compared againtst the complex use case in the next subchapter, where the same audio tracks are used, but now with different transfer functions applied to them.
 \subsection{Complex ANR use case}
 To close the topic of high-level simulations of the \ac{ANR} algorithm, a more complex and realistic use case is finally introduced. In this scenario, the same two audio tracks of the previous use case are used - but now they pass different transfer functions. Now, an analytical solution is not possible anymore, as the transfer functions affect the signals in different ways, making it impossible to simply subtract the noise signal from the corrupted signal. This scenario represents a more realistic application of the \ac{ANR} algorithm, as it involves complex audio signals with varying frequency components and dynamics, as well as different transfer functions affecting the signals.\\ \\
-Different transfer functions represent the reality of different sensors recording the corrupted signal and the reference noise signal with a specific frequency response characteristic - this circumstance is especially important, as later a fixed set of filter coefficients shall take care of the predictable part of the signal to reduce the computing power of the \ac{DSP}.\\ 
+Therefore, the audio tracks from the previous example are now convolved with different transfer functions, which mimic the case, that the sensor recording the corrupted signal, shows another frequency response characteristic as the one recording the reference noise signal. This means, that the reference noise signal is now not only differs from the noise signal corrupting the desired signal, making adaptive noise reduction the only feasible approach to reduce the noise from the corrupted signal.
-Therefore, the audio tracks from the previous example are now convolved with different transfer functions, which mimic the case, that the sensor recording the corrupted signal, shows another frequency response characteristic as the one recording the reference noise signal. This means, that the reference noise signal is now different to the noise signal corrupting the desired signal, making adaptive noise reduction the only feasible approach to reduce the noise from the corrupted signal.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_3_wav_complex.png}
@@ -127,14 +133,14 @@ Therefore, the audio tracks from the previous example are now convolved with dif
     \caption{The raw noise signal recorded with two different sensors, showing the effect of different transfer functions on the signal}
     \label{fig:fig_plot_4_wav_complex.png}
 \end{figure}
-\noindent To evaluate the performance of the \ac{ANR} algorithm in this complex scenario, the corrupted signal is recorded with the primary sensor while the reference noise signal is recorded with secondary sensor. The filter output in Figure \ref{fig:fig_plot_1_wav_complex.png} indicates, that the \ac{ANR} algorithm is still capable of significantly reducing the noise from the corrupted signal, even with the reference noise signal being different from the corruption noise signal. 
+\noindent To evaluate the performance of the \ac{ANR} algorithm in this complex scenario, the corrupted signal is recorded with the primary sensor while the reference noise signal is recorded with secondary sensor. The filter output and \ac{SNR}-Ratio in Figure \ref{fig:fig_plot_1_wav_complex.png} display with 6.98 dB a an even slightly better performance compared to the previous use case. This bevavior is explainable by the fact, that depending on the transfer functions of the sensors, for some signals the adaptation process might be more effective than for others.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_1_wav_complex.png}
     \caption{Desired signal, corrupted signal, reference noise signal and filter output of the complex \ac{ANR} use case}
     \label{fig:fig_plot_1_wav_complex.png}
 \end{figure}
-\noindent The error signal in Figure \ref{fig:fig_plot_2_wav_complex.png} shows an even better performance compared to the previous intermediate use case, indicating that the \ac{ANR} algorithm is effectively adapting its filter coefficients. The performance increase can be explained by the fact, that the transfer functions applied to the signals have attenuated certain frequency components of the noise signal, making it easier for the \ac{ANR} algorithm to isolate and reduce the noise from the corrupted signal. Also, the corruption noise signal is reduced in amplitude, whereas the reference noise signal is amplified in certain frequency areas, which helps the \ac{ANR} algorithm to better identify and cancel out the noise components from the corrupted signal.
+\noindent The error signal in Figure \ref{fig:fig_plot_2_wav_complex.png} shows, as expected, also a similar amplitude compared to the previous intermediate use case, indicating that the \ac{ANR} algorithm is still working fine. The \ac{SNR}-Gain of 6.98 dB indicates a quite sucessful noise reduction, even with just 16 taps in this more complex scenario.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_2_wav_complex.png}

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chapter_04.tex

@@ -1,12 +1,12 @@
-\section{Hardware implementation and optimization of the ANR Algorithm on a low-power system}
+\section{Hardware implementation and performance quantization of the ANR Algorithm on a low-power system}
-This section can be considered as the heart of this thesis. The first subchapter describes the hardware, on which the \ac{ANR} algorithm is implemented, including its environment, which serves as a link to the \ac{CI} system itself. The following subchapter continues with the basic implementation of the \ac{ANR} algorithm on the hardware itself and shall provide the reader with a basic understanding of its challenges, possibilities and limitations. This basic implementation is then low-level simulated with some of the previuous use cases to get some idea of the general performance.\\
+This section can be considered as the heart of this thesis. The first subchapter describes the hardware, on which the \ac{ANR} algorithm is implemented, including its environment, which serves as a link to the \ac{CI} system itself. The following subchapter continues with the basic implementation of the \ac{ANR} algorithm on the hardware itself and shall provide the reader with a basic understanding of its challenges, possibilities and limitations. This basic implementation is then low-level simulated with some of the previous use cases to get some idea of the general performance.\\
 The last subchapter picks the final optimizations of the \ac{ANR} algorithm itself as a central theme, especially with respect to the capabilities of a hybrid \ac{ANR} approach.
 \subsection{Low-power system architecture and integration}
 This thesis considers a low-power \ac{SOC} architecture that integrates a general-purpose \ac{ARM} core with a dedicated \ac{DSP} core. The system combines the flexibility of an \ac{ARM}-based control processor with the computational efficiency of a specialized \ac{DSP}, splitting general computing tasks from real-time signal processing workloads.
 \subsubsection{ARM and DSP hardware architecture overview}
 A 32-bit \ac{ARM} core serves as the primary control unit of the system. It is responsible for high-level application logic, system configuration, peripheral management as also scheduling and serves as a general-purpose processing unit. Due to its universal instruction set and extensive input/output interface, the \ac{ARM} core is well suited for handling general tasks and the interaction with the \ac{CI} system. Time-critical numerical processing is intentionally offloaded to the \ac{DSP} core in order to reduce computational load and power consumption on the control processor.\\ \\
-The \ac{DSP} used for the implementation features a 32-bit dual Harvard, dual \ac{MAC} architecture primarily designed for audio signal-processing applications in low-power embedded systems. It doesn´t feature a designated boot ROM, as it is initialized and managed by the \ac{ARM} core. The firmware executing the \ac{ANR} algorithm is developed and programmed in the C programming language. The used propretiery compiler is highly efficient and generates optimized assembler code, which is then translated in machine code to execute the \ac{ANR} algorithm on incoming samples.\\ \\
+The \ac{DSP} used for the implementation features a 32-bit dual Harvard, dual \ac{MAC} architecture primarily designed for audio signal-processing applications in low-power embedded systems. It doesn't feature a designated boot ROM, as it is initialized and managed by the \ac{ARM} core. The firmware executing the \ac{ANR} algorithm is developed and programmed in the C programming language. The used proprietary compiler is highly efficient and generates optimized assembler code, which is then translated in machine code to execute the \ac{ANR} algorithm on incoming samples.\\ \\
-All memory instances and registers of the \ac{SOC} are directly addressable by the \ac{ARM} through the standard busses, also enabling a simplified control of the \ac{DSP} through a shared memory section. The memory consists mainly out of the two followng parts:
+All memory instances and registers of the \ac{SOC} are directly addressable by the \ac{ARM} through the standard buses, also enabling a simplified control of the \ac{DSP} through a shared memory section. The memory consists mainly out of the two following parts:
 \begin{itemize}
     \item \textbf{Program Memory:} This memory section stores the executable code for both the \ac{ARM} core and the \ac{DSP} core. It contains the compiled instructions that define the behavior of the system, including the \ac{ANR} algorithm implemented on the \ac{DSP}.
     \item \textbf{Data Memory:} This memory section is used for storing runtime data and variables, required during the execution of the program. This also includes the memory section for input/output audio samples and intermediate processing results. The shared memory section between the \ac{ARM} core and the \ac{DSP} core is also part of the data memory, featuring a total size of 64 KB.
@@ -15,15 +15,15 @@ The data memory is supported by an integrated \ac{DMA} controller, which allows
 When the \ac{DSP} is not required to process audio data, it can be paused by pausing the clock provided to the \ac{DSP} core. When paused, the \ac{DSP} core enters a low-power state, still allowing the \ac{ARM} core to access its shared memory and wake up the \ac{DSP} core when needed. This mechanism helps to reduce overall power consumption, which is crucial for battery-operated devices like cochlear implants.\\ \\
 The processing unit of the \ac{DSP} is equipped with load/store architecture, meaning that, initially all operands need to be moved from the memory to the registers, before any operation can be performed. After this task is performed, the execution units (\ac{ALU} and multiplier) can perform their operations on the data and write back the results into the registers. Finally, the results need to be explicitly moved back to the memory.\\ \\
 Processor-wise, the \ac{DSP} includes a three stage pipeline consisting of fetch, decode, and execute stages, allowing for overlapping instruction execution and improved throughput. The architecture is optimized for high cycle efficiency when executing computationally intensive signal-processing workloads. The featured dual Harvard, dual \ac{MAC} architecture (two separate \ac{ALU}s) enables the execution of two \ac{MAC} operations, two memory operations (load/store) and two pointer updates in a single processor cycle.
-\subsubsection{Inter-core communication mechanisms}
+\subsubsection{Intercore communication mechanisms}
-In order to ensure a smooth, but power-efficient, operation together with the \ac{CI} system, a interrupt-driven communication between the \ac{ARM} core and the \ac{DSP} core is crucial. Center of communication between the the cores is the already mentioned shared memory region accessible by both processing units. This shared memory enables the exchange of data without the need for separate communication protocols or input/output interfaces (refer to Figure \ref{fig:fig_dsp_setup.jpg}). Synchronization between the cores is achieved using interrupt-based signaling: the \ac{ARM} core initiates processing requests by waking up the \ac{DSP} and triggering an interrupt which sets an action flag, while the \ac{DSP} notifies the \ac{ARM} core upon completion of a task also by changing an interrupt register (for simplicity reasons, this behaviour will be just called ``interrupts'' in the remaining thesis). This approach ensures efficient coordination while minimizing active waiting (polling) and therefore unnecessary power consumption.
+In order to ensure a smooth, but power-efficient, operation together with the \ac{CI} system, an interrupt-driven communication between the \ac{ARM} core and the \ac{DSP} core is crucial. Center of communication between the cores is the already mentioned shared memory region accessible by both processing units. This shared memory enables the exchange of data without the need for separate communication protocols or input/output interfaces (refer to Figure \ref{fig:fig_dsp_setup.jpg}). Synchronization between the cores is achieved using interrupt-based signaling: the \ac{ARM} core initiates processing requests by waking up the \ac{DSP} and triggering an interrupt which sets an action flag, while the \ac{DSP} notifies the \ac{ARM} core upon completion of a task also by changing an interrupt register (for simplicity reasons, this behavior will be just called ``interrupts'' in the remaining thesis). This approach ensures efficient coordination while minimizing active waiting (polling) and therefore unnecessary power consumption.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_setup.jpg}
     \caption{Simplified visualization of the interaction between the \ac{CI}-System, the \ac{ARM} core and the \ac{DSP} core, making use of the \ac{PCM} interface and shared memory for audio data exchange.}
     \label{fig:fig_dsp_setup.jpg}
 \end{figure}
-\noindent The \ac{ARM} Core receives the 16-bit audio data (the corrupted signal and the reference noise signal via two channels) from the CI system via a \ac{PCM} interface, which offers one 32-bit input and one 32-bit output register. An interrupt triggers the integrated \ac{DMA} controller when the input register is occupied, which transfers the audio data from the \ac{PCM} interface to the input buffer in a predefined memory location (now in two 16-bit samples again). Once completed, the \ac{DSP} core is requested to start processing the audio data. The \ac{DSP} core then reads the audio samples from the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the a 16-bit processed sample back to an output buffer, also located in the shared memory. Finally, the \ac{ARM} core is notified via an interrupt from the \ac{DSP} core, that the processing is complete - the \ac{DMA} controller then transfers the processed audio samples from the output buffer back to the \ac{PCM} interface for playback (refer to Figure \ref{fig:fig_dsp_comm.jpg}).\\ \\ 
+\noindent The \ac{ARM} Core receives the 16-bit audio data (the corrupted signal and the reference noise signal via two channels) from the CI system via a \ac{PCM} interface, which offers one 32-bit input and one 32-bit output register. An interrupt triggers the integrated \ac{DMA} controller when the input register is occupied, which transfers the audio data from the \ac{PCM} interface to the input buffer in a predefined memory location (now in two 16-bit samples again). Once completed, the \ac{DSP} core is requested to start processing the audio data. The \ac{DSP} core then reads the audio samples from the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the 16-bit processed sample back to an output buffer, also located in the shared memory. Finally, the \ac{ARM} core is notified via an interrupt from the \ac{DSP} core, that the processing is complete - the \ac{DMA} controller then transfers the processed audio samples from the output buffer back to the \ac{PCM} interface for playback (refer to Figure \ref{fig:fig_dsp_comm.jpg}).\\ \\ 
 \begin{figure}[H]
     \centering
     \includegraphics[width=0.9\linewidth]{Bilder/fig_dsp_comm.jpg}
@@ -34,11 +34,11 @@ In order to ensure a smooth, but power-efficient, operation together with the \a
 \subsection{Software architecture and execution flow}
 \subsubsection{ARM–DSP communication and data exchange details}
 In contrary, to the high-level simulation environment written in Python from the previous chapter, the implementation of the \ac{ANR} algorithm on the \ac{DSP} requires a low-level programming approach, as which takes into account the specific architecture and capabilities of the processor and its environment. This includes considerations such as memory management, data types, and optimization techniques specific to the \ac{DSP} architecture. The implementation is required to be done in the C programming language, which is a standard for embedded systems, as it allows low-level hardware implementation.\\ \\ 
-The implementation of the \ac{ANR} algorithm on the \ac{DSP} follows the same overall structure as the high-level variant, but now the focus lies on memory management, interrupt-handling and communication between the two cores. The \ac{ARM} operates in a continious loop, structured into several states:
+The implementation of the \ac{ANR} algorithm on the \ac{DSP} follows the same overall structure as the high-level variant, but now the focus lies on memory management, interrupt-handling and communication between the two cores. The \ac{ARM} operates in a continuous loop, structured into several states:
 \begin{itemize}
     \item \textbf{Idle:} The \ac{ARM} core waits for an interrupt from the \ac{DMA} controller, indicating that new audio samples are available in the input buffer.
     \item \textbf{Work:} After receiving the interrupt, the \ac{ARM} core triggers an interrupt on the \ac{DSP} core to start processing the audio samples.
-    \item \textbf{Wait:} After recieving the first interrupt, which signals that the \ac{DSP} startedprocessing the sample, the \ac{ARM} core waits for the second interrupt, indicating that the processing is complete.
+    \item \textbf{Wait:} After receiving the first interrupt, which signals that the \ac{DSP} started processing the sample, the \ac{ARM} core waits for the second interrupt, indicating that the processing is complete.
     \item \textbf{Done/Idle:} Once the processing is complete, the \ac{ARM} core triggers the \ac{DMA} controller to transfer the processed audio samples from the output buffer back to the \ac{PCM} interface for playback. The \ac{ARM} core then returns to the idle state, waiting for the next batch of audio samples.
 \end{itemize}
 On the contrary, the \ac{DSP} core operates in an interrupt-driven manner:
@@ -51,15 +51,15 @@ On the contrary, the \ac{DSP} core operates in an interrupt-driven manner:
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_dma.jpg}
-    \caption{Detailed visualization of the \ac{DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggerd, either to the \ac{DSP} core or to the \ac{ARM} core, depending if triggered during a Read- or Write-operation.}
+    \caption{Detailed visualization of the \ac{DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggered, either to the \ac{DSP} core or to the \ac{ARM} core, depending on, if triggered during a Read- or Write-operation.}
     \label{fig:fig_dsp_dma.jpg}
 \end{figure}
 \noindent Figure \ref{fig:fig_dsp_dma.jpg} visualizes the concrete operation of the \ac{DMA} controller during the audio sample processing. The \ac{DMA} controller is configured to samplewise transfer the audio samples from the \ac{PCM} interface to the input buffer of the shared memory. When the input buffer is filled with one sample of both channels, an interrupt is triggered to the \ac{DSP} core, notifying it to start processing the available samples. After processing, the results are written into the output buffer in the shared memory. Once the output buffer is occupied, another interrupt is triggered to the \ac{DMA} controller, indicating that the processed samples are ready to be transferred back to the \ac{PCM} interface for playback. \\ \\
-As the \ac{ARM} operation is not the main focus of this thesis and its behavior is already sufficiently described, further implementaion details will be omitted in the following while the focus will be put on implementation of the \ac{ANR} algorithm on the \ac{DSP} core itself.
+As the \ac{ARM} operation is not the main focus of this thesis and its behavior is already sufficiently described, further implementation details will be omitted in the following while the focus will be put on implementation of the \ac{ANR} algorithm on the \ac{DSP} core itself.
 \subsubsection{System control flow and main processing loop}
 The implementation of the \ac{ANR} algorithm on the \ac{DSP} core is structured into several key sections, each responsible for specific aspects of the algorithm's functionality. The following paragraphs outline the main components:
 \paragraph{Memory initialization and mapping}
-The memory initialization section starts with the definition of the interrupt register (0xC00004) and the corresponding bit masks used to control the interrupt behavior of the \ac{DSP} core. Afterwards, a section in the shared memory is defined for the storage of input and output audio samples after/before the transport to/from the \ac{PCM} interface. The output section is initialized with an offset of 16 bytes from the input section (0x800000), resulting in a storage capability of 4 32-bit double-words for each of the two memory sections - this is more than needed, but prevents future memory relocation, if the necessety for more space would arise. After this initialization, the interrupt register and the memory sections are declared as volatile variables, telling the compiler, that these variables can be changed outside the normal program flow (e.g., by hardware interrupts), preventing certain optimizations. The final input/output buffers are then declared in form of two 16-bit arrays, consisting of 4 elements each. Finally, a variable is declared to signal the \ac{DSP} core, an interrupt has occured, which changes the state of the interrupt register and signals a processing request.
+The memory initialization section starts with the definition of the interrupt register (0xC00004) and the corresponding bit masks used to control the interrupt behavior of the \ac{DSP} core. Afterwards, a section in the shared memory is defined for the storage of input and output audio samples after/before the transport to/from the \ac{PCM} interface. The output section is initialized with an offset of 16 bytes from the input section (0x800000), resulting in a storage capability of 4 32-bit double-words for each of the two memory sections - this is more than needed, but prevents future memory relocation, if the necessity for more space would arise. After this initialization, the interrupt register and the memory sections are declared as volatile variables, telling the compiler, that these variables can be changed outside the normal program flow (e.g., by hardware interrupts), preventing certain optimizations. The final input/output buffers are then declared in form of two 16-bit arrays, consisting of 4 elements each. Finally, a variable is declared to signal the \ac{DSP} core, an interrupt has occurred, which changes the state of the interrupt register and signals a processing request.
 \begin{figure}[H]
     \centering
     \begin{lstlisting}[language=C]
@@ -80,16 +80,16 @@ The memory initialization section starts with the definition of the interrupt re
     \label{fig:fig_dps_code_memory}
     \caption{Low-level implementation: Memory initialization and mapping}
 \end{figure}
-\noindent Figure \ref{fig:fig_compiler.jpg} shows an exemplary memory map of the input buffer array, taken from the compiler debugger. As the array is initialized as a 16 bit integer array, each element occupies 2 bytes of memory.
+\noindent Figure \ref{fig:fig_compiler.jpg} shows an exemplary memory map of the input buffer array, taken from the compiler debugger. As the array is initialized as a 16-bit integer array, each element occupies 2 bytes of memory.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_compiler.jpg}
-    \caption{Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16 bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise adressing is a result of the compiler abstraction.}
+    \caption{Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16-bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise addressing is a result of the compiler abstraction.}
     \label{fig:fig_compiler.jpg}
 \end{figure}
 \paragraph{Main loop and interrupt handling}
-The main loop of the \ac{DSP} core is quite compact, as it mainly focuses on handling interrupts and delegating the sample processing to the \ac{ANR} function. The loop starts by enabling interrupts with a compiler-specific function and setting up pointers for the output buffer and the sample variable. After setting the action flag to zero, the main function enters an infinite loop, signaling the \ac{ARM} core it´s halted state by setting the interrupt register to 1 and halting the core.\\ \\
+The main loop of the \ac{DSP} core is quite compact, as it mainly focuses on handling interrupts and delegating the sample processing to the \ac{ANR} function. The loop starts by enabling interrupts with a compiler-specific function and setting up pointers for the output buffer and the sample variable. After setting the action flag to zero, the main function enters an infinite loop, signaling the \ac{ARM} core it's halted state by setting the interrupt register to 1 and halting the core.\\ \\
-If the \ac{ARM} core requests a sample to be processed, it activates the \ac{DSP} core and triggers an interrupt, which sets the action flag to 1. The main loop then checks the action flag, and sets the interrupt register back to 0, indicating the \ac{ARM} core it is now processing the sample. After resetting the action flag, the output pointer is updated to point to the next position in the output buffer using a cyclic addition function. Before triggering the calc()-function, the calculated sample from the previous cycle is moved from its temporary memory location to the current position in the output buffer. Afterwards, the calc()-function is triggered for the current cycle and the loop restarts. The flow diagram in Figure \ref{fig:fig_dsp_logic.jpg} visualizes the described behavior of the main loop and interrupt handling on the \ac{DSP} core.
+If the \ac{ARM} core requests a sample to be processed, it activates the \ac{DSP} core and triggers an interrupt, which sets the action flag to 1. The main loop then checks the action flag, and sets the interrupt register back to 0, indicating the \ac{ARM} core it is now processing the sample. After resetting the action flag, the output pointer is updated to point to the next position in the output buffer using a cyclic addition function. Before triggering the calculate\_output()-function, the calculated sample from the previous cycle is moved from its temporary memory location to the current position in the output buffer. Afterwards, the calculate\_output()-function is triggered for the current cycle and the loop restarts. The flow diagram in Figure \ref{fig:fig_dsp_logic.jpg} visualizes the described behavior of the main loop and interrupt handling on the \ac{DSP} core.
 \begin{figure}[H]
     \centering
     \begin{lstlisting}[language=C]
@@ -106,7 +106,7 @@ If the \ac{ARM} core requests a sample to be processed, it activates the \ac{DSP
                     action_required = 0;     
                     out_pointer = cyclic_add(output_pointer, 2, output_port, 4); 
                     *output_pointer = *sample_pointer;
-                    calc(&corrupted_signal, &reference_noise_signal, mode, &input_port[1], &input_port[0], sample_pointer);
+                    calculate_output(&corrupted_signal, &reference_noise_signal, mode, &input_port[1], &input_port[0], sample_pointer);
                 }
             }
         }
@@ -120,8 +120,8 @@ If the \ac{ARM} core requests a sample to be processed, it activates the \ac{DSP
     \caption{Flow diagram of the code implementation of the main loop and interrupt handling on the \ac{DSP} core.}
     \label{fig:fig_dsp_logic.jpg}
 \end{figure}
-\paragraph{Calc()-function}
+\paragraph{calculate\_output()-function}
-The calc()-function at the very end of the main process loop represents the heart of the \ac{DSP}code, as it is responsible for applying the \ac{ANR} algorithm on the two input samples. As it follows the same structure as the high-level implementation described in the previous chapter, the general functionality will not be described in detail again. The technical implementation on the \ac{DSP} however will be outlined in detail in the following subchapter, as the hardware-specific optimizations, responsible for a real-time capable implementation, are a key element for the estimation of the expectable power consumption of the system.\\ \\
+The calculate\_output()-function at the very end of the main process loop represents the heart of the \ac{DSP} code, as it is responsible for applying the \ac{ANR} algorithm on the two input samples. As it follows the same structure as the high-level implementation described in the previous chapter, the general functionality will not be described in detail again. Yet, the technical implementation on the \ac{DSP} however will be outlined in detail in the following subchapter, as the hardware-specific optimizations are key elements for the estimation of the expectable power consumption of the system.\\ \\
 
 \subsection{DSP-level implementation of the ANR algorithm}
 The ability to process audio samples in real-time on the \ac{DSP} core is strongly dependent on compiler-specific optimizations and hardware-specific implementation techniques, which allow a far more efficient execution of the algorithm compared to a native C implementation. 
@@ -137,7 +137,7 @@ The simple function shown in Figure \ref{fig:fig_dsp_code_find_max} returns the
         return (a > b) ? a : b;
     }   
     \end{lstlisting}
-    \caption{Manual implementation of function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operations.}
+    \caption{Manual implementation of a max-function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operation.}
     \label{fig:fig_dsp_code_find_max}
 \end{figure}  
 \paragraph{Cyclic array iteration}
@@ -156,17 +156,117 @@ Basically every part of the \ac{ANR} algorithm relies on iterating through memor
         return new_pointer;
     }
     \end{lstlisting}
-    \caption{Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute an pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}
+    \caption{Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute a pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}
     \label{fig:fig_dsp_code_cyclic_add}
 \end{figure}  
 \noindent Figure \ref{fig:fig_dsp_code_cyclic_add} shows a manual implementation of such a cyclic array iteration function in C, which updates the pointer to a new address. This implementation takes the \ac{DSP} 20 cycles to execute, while the already implemented compiler-optimized version only takes one cycle, making use of the specific architecture of the \ac{DSP} allowing such a single-cycle operation.
 \paragraph{Fractional fixed-point arithmetic}
-As already mentioned during the beginning of the current chapter, the used \ac{DSP} is a fixed point processor, meaning, that it does not support floating-point arithmetic natively. Instead, it relies on fixed-point arithmetic, which represents numbers as integers scaled by a fixed factor. This is a key requirement, as it allows the use of the implemented dual \ac{MAC} \ac{ALU}s. This approach is also faster and more energy efficient, and therefore more suitable for embedded systems. However, it also introduces challenges in terms of precision and range, which need to taken into account when conducting certain calculations.\\ \\
+As already mentioned during the beginning of the current chapter, the used \ac{DSP} is a fixed point processor, meaning, that it does not support floating-point arithmetic natively. Instead, it relies on fixed-point arithmetic, which represents numbers as integers scaled by a fixed factor. This is a key requirement, as it allows the use of the implemented dual \ac{MAC} \ac{ALU}s. This approach is also faster and more energy efficient, and therefore more suitable for embedded systems. However, it also introduces challenges in terms of precision and range, which need to be taken into account when conducting certain calculations.\\ \\
 To tackle this issues, the \ac{DSP} compiler provides intrinsic functions for fractional fixed-point arithmetic, such as a fractional multiplication function, which takes two 32-bit integers as input and return an already bit-shifted 64-bit output, representing the fractional multiplication result. This approach prevents the need for manual bit-shifting operations after each multiplication.\\ \\
 To support such operations, a 72-bit accumulator is provided, allowing to store intermediate 64-bit results of 32-bit multiplications without losing precision - the remaining 8 bit serve as an overflow space. If needed, a saturation function is also provided, to round the 64-bit result back to a 32-bit value.
 
-\subsubsection{Performance evaluation and quantization of the DSP implementation}
+\subsubsection{Performance quantization of the ANR calculation}
-
+The $calculate\_output()$-function, forms the center of the \ac{ANR} algorithm on the \ac{DSP} core and is responsbile for the actual processing of the audio samples. The general functionality of the function in C is the same as in the high-level implementation (refer to Figure \ref{fig:fig_anr_logic}), and will therefore not be described in detail again. The main focus lies now on the computational efficiency of the different parts of the function, with the goal of generating a formula by quantizizing the computational effort of the different sub-parts in relation to changeable parameters like the filter length.\\ \\
-
+The $calculate\_output()$ functions consists out of the following five main parts:
+\begin{itemize}
+    \item $write\_buffer$: Pointer handling and buffer management
+    \item $apply\_fir\_filter$: Application of the \ac{FIR} filter on the reference noise signal
+    \item $update\_output$: Calculation of the output sample (=error signal)
+    \item $update\_filter\_coefficients$: Update of the \ac{FIR} filter coefficients based on the error signal
+    \item $write\_output$: Writing the output sample back to the output port in the shared memory section
+\end{itemize}
+These sub-functions feature \ac{DSP}-spefic optimizations and are partly depenend on the setable parameters like the filter length in regard of their computational cost. The following paragraphs will analyze the computational efficiency of these sub-functions in detail.
+\paragraph{write\_buffer}The $write\_buffer$-function is responsible for managing the input line, where the samples of the reference noise signal are stored for further processing. The buffer management mainly consits out of a cyclic pointer increase operation and a pointer dereference operation to write the new sample into the buffer. The cyclic pointer increase operation is implemented using the already mentioned intrinsic function of the \ac{DSP} compiler, while the pointer dereference operation takes 15 cycles to execute. This results in a total duration of 16 cycles for the $write\_buffer$-function to process, indipentent of the filter length or other parameters.
+\paragraph{apply\_fir\_filter} The $apply\_fir\_filter$-function is responsible for applying the coefficients of the \ac{FIR} filter on the reference noise signal samples stored in the input line. The needed cycles for this function are mainly depenendent on the lenght of the filter, as the number of multiplications and additions increase with the filter length. To increase the performance, the dual \ac{MAC} architecture of the \ac{DSP} is utilized, allowing two multiplications and two additions to be performed in a single cycle. Another \ac{DSP}-specific optimization is the use of the already introduced 72-bit accumulators and the fractional multiplication function, which allows performing multiplications on two 32-bit integers without losing precision or the need for manual bit-shifting operations.
+\begin{figure}[H]
+    \centering
+    \begin{lstlisting}[language=C]
+        for (int i=0; i < n_coeff; i+=2) chess_loop_range(1,){
+            x0 = *p_x0;
+            w0 = *p_w; 
+            p_w++;      
+            p_x0 = cyclic_add(p_x0, -1, p_xstart, sample_line_len); 
+            x1 = *p_x0; 
+            w1 = *p_w; y
+            p_w++;    
+            p_x0 = cyclic_add(p_x0, -1, p_xstart, sample_line_len); 
+
+            acc_fir_1+=fract_mult(x0, w0);
+            acc_fir_2+=fract_mult(x1, w1);
+        }    
+    \end{lstlisting}
+    \caption{Code snippet of the $apply\_fir\_filter$-function, showing the use of the dual \ac{MAC} architecture of the \ac{DSP} and the fractional multiplication function. The loop iterates through the filter coefficients and reference noise signal samples, performing two multiplications and two additions in each cycle.}
+    \label{fig:fig_dsp_code_apply_fir_filter}
+\end{figure}
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_fir_cycle.jpg}
+    \caption{Visualization of the FIR filter calculation in the $apply\_fir\_filter$-function during the 2nd cyclce of a calculation loop. The reference noise signal samples are stored in the sample line, while the filter coefficients are stored in a separate memory section (filter line).}
+    \label{fig:fig_dsp_fir_cycle.jpg}
+\end{figure}
+\noindent The final result is represented in a computing effort of 1 cycle per item in the sample line buffer (which equals the filter length) plus 12 cycles for general function overhead, resulting in a total of $N+12$ cycles for the $apply\_fir\_filter$-function, with $N$ being the filter length.
+\paragraph{update\_output} The $update\_output$-function is responsible for calculating the output sample based on the error signal and the accumulated filter output. The calculation is a simple subtraction and only takes 1 cycle to execute, independent of the filter length or other parameters.
+\paragraph{update\_filter\_coefficient} The $update\_filter\_coefficient$-function represents the second computationally expensive part of the $calculate\_output()$-function. The calculated output from the previous function is now multiplied with the step size and the corresponding sample from the reference noise signal, which is stored in the sample line buffer. The result is then added to the current filter coefficient to update it for the next cycle. Again, \ac{DSP}-specific optimizations, like the dual \ac{MAC} architecture, are used, resulting in a computing effort of 6 cycles per filter coeffcient. Per function call, an overhead of 8 cycles is added, resulting in a total of $6*N+8$ cycles for the $update\_filter\_coefficient$-function, with $N$ again being the filter length.
+\begin{figure}[H]
+    \centering
+    \begin{lstlisting}[language=C]
+        for (int i=0; i< n_coeff; i+=2) chess_loop_range(1,){
+        lldecompose(*((long long *)p_w0), w0, w1);
+        acc_w0 = to_accum(w0);    
+        acc_w1 = to_accum(w1);
+
+        acc_w0 += fract_mult(correction, *p_x0); 
+        acc_w1 += fract_mult(correction, *p_x1);
+
+        p_x0 = cyclic_add(p_x0, -2, p_xstart, sample_line_len);
+        p_x1 = cyclic_add(p_x1, -2, p_xstart, sample_line_len);
+        
+        *((long long *)p_w0) = llcompose(rnd_saturate(acc_w0), rnd_saturate(acc_w1));
+        p_w0+=2; 
+    }   
+    \end{lstlisting}
+    \caption{Code snippet of the $update\_filter\_coefficient$-function, again making use of the dual \ac{MAC} architecture of the \ac{DSP} and the fractional multiplication function. Additionaly,  32-bit values are loaded and stored as 64-bit values, using two also intrinisc functions, allowing to update two filter coefficients in a single cycle.}
+    \label{fig:fig_dsp_code_update_filter_coefficients}
+\end{figure}
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_coefficient_cycle.jpg}
+    \caption{Visualization of the coefficient calculation in the $update\_filter\_coefficient$-function during the 2nd cyclce of a calculation loop. The output is multiplied with the step size and the corresponding sample from the sample line, before being added to the current filter coefficient.}
+    \label{fig:fig_dsp_coefficient_cycle.jpg}
+\end{figure}
+\paragraph{write\_output} The $update\_output$-function is responsible for writing the  calculated output sample back into the shared memory section. The operation takes 5 cycles to execute, independent of the filter length or other parameters.
+\noindent The total computing effort of the $calculate\_output()$-function in dependency of the filter length $N$ can now be calculated by summing up the computing efforts of the different sub-functions:
+\begin{equation}
+\label{equation_computing}
+    \begin{aligned}
+    C_{total} = C_{write\_buffer} + C_{apply\_fir\_filter} + C_{update\_output} + \\
+    C_{update\_filter\_coefficient} + C_{write\_output}
+    \end{aligned}
+\end{equation}
+The sub-functions can seperatly be expressed in dependency of the filter length $N$ and also in dependency of the update rate of the filter coefficients, which is represented by the parameter $1/U$ (e.g., if the coefficients are updated every 2 cycles, $1/U$ would result in a vaule of 0.5):
+\begin{gather}
+\label{equation_c_1}
+ C_{write\_buffer} = 16 \\
+ \label{equation_c_2}
+C_{apply\_fir\_filter} = N + 12 \\
+ \label{equation_c_3}
+C_{update\_output} = 1 \\
+ \label{equation_c_4}
+C_{update\_filter\_coefficient} = \frac{1}{U}(6*N + 8)\\
+ \label{equation_c_5}
+C_{write\_output} = 5 \\
+\end{gather}
+\noindent By inserting the sub-function costs into the total computing effort formula, Equation \ref{equation_computing} can now be expressed as:
+\begin{equation}
+\label{equation_computing_final}
+ C_{total} = N + \frac{6*N+8}{U} + 34
+\end{equation}
+Equation \ref{equation_computing_final} now provides an estimation of the necessary computing effort for one output sample in relation to the filter length $N$ and the update rate of the filter coefficients $1/U$. This formula can now be used to estimate the needed computing power (and therefore the power consumption) of the \ac{DSP} core for different parameter settings, alowing to find an optimal parameter configuration in regard of the quality of the noise reduction and the power consumption of the system.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_c_total.png}
+    \caption{Dependence of the total computing effort on the filter length $N$ and update rate $1/U$.}
+    \label{fig:fig_c_total.png}
+\end{figure}
 
 

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chapter_05.tex

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+\section{Performance evaluation of different implementation variants}
+\subsection{Verification of the \ac{DSP} implementation}
+To verify the general performance of the \ac{DSP}-implemented \ac{ANR} algorithm, the complex usecase of the high-level implemenation is utilized, which includes, again, a 16-tap \ac{FIR} filter and an update of the filter coefficients every cycle. In contary to the high-level implementation, the coeffcient convergence is now not included in the evaluation anymore, but the metric for the \ac{ANR} performance stays the same as the \ac{SNR}-improvement.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_1_dsp_complex.png}
+    \caption{Desired signal, corrupted signal, reference noise signal and filter output of the complex \ac{ANR} use case, simulated on the \ac{DSP}}
+    \label{fig:fig_plot_1_dsp_complex.png}
+\end{figure}
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_plot_2_dsp_complex.png}
+    \caption{Error signal of the complex \ac{ANR} use case, simulated on the \ac{DSP}}
+    \label{fig:fig_plot_2_dsp_complex.png}
+\end{figure}
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_high_low_comparison.png}
+\caption{Comparison of the high- and low-level simulation output. The Pearson coefficient shows a correlation of above 99\% between the two graphs.}
+    \label{fig:fig_high_low_comparison.png}
+\end{figure}  
+\noindent Figure \ref{fig:fig_plot_1_dsp_complex.png} and \ref{fig:fig_plot_2_dsp_complex.png} show the results of the complex \ac{ANR} use case, simulated on the \ac{DSP} - with a \ac{SNR}-Gain of 6.98 dB it performs equivalent as the one of the high-level implementation. Figure \ref{fig:fig_high_low_comparison.png} shows both outputs seperately and then together in one sub figure. The \ac{DSP} output which features a Perason correlation of 99.3\% against the high-level output, again indicating the correct functionality of the \ac{DSP} implementation. The small difference can be explained by the fact that the \ac{DSP} implementation is based on fixed-point arithmetic, which leads to a slightly different convergence behavior. Nevertheless, the results show that the \ac{DSP} implementation of the \ac{ANR} algorithm is able to achieve the same performance as the high-level implementation, again indicating the fact, that 16 filter coefficients are sufficent to filter out a complex but synchrone noise signal. In reality, the \ac{ANR} algorithm is confronted with delayed signals, as the sensors are located im different positions. The next step is of evaluate the performance of the \ac{DSP} implementation in terms of computational efficiency under different scenarios and non-synchrone signals.
+\subsection{Computational efficiency evaluation}
+\noindent The main focus for evaluating the computational efficiency is the determination of the optimal filter length. To achieve this goal, different signal combinations, which are to be expected everyday situiations for a \ac{CI} patient, are considered. Now, also, a delay of 2ms bewteen the corrupted signal an the reference noise signal is applied, increasing the need for a longer filter. The desired signal of a male voice over speaker is now corrupted with 5 different noise signals, ruling out, that a certain combination of signals is not representative for the overall performance of the \ac{ANR} algorithm:
+\begin{itemize}
+    \item Breathing noise: Already used in the high-level implementation, this noise signal is a typical noise source for \ac{CI} patients, especially in quiet environments. It consists out of slowly rising and falling maxima.
+    \item Coughing noise: This noise signal is generated by coughing and consists out few, but long lasting maxima, showing similarities to a rectangular function.
+    \item Scratching noise: This noise signal is generated by scratching some material with finger nails, like the hair or clothes. It consists out of a high number of sharp peaks.
+    \item Drinking Noise: This noise signal is generated by swallowing a liquid and consists out of a low number of sharp peaks, featuring long pauses between them.
+    \item Chewing Noise: This noise signal is generated by consuming food and consists out of a high number of peaks of different amplitude.
+\end{itemize}
+The vizualization of the noise signals is shown in Figure \ref{fig:fig_noise_signals.png}.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_noise_signals.png}
+    \caption{Noise signals used to corrupt the desired signal in the computational efficiency evaluation}
+    \label{fig:fig_noise_signals.png}
+\end{figure}  
+\noindent The combination of stated sets delivers five different scenarious, everyone different in regard of it's challenges for the \ac{ANR} algorithm. For every scenario, the \ac{SNR}-Gain is calculated with an increasing set of filter coeffcients, ranging from 16 to 64.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_snr_comparison.png}
+    \caption{Simulation of the to be expected \ac{SNR}-Gain for different noise signals and filter lengths applied to the desired signal of a male speaker. The applied delay between the signals amounts 2ms. The graphs are smoothed by a third order savigol filter.}
+    \label{fig:fig_snr_comparison.png}
+\end{figure}  
+\noindent Figure \ref{fig:fig_snr_comparison.png} shows the expected \ac{SNR}-Gain for the different noise signals and filter lengths. The results shows, that a minimum filter length of about 32 taps is required, before (in any case) a significant rise in the \ac{SNR}-Gain can be observed - this is highly contrary to the sinchronous high-level simulation, where a filter length of only 16 taps provided sufficent noise reduction. This circustance can be explained by the fact, that the reference noise signal is now delayed, meaning, that the filter needs a certain length before it can react. The results also show, that the \ac{SNR}-Gain is different for the different noise signals, indicating, that the noise signals have different characteristics, like the number of peaks, their frequency spectrum an their amplitude.\\ \\
+The mean \ac{SNR}-Gain of the different noise signals, also shown in Figure \ref{fig:fig_snr_comparison.png}, signals, that after reaching 95\% of the maximum \ac{SNR}-Gain, the \ac{SNR}-Gain increase is slowing down. This threshold is reached at a filter length of 45 taps. This means, that a filter length of 45 taps represents an optimal solution for a statisfying performance of the \ac{ANR} algorithm, while a further increase of the filter length does not lead to a significant increase of the \ac{SNR}-Gain. This is an important finding, as it allows to optimize the computational efficiency of the \ac{ANR} algorithm by choosing an appropriate filter length.
+\subsection{Evaluation of the computational load for fixed implementation}
+\subsubsection{Full-Update implementation}
+\noindent Equation \ref{equation_computing_final} can now be utilized to calculate the needed cycles for the calculation of one sample of the filter output, using a filter length of 45 taps and an update of the filter coefficients every cycle. The needed cycles are calculated as follows:
+\begin{equation}
+\label{equation_computing_calculation}
+ C_{total} = 45 + \frac{6*45+8}{1} + 34 = 357 \text{ cycles}
+\end{equation}
+As already mentioned in the previous chapters, the sampling rate of the audio data provided to the \ac{PCM} interface amounts 20 kHz. The prefered clock frequency of the \ac{DSP} is chosen as 16 MHz, which means, that the \ac{DSP} core has cycle budget of
+\begin{equation}
+\label{equation_cycle_budget}
+    C_{budget} = \frac{16 MHz}{20 kHz} = 800 \text{ cycles}
+\end{equation}
+\noindent for one sample. With these two values, the load of the \ac{DSP} core can be calculated as follows:
+\begin{equation}
+\label{equation_load_calculation}
+    Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{357 \text{ cycles}}{800 \text{ cycles}} = 44.6 \%
+\end{equation}
+\noindent The results, calculated in Equation \ref{equation_computing_calculation} to \ref{equation_load_calculation} can be summarized as follows:\\ \\ 
+With the optimal filter length of 45 taps and an update rate of the filter coefficients every cycle, the \ac{ANR} algorithm is able to achieve a \ac{SNR}-Gain of about 11.54 dB, averaged over different signal/noise combinatons. Under this circumstances, the computational load of the \ac{DSP} core amounts about 45\%, which means that 55\% of the time, which a new sample takes to arrive, it can be halted, and therefore, the overall power consumption can be reduced.\\ \\
+The initial signal/noise combination of a male speaker disturbed by a breathing noise, which is used for the verification of the \ac{DSP} implementation, delivers with 45 filter coefficients an \ac{SNR}-Gain of about 9.44 dB, which will be again used as a benchmark for the coming evaluations.
+\subsubsection{Reduced-update implementation}
+The most straight-forward method to further reduce the computing effort for the \ac{DSP} core is to reduce the update frequency of the filter coeffcients. This means, that for every sample, the new filter coefficients are calculated, but not written to the into the Filter Line, meaning that the filter, calculated for the previous sample, is applied to the actual sample. Depending on the acoustic situation, the savings in computing power will most likely lead to a degredation of the noise reduction quality, depending if the current situation is highly dynamic (and therefore would require a frequent update of the filter coefficients) or is rather static. Changing the update frequency, changes the denominator in Equation \ref{equation_c_5} and therefore in Equation \ref{equation_computing_final}.\\ \\
+As already mentioned, the reduction of the update rate is evaluated for the signal/noise combination of a male speaker disturbed by a breathing noise. Therefore the \ac{SNR}-Gain of 9.44 dB represents 100\% achievable noise reduction with a maximum of 357 cycles.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_snr_reduced_update.png}
+    \caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}
+    \label{fig:fig_snr_reduced_update.png}
+\end{figure}
+\noindent Figure \ref{fig:fig_snr_reduced_update.png} descriptively illustrates the trend of the \ac{SNR}-Gain, the executed cycles per sample and the \ac{DSP} load compared to the full-update algorithm. Contrary to the executed cycles per sample and the load of the processor, the \ac{SNR}-Gain does not behave linear over the course of reducing the update frequency. This behavior allows us, to determinte the update rate, where the benevolent ratio of \ac{SNR}-Gain in regard to \ac{DSP} load can be expected.\\ \\
+The maximum offset bewteen the two graphs can be cound found at an updat rate of 0.33, meaning, that an update of the filter coefficients is only conducted every third sample. Updating Equation \ref{equation_computing_calculation} and \ref{equation_load_calculation} therefore delivers:
+\begin{equation}
+\label{equation_computing_calculation}
+ C_{total} = 45 + \frac{6*45+8}{0.33} + 34 = 171 \text{ cycles}
+\end{equation}
+\begin{equation}
+\label{equation_load_calculation}
+    Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{171 \text{ cycles}}{800 \text{ cycles}} = 21.4 \%
+\end{equation}
+The interpreation of this results leads to the coclusion, that the most cost-effective way to reduce the load of the \ac{DSP} would be to reduce the update rate of the filter coefficients to 0.33. This action nearly halfs the processor load, while only reducing the \ac{SNR}-Gain by rougly a third to 6.06 dB. The next step will be to determine the possibilites of a dynamic reduction of the update frequency to further improve the cost-value ratio of our implemenation.
+\subsection{Evaluation of the computational load for error driven implementation}
+The error-driven implemenation approach focuses on an error metric, over which the decision for an coefficient update is made. 
+\subsection{Summary of the performance evaluation}

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+\section{Conclusion and outlook}

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+        <mxCell id="lyxZcRr64k90961b_5eU-4" parent="1" style="text;whiteSpace=wrap;html=1;" value="&lt;div style=&quot;text-align: center;&quot;&gt;&lt;span style=&quot;background-color: transparent; color: light-dark(rgb(0, 0, 0), rgb(255, 255, 255));&quot;&gt;add&lt;/span&gt;&lt;/div&gt;" vertex="1">
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+        <mxCell id="lyxZcRr64k90961b_5eU-13" parent="1" style="text;whiteSpace=wrap;html=1;" value="&lt;div style=&quot;text-align: center;&quot;&gt;&lt;span style=&quot;background-color: transparent; color: light-dark(rgb(0, 0, 0), rgb(255, 255, 255));&quot;&gt;add&lt;/span&gt;&lt;/div&gt;" vertex="1">
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+        <mxCell id="lyxZcRr64k90961b_5eU-14" parent="1" style="text;whiteSpace=wrap;html=1;" value="&lt;div style=&quot;text-align: center;&quot;&gt;&lt;span style=&quot;background-color: transparent; color: light-dark(rgb(0, 0, 0), rgb(255, 255, 255));&quot;&gt;add&lt;/span&gt;&lt;/div&gt;" vertex="1">
+          <mxGeometry height="27" width="30" x="1003.75" y="599" as="geometry" />
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+        <mxCell id="lyxZcRr64k90961b_5eU-15" parent="1" style="text;whiteSpace=wrap;html=1;" value="&lt;div style=&quot;text-align: center;&quot;&gt;&lt;span style=&quot;background-color: transparent; color: light-dark(rgb(0, 0, 0), rgb(255, 255, 255));&quot;&gt;add&lt;/span&gt;&lt;/div&gt;" vertex="1">
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+        <mxCell id="lyxZcRr64k90961b_5eU-16" parent="1" style="text;whiteSpace=wrap;html=1;" value="&lt;div style=&quot;text-align: center;&quot;&gt;&lt;span style=&quot;background-color: transparent; color: light-dark(rgb(0, 0, 0), rgb(255, 255, 255));&quot;&gt;add&lt;/span&gt;&lt;/div&gt;" vertex="1">
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main.bbl-SAVE-ERROR

@@ -0,0 +1,164 @@
+% $ biblatex auxiliary file $
+% $ biblatex bbl format version 3.2 $
+% Do not modify the above lines!
+%
+% This is an auxiliary file used by the 'biblatex' package.
+% This file may safely be deleted. It will be recreated by
+% biber as required.
+%
+\begingroup
+\makeatletter
+\@ifundefined{ver@biblatex.sty}
+  {\@latex@error
+     {Missing 'biblatex' package}
+     {The bibliography requires the 'biblatex' package.}
+      \aftergroup\endinput}
+  {}
+\endgroup
+
+
+\refsection{0}
+  \datalist[entry]{none/global//global/global}
+    \entry{source_synchrony}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=ffb45f0281705211553241b831eeaf22}{%
+           family={MED-EL},
+           familyi={M\bibinithyphendelim E\bibinitperiod}}}%
+      }
+      \strng{namehash}{ffb45f0281705211553241b831eeaf22}
+      \strng{fullhash}{ffb45f0281705211553241b831eeaf22}
+      \strng{bibnamehash}{ffb45f0281705211553241b831eeaf22}
+      \strng{authorbibnamehash}{ffb45f0281705211553241b831eeaf22}
+      \strng{authornamehash}{ffb45f0281705211553241b831eeaf22}
+      \strng{authorfullhash}{ffb45f0281705211553241b831eeaf22}
+      \field{extraname}{1}
+      \field{sortinit}{1}
+      \field{sortinithash}{4f6aaa89bab872aa0999fec09ff8e98a}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{\url{https://www.medel.com/de/hearing-solutions/cochlear-implants}}
+      \field{note}{Accessed on 20.01.2026}
+      \field{title}{MED-EL Synchrony Cochlear Implant with a Sonnet 3 Audio Processor}
+      \field{year}{2026}
+    \endentry
+    \entry{source_electrode}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=ffb45f0281705211553241b831eeaf22}{%
+           family={MED-EL},
+           familyi={M\bibinithyphendelim E\bibinitperiod}}}%
+      }
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+      \strng{authorbibnamehash}{ffb45f0281705211553241b831eeaf22}
+      \strng{authornamehash}{ffb45f0281705211553241b831eeaf22}
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+      \field{sortinithash}{ad6fe7482ffbd7b9f99c9e8b5dccd3d7}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{\url{https://blog.medel.pro/de/chirurgie/relevanz-der-ci-elektrode/}}
+      \field{note}{Accessed on 30.01.2026}
+      \field{title}{Visualization of a MED-EL electrode inserted into a human cochlear}
+      \field{year}{2026}
+    \endentry
+    \entry{source_dsp_ch1}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=26ad37f8f6f878dc28acadb561885bff}{%
+           family={Li\bibnamedelima Tan},
+           familyi={L\bibinitperiod\bibinitdelim T\bibinitperiod},
+           given={Jean\bibnamedelima Jiang},
+           giveni={J\bibinitperiod\bibinitdelim J\bibinitperiod}}}%
+      }
+      \strng{namehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{fullhash}{26ad37f8f6f878dc28acadb561885bff}
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+      \strng{authorbibnamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authornamehash}{26ad37f8f6f878dc28acadb561885bff}
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+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{Elsevier Inc.}
+      \field{note}{Chapter 1}
+      \field{title}{Digital Signal Processing Fundamentals and Applications 3rd Ed}
+      \field{year}{2013}
+    \endentry
+    \entry{source_dsp_ch2}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=26ad37f8f6f878dc28acadb561885bff}{%
+           family={Li\bibnamedelima Tan},
+           familyi={L\bibinitperiod\bibinitdelim T\bibinitperiod},
+           given={Jean\bibnamedelima Jiang},
+           giveni={J\bibinitperiod\bibinitdelim J\bibinitperiod}}}%
+      }
+      \strng{namehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{fullhash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{bibnamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authorbibnamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authornamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authorfullhash}{26ad37f8f6f878dc28acadb561885bff}
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+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{Elsevier Inc.}
+      \field{note}{Chapter 2}
+      \field{title}{Digital Signal Processing Fundamentals and Applications 3rd Ed}
+      \field{year}{2013}
+    \endentry
+    \entry{source_patent}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=93a5470d20a141eea1a1f94678d4a447}{%
+           family={Fogel},
+           familyi={F\bibinitperiod},
+           given={Lawrence\bibnamedelima J.},
+           giveni={L\bibinitperiod\bibinitdelim J\bibinitperiod}}}%
+      }
+      \strng{namehash}{93a5470d20a141eea1a1f94678d4a447}
+      \strng{fullhash}{93a5470d20a141eea1a1f94678d4a447}
+      \strng{bibnamehash}{93a5470d20a141eea1a1f94678d4a447}
+      \strng{authorbibnamehash}{93a5470d20a141eea1a1f94678d4a447}
+      \strng{authornamehash}{93a5470d20a141eea1a1f94678d4a447}
+      \strng{authorfullhash}{93a5470d20a141eea1a1f94678d4a447}
+      \field{sortinit}{1}
+      \field{sortinithash}{4f6aaa89bab872aa0999fec09ff8e98a}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{United States Patent Office}
+      \field{note}{Pat. Nr. 2966549}
+      \field{title}{Apparatus for improving intelligence under high ambient noise levels}
+      \field{year}{1960}
+    \endentry
+    \entry{source_dsp_ch9}{misc}{}
+      \name{author}{1}{}{%
+        {{hash=26ad37f8f6f878dc28acadb561885bff}{%
+           family={Li\bibnamedelima Tan},
+           familyi={L\bibinitperiod\bibinitdelim T\bibinitperiod},
+           given={Jean\bibnamedelima Jiang},
+           giveni={J\bibinitperiod\bibinitdelim J\bibinitperiod}}}%
+      }
+      \strng{namehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{fullhash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{bibnamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authorbibnamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authornamehash}{26ad37f8f6f878dc28acadb561885bff}
+      \strng{authorfullhash}{26ad37f8f6f878dc28acadb561885bff}
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+      \field{sortinit}{1}
+      \field{sortinithash}{4f6aaa89bab872aa0999fec09ff8e98a}
+      \field{labelnamesource}{author}
+      \field{labeltitlesource}{title}
+      \field{howpublished}{Elsevier Inc.}
+      \field{note}{Chapter 9}
+      \field{title}{Digital Signal Processing Fundamentals and Applications 3rd Ed}
+      \field{year}{2013}
+    \endentry
+  \enddatalist
+\endrefsection
+\endinput
+

main.tex

@@ -47,7 +47,7 @@ in cochlear implant systems}}\\[-0.5ex]
 \textbf{\Large{Master of Science}}\\
 \bigskip\par
 by \par
-\large{Patrick Hangl, BSc}\\[-1ex]
+\large{Patrick Hangl, B.Sc.}\\[-1ex]
 \large{Matriculation Nr.: q4179749}\\ [-1ex]
 \vspace{0.6cm}
 \end{center}
@@ -73,6 +73,8 @@ abstract
 \include{chapter_02}
 \include{chapter_03}
 \include{chapter_04}
+\include{chapter_05}
+\include{chapter_06}
 \printbibliography
 \listoffigures