Compare commits
3 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Patrick Hangl
|
dd514337d7 | ||
|
Patrick Hangl
|
52e5b87f76 | ||
|
Patrick Hangl
|
66385250bc |
Binary file not shown.
|
After Width: | Height: | Size: 1.0 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 825 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 652 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 633 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 703 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 737 KiB |
+27
-27
@@ -7,10 +7,10 @@
|
||||
\acronymused{ANR}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Low-power system architecture and integration}{42}{}\protected@file@percent }
|
||||
\AC@undonewlabel{acro:SOC}
|
||||
\newlabel{acro:SOC}{{4.1}{42}{}{subsection.4.1}{}}
|
||||
\newlabel{acro:SOC}{{4.1}{42}{}{}{}}
|
||||
\acronymused{SOC}
|
||||
\AC@undonewlabel{acro:ARM}
|
||||
\newlabel{acro:ARM}{{4.1}{42}{}{subsection.4.1}{}}
|
||||
\newlabel{acro:ARM}{{4.1}{42}{}{}{}}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
@@ -22,7 +22,7 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:MAC}
|
||||
\newlabel{acro:MAC}{{4.1.1}{42}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:MAC}{{4.1.1}{42}{}{}{}}
|
||||
\acronymused{MAC}
|
||||
\acronymused{ARM}
|
||||
\acronymused{ANR}
|
||||
@@ -37,10 +37,10 @@
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:DMA}
|
||||
\newlabel{acro:DMA}{{4.1.1}{43}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:DMA}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{DMA}
|
||||
\AC@undonewlabel{acro:PCM}
|
||||
\newlabel{acro:PCM}{{4.1.1}{43}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:PCM}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
@@ -51,7 +51,7 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:ALU}
|
||||
\newlabel{acro:ALU}{{4.1.1}{43}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:ALU}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{ALU}
|
||||
\acronymused{DSP}
|
||||
\acronymused{MAC}
|
||||
@@ -70,7 +70,7 @@
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
\newlabel{fig:fig_dsp_setup.jpg}{{32}{44}{}{figure.32}{}}
|
||||
\newlabel{fig:fig_dsp_setup.jpg}{{32}{44}{}{}{}}
|
||||
\acronymused{ARM}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DMA}
|
||||
@@ -85,7 +85,7 @@
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {33}{\ignorespaces Simplified flowchart of the sample processing between the \ac {ARM} core and the \ac {DSP} core via interrupts and shared memory.}}{45}{}\protected@file@percent }
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_comm.jpg}{{33}{45}{}{figure.33}{}}
|
||||
\newlabel{fig:fig_dsp_comm.jpg}{{33}{45}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}Software architecture and execution flow}{45}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}ARM–DSP communication and data exchange details}{45}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
@@ -121,7 +121,7 @@
|
||||
\acronymused{DMA}
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
\newlabel{fig:fig_dsp_dma.jpg}{{34}{47}{}{figure.34}{}}
|
||||
\newlabel{fig:fig_dsp_dma.jpg}{{34}{47}{}{}{}}
|
||||
\acronymused{DMA}
|
||||
\acronymused{DMA}
|
||||
\acronymused{PCM}
|
||||
@@ -138,10 +138,10 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dps_code_memory}{{4.2.2}{48}{}{lstnumber.-2.13}{}}
|
||||
\newlabel{fig:fig_dps_code_memory}{{4.2.2}{48}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {35}{\ignorespaces Low-level implementation: Memory initialization and mapping}}{48}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {36}{\ignorespaces Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16-bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise addressing is a result of the compiler abstraction.}}{48}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_compiler.jpg}{{36}{48}{}{figure.36}{}}
|
||||
\newlabel{fig:fig_compiler.jpg}{{36}{48}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{48}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{ANR}
|
||||
@@ -151,10 +151,10 @@
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {37}{\ignorespaces Low-level implementation: Main loop and interrupt handling}}{49}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dps_code_mainloop}{{37}{49}{}{figure.37}{}}
|
||||
\newlabel{fig:fig_dps_code_mainloop}{{37}{49}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {38}{\ignorespaces Flow diagram of the code implementation of the main loop and interrupt handling on the \ac {DSP} core.}}{50}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_logic.jpg}{{38}{50}{}{figure.38}{}}
|
||||
\newlabel{fig:fig_dsp_logic.jpg}{{38}{50}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{calculate\_output()-function}{50}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{ANR}
|
||||
@@ -168,11 +168,11 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {39}{\ignorespaces Manual implementation of a max-function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operation.}}{51}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_find_max}{{39}{51}{}{figure.39}{}}
|
||||
\newlabel{fig:fig_dsp_code_find_max}{{39}{51}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Cyclic array iteration}{51}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {40}{\ignorespaces Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute a pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}}{52}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{52}{}{figure.40}{}}
|
||||
\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{52}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Fractional fixed-point arithmetic}{52}{}\protected@file@percent }
|
||||
@@ -196,9 +196,9 @@
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {41}{\ignorespaces Code snippet of the $apply\_fir\_filter$-function, showing the use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. The loop iterates through the filter coefficients and reference noise signal samples, performing two multiplications and two additions in each cycle.}}{54}{}\protected@file@percent }
|
||||
\acronymused{MAC}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{54}{}{figure.41}{}}
|
||||
\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{54}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {42}{\ignorespaces Visualization of the FIR filter calculation in the $apply\_fir\_filter$-function during the 2nd cyclce of a calculation loop. The reference noise signal samples are stored in the sample line, while the filter coefficients are stored in a separate memory section (filter line).}}{54}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{54}{}{figure.42}{}}
|
||||
\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{54}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_output}{55}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_filter\_coefficient}{55}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
@@ -206,20 +206,20 @@
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {43}{\ignorespaces Code snippet of the $update\_filter\_coefficient$-function, again making use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. Additionaly, 32-bit values are loaded and stored as 64-bit values, using two also intrinisc functions, allowing to update two filter coefficients in a single cycle.}}{55}{}\protected@file@percent }
|
||||
\acronymused{MAC}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{55}{}{figure.43}{}}
|
||||
\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{55}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {44}{\ignorespaces Visualization of the coefficient calculation in the $update\_filter\_coefficient$-function during the 2nd cyclce of a calculation loop. The output is multiplied with the step size and the corresponding sample from the sample line, before being added to the current filter coefficient.}}{56}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{56}{}{figure.44}{}}
|
||||
\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{56}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{write\_output}{56}{}\protected@file@percent }
|
||||
\newlabel{equation_computing}{{24}{56}{}{equation.24}{}}
|
||||
\newlabel{equation_c_1}{{25}{56}{}{equation.25}{}}
|
||||
\newlabel{equation_c_2}{{26}{56}{}{equation.26}{}}
|
||||
\newlabel{equation_c_3}{{27}{56}{}{equation.27}{}}
|
||||
\newlabel{equation_c_4}{{28}{56}{}{equation.28}{}}
|
||||
\newlabel{equation_c_5}{{29}{56}{}{equation.29}{}}
|
||||
\newlabel{equation_computing_final}{{31}{57}{}{equation.31}{}}
|
||||
\newlabel{equation_computing}{{24}{56}{}{}{}}
|
||||
\newlabel{equation_c_1}{{25}{56}{}{}{}}
|
||||
\newlabel{equation_c_2}{{26}{56}{}{}{}}
|
||||
\newlabel{equation_c_3}{{27}{56}{}{}{}}
|
||||
\newlabel{equation_c_4}{{28}{56}{}{}{}}
|
||||
\newlabel{equation_c_5}{{29}{56}{}{}{}}
|
||||
\newlabel{equation_computing_final}{{31}{57}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {45}{\ignorespaces Dependence of the total computing effort on the filter length $N$ and update rate $1/U$.}}{57}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_c_total.png}{{45}{57}{}{figure.45}{}}
|
||||
\newlabel{fig:fig_c_total.png}{{45}{57}{}{}{}}
|
||||
\@setckpt{chapter_04}{
|
||||
\setcounter{page}{58}
|
||||
\setcounter{equation}{31}
|
||||
|
||||
+51
-21
@@ -10,15 +10,15 @@
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {46}{\ignorespaces Desired signal, corrupted signal, reference noise signal and filter output of the complex \ac {ANR} use case, simulated on the \ac {DSP}}}{58}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_plot_1_dsp_complex.png}{{46}{58}{}{figure.46}{}}
|
||||
\newlabel{fig:fig_plot_1_dsp_complex.png}{{46}{58}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {47}{\ignorespaces Error signal of the complex \ac {ANR} use case, simulated on the \ac {DSP}}}{59}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_plot_2_dsp_complex.png}{{47}{59}{}{figure.47}{}}
|
||||
\newlabel{fig:fig_plot_2_dsp_complex.png}{{47}{59}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {48}{\ignorespaces Comparison of the high- and low-level simulation output.}}{59}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_high_low_comparison.png}{{48}{59}{}{figure.48}{}}
|
||||
\newlabel{fig:fig_high_low_comparison.png}{{48}{59}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {49}{\ignorespaces Histogram of the error amplitude between the high- and low-level simulation output.}}{60}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_high_low_comparison_hist.png}{{49}{60}{}{figure.49}{}}
|
||||
\newlabel{fig:fig_high_low_comparison_hist.png}{{49}{60}{}{}{}}
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
@@ -32,12 +32,12 @@
|
||||
\acronymused{ANR}
|
||||
\acronymused{CI}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {50}{\ignorespaces Noise signals used to corrupt the desired signal in the computational efficiency evaluation}}{61}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_noise_signals.png}{{50}{61}{}{figure.50}{}}
|
||||
\newlabel{fig:fig_noise_signals.png}{{50}{61}{}{}{}}
|
||||
\acronymused{ANR}
|
||||
\acronymused{SNR}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {51}{\ignorespaces Simulation of the to be expected \ac {SNR}-Gain for different noise signals and filter lengths applied to the desired signal of a male speaker. The applied delay between the signals amounts 2ms. The graphs are smoothed by a third order savigol filter.}}{62}{}\protected@file@percent }
|
||||
\acronymused{SNR}
|
||||
\newlabel{fig:fig_snr_comparison.png}{{51}{62}{}{figure.51}{}}
|
||||
\newlabel{fig:fig_snr_comparison.png}{{51}{62}{}{}{}}
|
||||
\acronymused{SNR}
|
||||
\acronymused{SNR}
|
||||
\acronymused{SNR}
|
||||
@@ -47,39 +47,69 @@
|
||||
\acronymused{ANR}
|
||||
\acronymused{SNR}
|
||||
\acronymused{ANR}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.3}Evaluation of the computational load for fixed implementation}{62}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.3}Evaluation of the computational load for a fixed update implementation}{62}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.1}Full-Update implementation}{62}{}\protected@file@percent }
|
||||
\newlabel{equation_computing_calculation}{{32}{63}{}{equation.32}{}}
|
||||
\newlabel{equation_computing_calculation_full_update}{{32}{63}{}{}{}}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\newlabel{equation_cycle_budget}{{33}{63}{}{equation.33}{}}
|
||||
\newlabel{equation_cycle_budget}{{33}{63}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\newlabel{equation_load_calculation}{{34}{63}{}{equation.34}{}}
|
||||
\newlabel{equation_load_calculation_full_update}{{34}{63}{}{}{}}
|
||||
\acronymused{ANR}
|
||||
\acronymused{SNR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.2}Reduced-update implementation}{63}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.2}Reduced-update implementation for the benchmark case}{63}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {52}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}}{64}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_snr_reduced_update.png}{{52}{64}{}{figure.52}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {52}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm for the benchmark case. The baseline of 100\% is the full update implementation. The marked dots represent the results of the simulation for an explicit setup.}}{64}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_snr_update_rate.png}{{52}{64}{}{}{}}
|
||||
\acronymused{SNR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\acronymused{SNR}
|
||||
\acronymused{DSP}
|
||||
\newlabel{equation_computing_calculation}{{35}{64}{}{equation.35}{}}
|
||||
\newlabel{equation_load_calculation}{{36}{64}{}{equation.36}{}}
|
||||
\newlabel{equation_computing_calculation_reduced_update_1}{{35}{64}{}{}{}}
|
||||
\newlabel{equation_load_calculation_reduced_update_1}{{36}{64}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.4}Evaluation of the computational load for error driven implementation}{64}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.5}Summary of the performance evaluation}{65}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.3}Reduced-update implementation for multiple noise signals}{64}{}\protected@file@percent }
|
||||
\acronymused{SNR}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {53}{\ignorespaces Performance gain (distance between relative SNR-Gain and needed relative cycles/sample) in relation to the update rate of the ANR algorithm for different noise signals.}}{65}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_gain_update_rate.png}{{53}{65}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {54}{\ignorespaces Absolute \ac {DSP} load in relation to the update rate of the ANR algorithm for different noise signals.}}{65}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_load_update_rate.png}{{54}{65}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\newlabel{equation_computing_calculation_reduced_update_2}{{37}{65}{}{}{}}
|
||||
\newlabel{equation_load_calculation_reduced_update_2}{{38}{66}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.4}Computational load for reduced-update implementation}{66}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.4}Evaluation of the computational load for an error driven implementation}{66}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.4.1}Error threshold implementation for the benchmark case}{66}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {55}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}}{67}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_snr_error_threshold.png.png}{{55}{67}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.4.2}Error threshold implementaion for multiple noise signals}{67}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {56}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}}{68}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_gain_error_threshold.png.png}{{56}{68}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {57}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}}{68}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_load_error_threshold.png.png}{{57}{68}{}{}{}}
|
||||
\acronymused{SNR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{SNR}
|
||||
\newlabel{equation_computing_calculation_error_threshold}{{39}{69}{}{}{}}
|
||||
\newlabel{equation_load_calculation_error_threshold}{{40}{69}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {5.4.3}Computational load for error threshold implementation}{69}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {5.5}Summary of the performance evaluation}{69}{}\protected@file@percent }
|
||||
\acronymused{SNR}
|
||||
\@setckpt{chapter_05}{
|
||||
\setcounter{page}{66}
|
||||
\setcounter{equation}{36}
|
||||
\setcounter{page}{70}
|
||||
\setcounter{equation}{40}
|
||||
\setcounter{enumi}{0}
|
||||
\setcounter{enumii}{0}
|
||||
\setcounter{enumiii}{0}
|
||||
@@ -92,7 +122,7 @@
|
||||
\setcounter{subsubsection}{0}
|
||||
\setcounter{paragraph}{0}
|
||||
\setcounter{subparagraph}{0}
|
||||
\setcounter{figure}{52}
|
||||
\setcounter{figure}{57}
|
||||
\setcounter{table}{0}
|
||||
\setcounter{float@type}{16}
|
||||
\setcounter{tabx@nest}{0}
|
||||
@@ -213,7 +243,7 @@
|
||||
\setcounter{lstnumber}{15}
|
||||
\setcounter{FancyVerbLine}{0}
|
||||
\setcounter{linenumber}{1}
|
||||
\setcounter{LN@truepage}{65}
|
||||
\setcounter{LN@truepage}{69}
|
||||
\setcounter{FancyVerbWriteLine}{0}
|
||||
\setcounter{FancyVerbBufferLine}{0}
|
||||
\setcounter{FV@TrueTabGroupLevel}{0}
|
||||
|
||||
+81
-22
@@ -49,13 +49,13 @@ The vizualization of the noise signals is shown in Figure \ref{fig:fig_noise_sig
|
||||
\caption{Simulation of the to be expected \ac{SNR}-Gain for different noise signals and filter lengths applied to the desired signal of a male speaker. The applied delay between the signals amounts 2ms. The graphs are smoothed by a third order savigol filter.}
|
||||
\label{fig:fig_snr_comparison.png}
|
||||
\end{figure}
|
||||
\noindent Figure \ref{fig:fig_snr_comparison.png} shows the expected \ac{SNR}-Gain for the different noise signals and filter lengths. The results show, that a minimum filter length of about 32 taps is required, before (in any case) a significant rise in the \ac{SNR}-Gain can be observed - this is highly contrary to the synchrone intermediate high level simulation, where a filter length of only 16 taps provided sufficent noise reduction. This circumstance can be explained by the fact, that the corruption noise signal is now delayed to the reference noise signal, meaning, that the filter needs a certain length before it can be sufficently adapted. The results also show, that the \ac{SNR}-Gain is different for the different noise signals, indicating, that the noise signals have different characteristics, like the number of peaks, their frequency spectrum and their amplitude.\\ \\
|
||||
The mean \ac{SNR}-Gain of the different noise signals, also shown in Figure \ref{fig:fig_snr_comparison.png}, signals, that after reaching 95\% of the maximum \ac{SNR}-Gain, the \ac{SNR}-Gain increase is slowing down. This threshold is reached at a filter length of 45 taps. This means, that a filter length of 45 taps represents an optimal solution for a statisfying performance of the \ac{ANR} algorithm, while a further increase of the filter length does not lead to a significant increase of the \ac{SNR}-Gain in this setup. This is an important finding, as it allows optimizing the computational efficiency of the \ac{ANR} algorithm by choosing an appropriate filter length.
|
||||
\subsection{Evaluation of the computational load for fixed implementation}
|
||||
\noindent Figure \ref{fig:fig_snr_comparison.png} shows the expected \ac{SNR}-Gain for the different noise signals and filter lengths. The results shows, that a minimum filter length of about 32 taps is required, before (in any case) a significant rise in the \ac{SNR}-Gain can be observed - this is highly contrary to the synchrone intermediate high level simulation, where a filter length of only 16 taps provided sufficent noise reduction. This circumstance can be explained by the fact, that the corruption noise signal is now delayed to the reference noise signal, meaning, that the filter needs a certain length before it can be sufficently adapted. The results also show, that the \ac{SNR}-Gain is different for the different noise signals, indicating, that the noise signals have different characteristics, like the number of peaks, their frequency spectrum an their amplitude.\\ \\
|
||||
The mean \ac{SNR}-Gain of the different noise signals, also shown in Figure \ref{fig:fig_snr_comparison.png}, signals, that after reaching 95\% of the maximum \ac{SNR}-Gain, the \ac{SNR}-Gain increase is slowing down. This threshold is reached at a filter length of 45 taps. This means, that a filter length of 45 taps represents an optimal solution for a statisfying performance of the \ac{ANR} algorithm, while a further increase of the filter length does not lead to a significant increase of the \ac{SNR}-Gain in this setup. This is an important finding, as it allows to optimize the computational efficiency of the \ac{ANR} algorithm by choosing an appropriate filter length.
|
||||
\subsection{Evaluation of the computational load for a fixed update implementation}
|
||||
\subsubsection{Full-Update implementation}
|
||||
\noindent Equation \ref{equation_computing_final} can now be utilized to calculate the needed cycles for the calculation of one sample of the filter output, using a filter length of 45 taps and an update of the filter coefficients every cycle. The needed cycles are calculated as follows:
|
||||
\begin{equation}
|
||||
\label{equation_computing_calculation}
|
||||
\label{equation_computing_calculation_full_update}
|
||||
C_{total} = 45 + (6*45+8)*1 + 34 = 357 \text{ cycles}
|
||||
\end{equation}
|
||||
As already mentioned in the previous chapters, the sampling rate of the audio data provided to the \ac{PCM} interface amounts 20 kHz. The prefered clock frequency of the \ac{DSP} is chosen as 16 MHz, which means, that the \ac{DSP} core has cycle budget of
|
||||
@@ -65,32 +65,91 @@ As already mentioned in the previous chapters, the sampling rate of the audio da
|
||||
\end{equation}
|
||||
\noindent for one sample. With these two values, the load of the \ac{DSP} core can be calculated as follows:
|
||||
\begin{equation}
|
||||
\label{equation_load_calculation}
|
||||
\label{equation_load_calculation_full_update}
|
||||
Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{357 \text{ cycles}}{800 \text{ cycles}} = 44.6 \%
|
||||
\end{equation}
|
||||
\noindent The results, calculated in Equation \ref{equation_computing_calculation} to \ref{equation_load_calculation} can be summarized as follows:\\ \\
|
||||
With the optimal filter length of 45 taps and an update rate of the filter coefficients every cycle, the \ac{ANR} algorithm is able to achieve a \ac{SNR}-Gain of about 11.54 dB, averaged over different signal/noise combinations. Under these circumstances, the computational load of the \ac{DSP} core amounts about 45\%, which means that 55\% of the time, which a new sample takes to arrive, it can be halted, and therefore, the overall power consumption can be reduced.\\ \\
|
||||
The initial signal/noise combination of a male speaker disturbed by a breathing noise, which is used for the verification of the \ac{DSP} implementation, delivers with 45 filter coefficients a \ac{SNR}-Gain of about 9.47 dB, which will be again used as a benchmark for the coming evaluations.
|
||||
\subsubsection{Reduced-update implementation}
|
||||
The most straight-forward method to further reduce the computing effort for the \ac{DSP} core is to reduce the update frequency of the filter coeffcients. This means, that for every sample, the new filter coefficients are calculated, but not written to the into the Filter Line, meaning that the filter, calculated for the previous sample, is applied to the actual sample. Depending on the acoustic situation, the savings in computing power will most likely lead to a degredation of the noise reduction quality, depending on if the current situation is highly dynamic (and therefore would require a frequent update of the filter coefficients) or is rather static. Changing the update frequency, changes the denominator in Equation \ref{equation_c_5} and therefore in Equation \ref{equation_computing_final}.\\ \\
|
||||
As already mentioned, the reduction of the update rate is evaluated for the signal/noise combination of a male speaker disturbed by a breathing noise. Therefore, the \ac{SNR}-Gain of 9.47 dB with 45 filter coefficients represent 100\% achievable noise reduction with a maximum of 357 cycles.
|
||||
\noindent The results, calculated in Equation \ref{equation_computing_calculation_full_update} to \ref{equation_load_calculation_full_update} can also be recapped as follows:\\ \\
|
||||
With the optimal filter length of 45 taps and an update rate of the filter coefficients every cycle, the \ac{ANR} algorithm is able to achieve a \ac{SNR}-Gain of about 11.54 dB, averaged over different signal/noise combinations. Under this circumstances, the computational load of the \ac{DSP} core amounts about 45\%, which means that 55\% of the time, which a new sample takes to arrive, it can be halted, and therefore, the overall power consumption can be reduced.\\ \\
|
||||
The initial signal/noise combination of a male speaker disturbed by a breathing noise, which is used for the verification of the \ac{DSP} implementation, shall serve as a benchmark for the coming evaluations. With 45 filter coefficients it delivers an \ac{SNR}-Gain of about 9.47 dB.
|
||||
\subsubsection{Reduced-update implementation for the benchmark case}
|
||||
The most straight-forward method to further reduce the computing effort for the \ac{DSP} core is to reduce the update frequency of the filter coeffcients. For every sample, the new filter coefficients are calculated, but not written to the into the Filter Line - this means, that the filter, calculated for the previous sample, is applied to the actual sample. Depending on the acoustic situation, the savings in computing power will most likely lead to a degredation of the noise reduction quality, depending if the current situation is highly dynamic (and therefore would require a frequent update of the filter coefficients) or is rather static. Changing the update frequency, changes the denominator in Equation \ref{equation_c_5} and therefore in Equation \ref{equation_computing_final}.\\ \\
|
||||
As already mentioned, the reduction of the update rate is initially evaluated for the benchmark case (male speaker disturbed by a breathing noise) and then checked for general validity. Therefore the \ac{SNR}-Gain of 9.47 dB with 45 filter coefficients represent 100\% achievable noise reduction with a maximum of 357 cycles (also 100\%) in the following figure.
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_snr_reduced_update.png}
|
||||
\caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}
|
||||
\label{fig:fig_snr_reduced_update.png}
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_snr_update_rate.png}
|
||||
\caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm for the benchmark case. The baseline of 100\% is the full update implementation. The marked dots represent the results of the simulation for an explicit setup.}
|
||||
\label{fig:fig_snr_update_rate.png}
|
||||
\end{figure}
|
||||
\noindent Figure \ref{fig:fig_snr_reduced_update.png} descriptively illustrates the trend of the \ac{SNR}-Gain, the executed cycles per sample and the \ac{DSP} load compared to the full-update algorithm. Contrary to the executed cycles per sample and the load of the processor, the \ac{SNR}-Gain does not behave linear over the course of reducing the update frequency. This behavior allows us, to determinte the update rate, where the benevolent ratio of \ac{SNR}-Gain in regard to \ac{DSP} load can be expected.\\ \\
|
||||
The maximum offset bewteen the two graphs can be cound found at an updat rate of 0.39, meaning, that an update of the filter coefficients is only conducted in roughly 2 out of 5 samples. Updating Equation \ref{equation_computing_calculation} and \ref{equation_load_calculation} therefore delivers:
|
||||
|
||||
\noindent Figure \ref{fig:fig_snr_update_rate.png} descriptively illustrates the trend of the \ac{SNR}-Gain, the executed cycles per sample and the \ac{DSP} load compared to the full-update variant of the benchmark case. Contrary to the executed cycles per sample and the load of the processor, the \ac{SNR}-Gain does not behave linear over the course of reducing the update frequency. This behavior allows us to determinte the update rate, where the most benevolent ratio of \ac{SNR}-Gain in regard to \ac{DSP} load can be expected.\\ \\
|
||||
The maximum offset bewteen the two graphs can be cound found at an updat rate of 0.39, meaning, that an update of the filter coefficients is only conducted in roughly 2 out of 5 samples. Updating Equation \ref{equation_computing_calculation_full_update} and \ref{equation_load_calculation_full_update} therefore delivers:
|
||||
\begin{equation}
|
||||
\label{equation_computing_calculation}
|
||||
\label{equation_computing_calculation_reduced_update_1}
|
||||
C_{total} = 45 + (6*45+8)*0.39 + 34 = 188 \text{ cycles}
|
||||
\end{equation}
|
||||
\begin{equation}
|
||||
\label{equation_load_calculation}
|
||||
\label{equation_load_calculation_reduced_update_1}
|
||||
Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{188 \text{ cycles}}{800 \text{ cycles}} = 23.5 \%
|
||||
\end{equation}
|
||||
The interpreation of these results leads to the coclusion, that the most cost-effective way to reduce the load of the \ac{DSP} would be to reduce the update rate of the filter coefficients to 0.39. This action nearly halfs the processor load, while only reducing the \ac{SNR}-Gain by rougly 31 \% to 6.40 dB. The next step will be to determine the possibilites of a dynamic reduction of the update frequency to further improve the cost-value ratio of our implemenation.
|
||||
\subsection{Evaluation of the computational load for error driven implementation}
|
||||
The error-driven implemenation approach focuses on an error metric, over which the decision for a coefficient update is made.
|
||||
\subsection{Summary of the performance evaluation}
|
||||
The interpretation of this results leads to the conclusion, that the most cost-effective way to reduce the load of the \ac{DSP} would be to reduce the update rate of the filter coefficients to 0.39. In the case of the benchmark signal/noise combination, this action nearly halfs the processor load from 44.6\% to 23.5\%, while only reducing the \ac{SNR}-Gain by rougly 31 \% from 9.47 dB to 6.40 dB. In the next step, the same analysis will be applied on all introduced noise signal, to get an idea of the general validity of the mad eobservation.
|
||||
\subsubsection{Reduced-update implementation for multiple noise signals}
|
||||
Now the same evaluation as in the previous subchapter is conducted for the five introduced noise signals, with the difference, that now on the y-axis the performance gain (the distance between relative SNR-Gain and needed relative cycles/sample) instead of the \ac{SNR}-Gain is plotted.
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_gain_update_rate.png}
|
||||
\caption{Performance gain (distance between relative SNR-Gain and needed relative cycles/sample) in relation to the update rate of the ANR algorithm for different noise signals.}
|
||||
\label{fig:fig_gain_update_rate.png}
|
||||
\end{figure}
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_load_update_rate.png}
|
||||
\caption{Absolute \ac{DSP} load in relation to the update rate of the ANR algorithm for different noise signals.}
|
||||
\label{fig:fig_load_update_rate.png}
|
||||
\end{figure}
|
||||
\noindent Figure \ref{fig:fig_gain_update_rate.png} shows the performance gain for the five different scenarios. The mean performance gain for all scenarious now wandered to an update rate of 0.32. Figure \ref{fig:fig_load_update_rate.png} shows the load of the \ac{DSP} core for the different update rates, which is the same for all scenarios, as it is only dependent on the update rate itself.
|
||||
\begin{equation}
|
||||
\label{equation_computing_calculation_reduced_update_2}
|
||||
C_{total} = 45 + (6*45+8)*0.32 + 34 = 168 \text{ cycles}
|
||||
\end{equation}
|
||||
\begin{equation}
|
||||
\label{equation_load_calculation_reduced_update_2}
|
||||
Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{188 \text{ cycles}}{800 \text{ cycles}} = 20.8 \%
|
||||
\end{equation}
|
||||
Equation \ref{equation_computing_calculation_reduced_update_2} and \ref{equation_load_calculation_reduced_update_2} confirm, that for an update rate of 0.32, a reduction of the \ac{DSP} load to 20.8\% can be achieved, correlating with a performance gain of 24.9\%. This means, that for all viewed scenarios, an update rate of 0.32 represents the best cost-value ratio, for reducing the load while geting the best possible noise reduction. The relative performance for all scenarios result in a mean \ac{SNR}-Gain reduction of XX\% from 11.54 dB to XX.XX dB, while the load of the \ac{DSP} core is reduced by about 53.4\% from 44.6\% to 20.8\%.
|
||||
\subsubsection{Computational load for reduced-update implementation}
|
||||
\subsection{Evaluation of the computational load for an error driven implementation}
|
||||
\subsubsection{Error threshold implementation for the benchmark case}
|
||||
In contrary to the fixed update implementation of the previous chapter, the error-driven implementation is a more sophisticated approach, which focuses on an error metric, over which the decision for an coefficient update is made. The idea is, that in a more static acoustic situation, the filter coefficients do not need to be updated as frequently as in a more dynamic situation, where the characteristics of the noise signal are changing more rapidly. As the fixed update implementation is not able to detect such changes, the reduction in update frequency is applied in a static way, which means, that there are situations were it is beneficial and situations where it is not. The error-driven implementation, on the other hand, is able to detect such changes and therefore can adapt the update frequency accordingly. Therefore, the error-driven implementation is expected to deliver a better cost-value ratio than the fixed update implementation. !!!It has to be taken into the mind, that this more complex approach also requires more computing power for the decision making, which affects the overall load of the \ac{DSP} core.!!!
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_snr_error_threshold.png}
|
||||
\caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}
|
||||
\label{fig:fig_snr_error_threshold.png.png}
|
||||
\end{figure}
|
||||
\subsubsection{Error threshold implementaion for multiple noise signals}
|
||||
The first approach for the error-driven implementation is to use a fixed error threshold. This means, that if the error signal remains below an, in advance set, certain threshold, the filter coefficients remain unchanged and are not updated. If the error signal exceeds the threshold, the filter coefficients are updated as in the full-update implementation. \\ \\ The crucial aspect of this approach, is the right choise of the error threshold, which is expected to be highly dependent on the acoustic situation. To get an idea of a beneficial error threshold, different values are evaluated for the already used signal/noise benchmark of a male speaker disturbed by a breathing noise. The reduction in computational load must now be calculated for the whole audio track by the percentage of samples, where the error signal exceeds the threshold. This means in detail, that if for a certain error threshold, 50000 of 200000 samples exceed said threshold, the update rate of the filter coefficients amounts 0.25, which means that the filter coefficients are only updated in 25\% of the samples. The result can therefore be expressed in the same way as for the fixed update implementation, where the update rate is directly calculated for one sample.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_gain_error_threshold.png}
|
||||
\caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}
|
||||
\label{fig:fig_gain_error_threshold.png.png}
|
||||
\end{figure}
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=1.0\linewidth]{Bilder/fig_load_error_threshold.png}
|
||||
\caption{Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the fixed error threshold. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}
|
||||
\label{fig:fig_load_error_threshold.png.png}
|
||||
\end{figure}
|
||||
\noindent Our benchmark track is evaluated for error tresholds ranging from 0 to 0.5. The results, represented in Figure \ref{fig:fig_snr_error_threshold.png.png}, show for small thresholds, especially smaller than 0.1, a highly beneficial behavior can be anticipated, where the \ac{SNR}-Gain is only slightly reduced, while the load of the \ac{DSP} core is significantly reduced. The maximum offset between the two graphs can be found at an error threshold of 0.02 - at this point the \ac{SNR}-Gain is reduced by only 8.9\% to 8.63 dB, while the coefficient adaption is only conducted in ~81400 of 200000 samples, which equivalents an update rate of about 41\%.
|
||||
\begin{equation}
|
||||
\label{equation_computing_calculation_error_threshold}
|
||||
C_{total} = 45 + (6*45+8)*0.407 + 34 = 192 \text{ cycles}
|
||||
\end{equation}
|
||||
\begin{equation}
|
||||
\label{equation_load_calculation_error_threshold}
|
||||
Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{192 \text{ cycles}}{800 \text{ cycles}} = 24.0 \%
|
||||
\end{equation}
|
||||
\subsubsection{Computational load for error threshold implementation}
|
||||
\subsection{Summary of the performance evaluation}
|
||||
The results of the fixed error threshold implementation shows, that at it´s optimum setting, about the same reduction in needed cycles/sample than in the reduced updated implemenation can be achieved (188 vs 192 cycles), while the \ac{SNR}-Gain is reduced by only 8.9\% compared to 31\% for the reduced update implementation. This means, that the fixed error threshold implementation delivers a far better cost-value ratio than the fixed update implementation, while still being a rather simple approach.
|
||||
+5
-5
@@ -1,8 +1,8 @@
|
||||
\relax
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {6}Conclusion and outlook}{66}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {6}Conclusion and outlook}{70}{}\protected@file@percent }
|
||||
\@setckpt{chapter_06}{
|
||||
\setcounter{page}{67}
|
||||
\setcounter{equation}{36}
|
||||
\setcounter{page}{71}
|
||||
\setcounter{equation}{40}
|
||||
\setcounter{enumi}{0}
|
||||
\setcounter{enumii}{0}
|
||||
\setcounter{enumiii}{0}
|
||||
@@ -15,7 +15,7 @@
|
||||
\setcounter{subsubsection}{0}
|
||||
\setcounter{paragraph}{0}
|
||||
\setcounter{subparagraph}{0}
|
||||
\setcounter{figure}{52}
|
||||
\setcounter{figure}{57}
|
||||
\setcounter{table}{0}
|
||||
\setcounter{float@type}{16}
|
||||
\setcounter{tabx@nest}{0}
|
||||
@@ -136,7 +136,7 @@
|
||||
\setcounter{lstnumber}{15}
|
||||
\setcounter{FancyVerbLine}{0}
|
||||
\setcounter{linenumber}{1}
|
||||
\setcounter{LN@truepage}{66}
|
||||
\setcounter{LN@truepage}{70}
|
||||
\setcounter{FancyVerbWriteLine}{0}
|
||||
\setcounter{FancyVerbBufferLine}{0}
|
||||
\setcounter{FV@TrueTabGroupLevel}{0}
|
||||
|
||||
Reference in New Issue
Block a user