From ad0e8000afc1a696446d5e646b10336186270698 Mon Sep 17 00:00:00 2001
From: Patrick Hangl <patrick.hangl@medel.com>
Date: Thu, 15 Jan 2026 15:25:41 +0100
Subject: [PATCH] 4.2

---
 Bilder/fig_compiler.jpg     | Bin 0 -> 34210 bytes
 Bilder/fig_dsp_logic.jpg    | Bin 0 -> 80801 bytes
 chapter_04.aux              |  33 ++---
 chapter_04.tex              |  49 +++++---
 drawio/fig_dsp_logic.drawio | 235 ++++++++++++++++++++++++++++++++++++
 5 files changed, 284 insertions(+), 33 deletions(-)
 create mode 100644 Bilder/fig_compiler.jpg
 create mode 100644 Bilder/fig_dsp_logic.jpg
 create mode 100644 drawio/fig_dsp_logic.drawio

diff --git a/Bilder/fig_compiler.jpg b/Bilder/fig_compiler.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..f00432c78ee6a027664948e5900117da2bb9fc95
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diff --git a/chapter_04.aux b/chapter_04.aux
index 956bcee..5972c78 100644
--- a/chapter_04.aux
+++ b/chapter_04.aux
@@ -3,7 +3,6 @@
 \acronymused{ANR}
 \acronymused{CI}
 \acronymused{ANR}
-\acronymused{DSP}
 \acronymused{ANR}
 \acronymused{ANR}
 \@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Description of the low-power DSP and its environment}{40}{}\protected@file@percent }
@@ -45,8 +44,6 @@
 \acronymused{PCM}
 \acronymused{DSP}
 \acronymused{PCM}
-\acronymused{ARM}
-\acronymused{DSP}
 \acronymused{DSP}
 \acronymused{DSP}
 \acronymused{DSP}
@@ -60,7 +57,7 @@
 \acronymused{MAC}
 \acronymused{ALU}
 \acronymused{MAC}
-\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Communication between the ARM core and the DSP}{41}{}\protected@file@percent }
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Communication between the ARM core and the DSP core}{41}{}\protected@file@percent }
 \acronymused{CI}
 \acronymused{ARM}
 \acronymused{DSP}
@@ -99,9 +96,9 @@
 \acronymused{DMA}
 \acronymused{ARM}
 \acronymused{DSP}
-\acronymused{ARM}
 \acronymused{DSP}
 \acronymused{ARM}
+\acronymused{ARM}
 \acronymused{DMA}
 \acronymused{PCM}
 \acronymused{ARM}
@@ -109,6 +106,7 @@
 \acronymused{DSP}
 \acronymused{ARM}
 \acronymused{DSP}
+\acronymused{ARM}
 \acronymused{ANR}
 \acronymused{DSP}
 \acronymused{ARM}
@@ -117,7 +115,6 @@
 \acronymused{PCM}
 \acronymused{ARM}
 \acronymused{DSP}
-\acronymused{DMA}
 \@writefile{lof}{\contentsline {figure}{\numberline {34}{\ignorespaces Detailed visualization of the \ac {DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggerd, either to the \ac {DSP} core or to the \ac {ARM} core, depending on the input or output direction.}}{45}{}\protected@file@percent }
 \acronymused{DMA}
 \acronymused{DSP}
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-\@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{46}{}\protected@file@percent }
+\@writefile{lof}{\contentsline {figure}{\numberline {36}{\ignorespaces Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16 bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array.}}{47}{}\protected@file@percent }
+\newlabel{fig:fig_compiler.jpg}{{36}{47}{}{}{}}
+\@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{47}{}\protected@file@percent }
 \acronymused{DSP}
 \acronymused{ANR}
 \acronymused{ARM}
 \acronymused{ARM}
 \acronymused{DSP}
 \acronymused{ARM}
+\acronymused{DSP}
 \newlabel{fig:fig_dps_code_mainloop}{{4.2.2}{47}{}{}{}}
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-\@writefile{toc}{\contentsline {subsection}{\numberline {4.4}Second optimization approach: hybrid ANR algorithm}{47}{}\protected@file@percent }
+\@writefile{lof}{\contentsline {figure}{\numberline {37}{\ignorespaces Low-level implementation: Main loop and interrupt handling}}{47}{}\protected@file@percent }
+\@writefile{lof}{\contentsline {figure}{\numberline {38}{\ignorespaces Flow diagram of the code implementation of the main loop and interrupt handling on the \ac {DSP} core.}}{48}{}\protected@file@percent }
+\acronymused{DSP}
+\newlabel{fig:fig_dsp_logic.jpg}{{38}{48}{}{}{}}
+\@writefile{toc}{\contentsline {paragraph}{ANR function}{48}{}\protected@file@percent }
+\acronymused{DSP}
+\@writefile{toc}{\contentsline {subsection}{\numberline {4.3}Hardware simulation of previous examples}{49}{}\protected@file@percent }
+\@writefile{toc}{\contentsline {subsection}{\numberline {4.4}Optimization approach: hybrid ANR algorithm}{49}{}\protected@file@percent }
 \@setckpt{chapter_04}{
-\setcounter{page}{48}
+\setcounter{page}{50}
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@@ -169,7 +172,7 @@
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diff --git a/chapter_04.tex b/chapter_04.tex
index 89d2e25..a6e76c3 100644
--- a/chapter_04.tex
+++ b/chapter_04.tex
@@ -1,30 +1,29 @@
 \section{Hardware implementation and optimization of the ANR algorithm}
-This section aims to be the main part of this thesis. The first subchapter describes the hardware, on which the \ac{ANR} algorithm is implemented, including its environment, which serves as a link to the \ac{CI} system itself. The following subchapter continues with the basic implementation of the \ac{ANR} algorithm on the hardware itself and shall provide the reader with a basic understanding of its challenges, possibilities and limitations. This basic implementation shall serve as a baseline for the following optimizations.\\
-During the third chapter, this initial implementation is further optimized in order to achieve an improved real-time performance on the \ac{DSP}. The last subchapter picks the final optimizations of the \ac{ANR} algorithm itself as a central theme, especially with respect to the capabilities of a hybrid \ac{ANR} approach.
+This section can be considered as the heart of this thesis. The first subchapter describes the hardware, on which the \ac{ANR} algorithm is implemented, including its environment, which serves as a link to the \ac{CI} system itself. The following subchapter continues with the basic implementation of the \ac{ANR} algorithm on the hardware itself and shall provide the reader with a basic understanding of its challenges, possibilities and limitations. This basic implementation is then low-level simulated with some of the previuous use cases to get some idea of the general performance.\\
+The last subchapter picks the final optimizations of the \ac{ANR} algorithm itself as a central theme, especially with respect to the capabilities of a hybrid \ac{ANR} approach.
 \subsection{Description of the low-power DSP and its environment}
 This thesis considers a low-power \ac{SOC} architecture that integrates a general-purpose \ac{ARM} core with a dedicated \ac{DSP} core. The system combines the flexibility of an \ac{ARM}-based control processor with the computational efficiency of a specialized \ac{DSP}, splitting general computing tasks from real-time signal processing workloads.
 \subsubsection{Hardware overview}
 A 32-bit \ac{ARM} core serves as the primary control unit of the system. It is responsible for high-level application logic, system configuration, peripheral management as also scheduling and serves as a general-purpose processing unit. Due to its universal instruction set and extensive input/output interface, the \ac{ARM} core is well suited for handling general tasks and the interaction with the \ac{CI} system. Time-critical numerical processing is intentionally offloaded to the \ac{DSP} core in order to reduce computational load and power consumption on the control processor.\\ \\
-The \ac{DSP} used for the implementation features a 32-bit dual Harvard, dual \ac{MAC} architecture primarily designed for audio signal-processing applications in low-power embedded systems. It doesn´t feature a designated boot ROM, as it is initialized by the \ac{ARM} core. The firmware executing the \ac{ANR} algorithm is developed and programmed in the C programming language. The used propretiery compiler is highly efficient and generates optimized assembler code, which is then translated in machine code to execute the \ac{ANR} algorithm on incoming samples.\\ \\
+The \ac{DSP} used for the implementation features a 32-bit dual Harvard, dual \ac{MAC} architecture primarily designed for audio signal-processing applications in low-power embedded systems. It doesn´t feature a designated boot ROM, as it is initialized and managed by the \ac{ARM} core. The firmware executing the \ac{ANR} algorithm is developed and programmed in the C programming language. The used propretiery compiler is highly efficient and generates optimized assembler code, which is then translated in machine code to execute the \ac{ANR} algorithm on incoming samples.\\ \\
 All memory instances and registers of the \ac{SOC} are directly addressable by the \ac{ARM} through the standard busses, also enabling a simplified control of the \ac{DSP} through a shared memory section. The memory consists mainly out of the two followng parts:
 \begin{itemize}
     \item \textbf{Program Memory:} This memory section stores the executable code for both the \ac{ARM} core and the \ac{DSP} core. It contains the compiled instructions that define the behavior of the system, including the \ac{ANR} algorithm implemented on the \ac{DSP}.
     \item \textbf{Data Memory:} This memory section is used for storing runtime data and variables, required during the execution of the program. This also includes the memory section for input/output audio samples and intermediate processing results. The shared memory section between the \ac{ARM} core and the \ac{DSP} core is also part of the data memory, featuring a total size of 64 KB.
 \end{itemize}
-The data memory is supported by an integrated \ac{DMA} controller, which allows efficient data transfers between peripherals and memory without burdening the processing cores. This is particularly needed for transferring audio samples from the \ac{PCM} interface to the shared memory section for further processing by the \ac{DSP}, as well as transferring processed samples back to the \ac{PCM} interface for playback.\\ \\
-The mentioned 64 KB shared memory section between the \ac{ARM} core and the \ac{DSP} core is crucial for enabling efficient communication and data exchange between the two processing units, further described in the following subchapter.\\ \\ 
+The data memory is supported by an integrated \ac{DMA} controller, which allows efficient data transfers between peripherals and memory without burdening the processing cores. This is particularly needed for transferring audio samples from the \ac{PCM} interface to the shared memory section for further processing by the \ac{DSP}, as well as transferring processed samples back to the \ac{PCM} interface for playback. The shared memory section is crucial for enabling efficient communication and data exchange between the two processing units, further described in the following subchapter.\\ \\
 When the \ac{DSP} is not required to process audio data, it can be paused by pausing the clock provided to the \ac{DSP} core. When paused, the \ac{DSP} core enters a low-power state, still allowing the \ac{ARM} core to access its shared memory and wake up the \ac{DSP} core when needed. This mechanism helps to reduce overall power consumption, which is crucial for battery-operated devices like cochlear implants.\\ \\
 The processing unit of the \ac{DSP} is equipped with load/store architecture, meaning that, initially all operands need to be moved from the memory to the registers, before any operation can be performed. After this task is performed, the execution units (\ac{ALU} and multiplier) can perform their operations on the data and write back the results into the registers. Finally, the results need to be explicitly moved back to the memory.\\ \\
 Processor-wise, the \ac{DSP} includes a three stage pipeline consisting of fetch, decode, and execute stages, allowing for overlapping instruction execution and improved throughput. The architecture is optimized for high cycle efficiency when executing computationally intensive signal-processing workloads. The featured dual Harvard, dual \ac{MAC} architecture (two separate \ac{ALU}s) enables the execution of two \ac{MAC} operations, two memory operations (load/store) and two pointer updates in a single processor cycle.
-\subsubsection{Communication between the ARM core and the DSP}
-In order to ensure a smooth, but power-efficient, operation together with the \ac{CI} system, a interrupt-driven communication between the \ac{ARM} core and the \ac{DSP} core is crucial. Center of communication between the the cores is the already mentioned shared memory region accessible by both processing units. This shared memory enables the exchange of data without the need for separate communication protocols or input/output interfaces (refer to Figure \ref{fig:fig_dsp_setup.jpg}). Synchronization between the cores is achieved using interrupt-based signaling: the \ac{ARM} core initiates processing requests by triggering waking up the \ac{DSP} and triggering an interrupt which sets an action flag, while the \ac{DSP} notifies the \ac{ARM} core upon completion of a task also by changing an interrupt register. This approach ensures efficient coordination while minimizing active waiting (polling) and therefore unnecessary power consumption.
+\subsubsection{Communication between the ARM core and the DSP core}
+In order to ensure a smooth, but power-efficient, operation together with the \ac{CI} system, a interrupt-driven communication between the \ac{ARM} core and the \ac{DSP} core is crucial. Center of communication between the the cores is the already mentioned shared memory region accessible by both processing units. This shared memory enables the exchange of data without the need for separate communication protocols or input/output interfaces (refer to Figure \ref{fig:fig_dsp_setup.jpg}). Synchronization between the cores is achieved using interrupt-based signaling: the \ac{ARM} core initiates processing requests by waking up the \ac{DSP} and triggering an interrupt which sets an action flag, while the \ac{DSP} notifies the \ac{ARM} core upon completion of a task also by changing an interrupt register (for simplicity reasons, this behaviour will be just called ``interrupts'' in the remaining thesis). This approach ensures efficient coordination while minimizing active waiting (polling) and therefore unnecessary power consumption.
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_setup.jpg}
     \caption{Simplified visualization of the interaction between the \ac{ARM} core and the \ac{DSP} core}
     \label{fig:fig_dsp_setup.jpg}
 \end{figure}
-\noindent The \ac{ARM} Core receives the 16-bit audio data (the corrupted signal and the reference noise signal via two channels) from the CI system via a \ac{PCM} interface, which offers one 32-bit input and one 32-bit output register. An interrupt triggers the integrated \ac{DMA} controller when the input register is occupied, which transfers the audio data from the \ac{PCM} interface to buffer in a predefined memory location. Once completed, the \ac{DSP} core is requested to start processing the audio data. The \ac{DSP} core then reads the audio samples from the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the a 32-bit processed sample (shifted from 16 bit) back to an output buffer, also located in the shared memory. Finally, the \ac{ARM} core is notified via an interrupt from the \ac{DSP} core, that the processing is complete - the \ac{DMA} controller then transfers the processed audio samples from the output buffer back to the \ac{PCM} interface for playback (refer to Figure \ref{fig:fig_dsp_comm.jpg}).\\ \\ 
+\noindent The \ac{ARM} Core receives the 16-bit audio data (the corrupted signal and the reference noise signal via two channels) from the CI system via a \ac{PCM} interface, which offers one 32-bit input and one 32-bit output register. An interrupt triggers the integrated \ac{DMA} controller when the input register is occupied, which transfers the audio data from the \ac{PCM} interface to the input buffer in a predefined memory location (now in two 16-bit samples again). Once completed, the \ac{DSP} core is requested to start processing the audio data. The \ac{DSP} core then reads the audio samples from the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the a 16-bit processed sample back to an output buffer, also located in the shared memory. Finally, the \ac{ARM} core is notified via an interrupt from the \ac{DSP} core, that the processing is complete - the \ac{DMA} controller then transfers the processed audio samples from the output buffer back to the \ac{PCM} interface for playback (refer to Figure \ref{fig:fig_dsp_comm.jpg}).\\ \\ 
 \begin{figure}[H]
     \centering
     \includegraphics[width=0.9\linewidth]{Bilder/fig_dsp_comm.jpg}
@@ -39,28 +38,28 @@ The implementation of the \ac{ANR} algorithm on the \ac{DSP} follows the same ov
 \begin{itemize}
     \item \textbf{Idle:} The \ac{ARM} core waits for an interrupt from the \ac{DMA} controller, indicating that new audio samples are available in the input buffer.
     \item \textbf{Work:} After receiving the interrupt, the \ac{ARM} core triggers an interrupt on the \ac{DSP} core to start processing the audio samples.
-    \item \textbf{Wait:} The \ac{ARM} core waits for an interrupt from the \ac{DSP} core, indicating that the processing is complete.
+    \item \textbf{Wait:} After recieving the first interrupt, which signals that the \ac{DSP} startedprocessing the sample, the \ac{ARM} core waits for the second interrupt, indicating that the processing is complete.
     \item \textbf{Done/Idle:} Once the processing is complete, the \ac{ARM} core triggers the \ac{DMA} controller to transfer the processed audio samples from the output buffer back to the \ac{PCM} interface for playback. The \ac{ARM} core then returns to the idle state, waiting for the next batch of audio samples.
 \end{itemize}
 On the contrary, the \ac{DSP} core operates in an interrupt-driven manner:
 \begin{itemize}
     \item \textbf{Idle:} The \ac{DSP} core remains in a halted state, waiting to be activated by the \ac{ARM} core to start processing.
-    \item \textbf{Work:} Once activated, the \ac{DSP} core reads the audio samples from the input buffer located in the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the processed samples back to the output buffer in the shared memory.
+    \item \textbf{Work:} Once activated, the \ac{DSP} core signals the \ac{ARM} core the beginning of its work cycle by raising an interrupt, reads the audio samples from the input buffer located in the shared memory, processes them using the implemented \ac{ANR} algorithm, and writes the processed samples back to the output buffer in the shared memory.
     \item \textbf{Done/Idle:} After completing the processing, the \ac{DSP} core triggers an interrupt on the \ac{ARM} core to notify that the processing is complete. The \ac{DSP} core then returns to its sleeping state, waiting for the next processing request.
 \end{itemize}
-\noindent The \ac{DMA} controller plays a crucial role in this architecture by handling the data transfers between the \ac{PCM} interface and the shared memory buffers. It operates independently of both the \ac{ARM} core and the \ac{DSP} core, allowing for efficient data movement without burdening the processing units. The \ac{DMA} controller is configured to transfer audio samples in blocks, triggering interrupts to notify the respective cores when new data is available or when processing is complete. 
+\noindent The \ac{DMA} controller plays a crucial role in this architecture by handling the data transfers between the \ac{PCM} interface and the shared memory buffers. It operates independently of both the \ac{ARM} core and the \ac{DSP} core, allowing for efficient data movement without burdening the processing units. 
 \begin{figure}[H]
     \centering
     \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_dma.jpg}
     \caption{Detailed visualization of the \ac{DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggerd, either to the \ac{DSP} core or to the \ac{ARM} core, depending on the input or output direction.}
     \label{fig:fig_dsp_dma.jpg}
 \end{figure}
-\noindent Figure \ref{fig:fig_dsp_dma.jpg} visualizes the concrete operation of the \ac{DMA} controller during the audio sample processing. The \ac{DMA} controller is configured to samplewise transfer the audio samples from the \ac{PCM} interface into a defined memory location of the shared memory (input buffer). When the input buffer is filled with one sample of both channels, an interrupt is triggered to the \ac{DSP} core, notifying it to start processing the available samples. After processing, the results are written to another designated section of the memory (output buffer). When the output buffer recieves the result, another interrupt is triggered to the \ac{DMA} controller, indicating that the processed samples are ready to be transferred back to the \ac{PCM} interface for playback. \\ \\
-As the \ac{ARM} operation is not the main focus of this thesis, the following section will focus on implementation of the \ac{ANR} algorithm on the \ac{DSP} core itself. As the behavior of the \ac{ARM} core is already sufficiently described, furhter implementaion details will be omitted in the following. 
+\noindent Figure \ref{fig:fig_dsp_dma.jpg} visualizes the concrete operation of the \ac{DMA} controller during the audio sample processing. The \ac{DMA} controller is configured to samplewise transfer the audio samples from the \ac{PCM} interface to the input buffer of the shared memory. When the input buffer is filled with one sample of both channels, an interrupt is triggered to the \ac{DSP} core, notifying it to start processing the available samples. After processing, the results are written into the output buffer in the shared memory. Once the output buffer is occupied, another interrupt is triggered to the \ac{DMA} controller, indicating that the processed samples are ready to be transferred back to the \ac{PCM} interface for playback. \\ \\
+As the \ac{ARM} operation is not the main focus of this thesis and its behavior is already sufficiently described, further implementaion details will be omitted in the following while the focus will be put on implementation of the \ac{ANR} algorithm on the \ac{DSP} core itself.
 \subsubsection{Code implementation of the ANR algorithm on the DSP}
-The implementation of the \ac{ANR} algorithm on the \ac{DSP} core is structured into several key sections, each responsible for specific aspects of the algorithm's functionality. The following paragraphs outline the main components of the code implementation:
+The implementation of the \ac{ANR} algorithm on the \ac{DSP} core is structured into several key sections, each responsible for specific aspects of the algorithm's functionality. The following paragraphs outline the main components:
 \paragraph{Memory initialization and mapping}
-The memory initialization section starts with the definition of the interrupt register (0xC00004) and the corresponding bit masks used to control the interrupt behavior of the \ac{DSP} core. Afterwards, a section in the shared memory is defined for the storage of input and output audio samples after/before the transport to/from the \ac{PCM} interface. The output section is initialized with an offset of 16 bytes from the input section (0x800000), resulting in a storage capability of 4 32-bit double-words for each of the two memory sections - this is more than needed, but prevents future memory relocation, if the necessety for more space would arise. After this initialization, the interrupt register and the memory sections are declared as volatile variables, telling the compiler, that these variables can be changed outside the normal program flow (e.g., by hardware interrupts), preventing certain optimizations. The storage capability of 4 16-bit words shows itself in the declaration of the input and output arrays, consisting of 4 elements each. Finally, a variable is declared to signal the \ac{DSP} core, an interrupt has occured, which changes the state of the interrupt register and signals a processing request.
+The memory initialization section starts with the definition of the interrupt register (0xC00004) and the corresponding bit masks used to control the interrupt behavior of the \ac{DSP} core. Afterwards, a section in the shared memory is defined for the storage of input and output audio samples after/before the transport to/from the \ac{PCM} interface. The output section is initialized with an offset of 16 bytes from the input section (0x800000), resulting in a storage capability of 4 32-bit double-words for each of the two memory sections - this is more than needed, but prevents future memory relocation, if the necessety for more space would arise. After this initialization, the interrupt register and the memory sections are declared as volatile variables, telling the compiler, that these variables can be changed outside the normal program flow (e.g., by hardware interrupts), preventing certain optimizations. The final input/output buffers are then declared in form of two 16-bit arrays, consisting of 4 elements each. Finally, a variable is declared to signal the \ac{DSP} core, an interrupt has occured, which changes the state of the interrupt register and signals a processing request.
 \begin{figure}[H]
     \centering
     \begin{lstlisting}[language=C]
@@ -81,9 +80,16 @@ The memory initialization section starts with the definition of the interrupt re
     \label{fig:fig_dps_code_memory}
     \caption{Low-level implementation: Memory initialization and mapping}
 \end{figure}
+Figure \ref{fig:fig_compiler.jpg} shows an exemplary memory map of the input buffer array, taken from the compiler debugger. As the array is initialized as a 16 bit integer array, each element occupies 2 bytes of memory.
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_compiler.jpg}
+    \caption{Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16 bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array.}
+    \label{fig:fig_compiler.jpg}
+\end{figure}
 \paragraph{Main loop and interrupt handling}
 The main loop of the \ac{DSP} core is quite compact, as it mainly focuses on handling interrupts and delegating the sample processing to the \ac{ANR} function. The loop starts by enabling interrupts with a compiler-specific function and setting up pointers for the output buffer and the sample variable. After setting the action flag to zero, the main function enters an infinite loop, signaling the \ac{ARM} core it´s halted state by setting the interrupt register to 1 and halting the core.\\ \\
-If the \ac{ARM} core requests a sample to be processed, a interrupt is triggered, which activates the \ac{DSP} core and sets the action flag to 1. The main loop then checks the action flag, and sets the interrupt register back to 0, indicating the \ac{ARM} core it is now processing the sample. After resetting the action flag, the output pointer is updated to point to the next position in the output buffer using a cyclic addition function. Before triggering the calc()-function the calculated sample from the previous cycle is moved from its temporary memory location to the current position in the output buffer. Afterwards, the calc()-function is triggered for the current cycle, and the loop ends. 
+If the \ac{ARM} core requests a sample to be processed, it activates the \ac{DSP} core and triggers an interrupt, which sets the action flag to 1. The main loop then checks the action flag, and sets the interrupt register back to 0, indicating the \ac{ARM} core it is now processing the sample. After resetting the action flag, the output pointer is updated to point to the next position in the output buffer using a cyclic addition function. Before triggering the calc()-function, the calculated sample from the previous cycle is moved from its temporary memory location to the current position in the output buffer. Afterwards, the calc()-function is triggered for the current cycle and the loop restarts. The flow diagram in Figure \ref{fig:fig_dsp_logic.jpg} visualizes the described behavior of the main loop and interrupt handling on the \ac{DSP} core.
 \begin{figure}[H]
     \centering
     \begin{lstlisting}[language=C]
@@ -108,7 +114,14 @@ If the \ac{ARM} core requests a sample to be processed, a interrupt is triggered
     \label{fig:fig_dps_code_mainloop}
     \caption{Low-level implementation: Main loop and interrupt handling}
 \end{figure}
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=1.0\linewidth]{Bilder/fig_dsp_logic.jpg}
+    \caption{Flow diagram of the code implementation of the main loop and interrupt handling on the \ac{DSP} core.}
+    \label{fig:fig_dsp_logic.jpg}
+\end{figure}
 \paragraph{ANR function}
-\subsection{First optimization approach: algorithm implementation}
-\subsection{Second optimization approach: hybrid ANR algorithm}
+The ANR algorithm implemented on the \ac{DSP} core follows the same structure as the high-level implementation described in the previous chapter, and will therefore not be described in detail. However, the hardware-specific optimizations, responsible for a real-time capable implementation, shall be outlined in a more detailed manner.\\ \\
+\subsection{Hardware simulation of previous examples}
+\subsection{Optimization approach: hybrid ANR algorithm}
 
diff --git a/drawio/fig_dsp_logic.drawio b/drawio/fig_dsp_logic.drawio
new file mode 100644
index 0000000..dbd01c7
--- /dev/null
+++ b/drawio/fig_dsp_logic.drawio
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