Plots überarbeitet
This commit is contained in:
Patrick Hangl
124
chapter_04.aux
124
chapter_04.aux
@@ -1,28 +1,28 @@
|
||||
\relax
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {4}Hardware implementation and performance quantization of the ANR Algorithm on a low-power system}{40}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {section}{\numberline {4}Hardware implementation and performance quantization of the ANR Algorithm on a low-power system}{42}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{CI}
|
||||
\acronymused{ANR}
|
||||
\acronymused{ANR}
|
||||
\acronymused{ANR}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Low-power system architecture and integration}{40}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Low-power system architecture and integration}{42}{}\protected@file@percent }
|
||||
\AC@undonewlabel{acro:SOC}
|
||||
\newlabel{acro:SOC}{{4.1}{40}{}{subsection.4.1}{}}
|
||||
\newlabel{acro:SOC}{{4.1}{42}{}{}{}}
|
||||
\acronymused{SOC}
|
||||
\AC@undonewlabel{acro:ARM}
|
||||
\newlabel{acro:ARM}{{4.1}{40}{}{subsection.4.1}{}}
|
||||
\newlabel{acro:ARM}{{4.1}{42}{}{}{}}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1}ARM and DSP hardware architecture overview}{40}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1}ARM and DSP hardware architecture overview}{42}{}\protected@file@percent }
|
||||
\acronymused{ARM}
|
||||
\acronymused{ARM}
|
||||
\acronymused{CI}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:MAC}
|
||||
\newlabel{acro:MAC}{{4.1.1}{40}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:MAC}{{4.1.1}{42}{}{}{}}
|
||||
\acronymused{MAC}
|
||||
\acronymused{ARM}
|
||||
\acronymused{ANR}
|
||||
@@ -37,10 +37,10 @@
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:DMA}
|
||||
\newlabel{acro:DMA}{{4.1.1}{41}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:DMA}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{DMA}
|
||||
\AC@undonewlabel{acro:PCM}
|
||||
\newlabel{acro:PCM}{{4.1.1}{41}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:PCM}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
@@ -51,13 +51,13 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\AC@undonewlabel{acro:ALU}
|
||||
\newlabel{acro:ALU}{{4.1.1}{41}{}{subsubsection.4.1.1}{}}
|
||||
\newlabel{acro:ALU}{{4.1.1}{43}{}{}{}}
|
||||
\acronymused{ALU}
|
||||
\acronymused{DSP}
|
||||
\acronymused{MAC}
|
||||
\acronymused{ALU}
|
||||
\acronymused{MAC}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Intercore communication mechanisms}{41}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Intercore communication mechanisms}{43}{}\protected@file@percent }
|
||||
\acronymused{CI}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
@@ -65,12 +65,12 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {32}{\ignorespaces Simplified visualization of the interaction between the \ac {CI}-System, the \ac {ARM} core and the \ac {DSP} core, making use of the \ac {PCM} interface and shared memory for audio data exchange.}}{42}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {32}{\ignorespaces Simplified visualization of the interaction between the \ac {CI}-System, the \ac {ARM} core and the \ac {DSP} core, making use of the \ac {PCM} interface and shared memory for audio data exchange.}}{44}{}\protected@file@percent }
|
||||
\acronymused{CI}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
\newlabel{fig:fig_dsp_setup.jpg}{{32}{42}{}{figure.32}{}}
|
||||
\newlabel{fig:fig_dsp_setup.jpg}{{32}{44}{}{}{}}
|
||||
\acronymused{ARM}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DMA}
|
||||
@@ -82,12 +82,12 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{DMA}
|
||||
\acronymused{PCM}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {33}{\ignorespaces Simplified flowchart of the sample processing between the \ac {ARM} core and the \ac {DSP} core via interrupts and shared memory.}}{43}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {33}{\ignorespaces Simplified flowchart of the sample processing between the \ac {ARM} core and the \ac {DSP} core via interrupts and shared memory.}}{45}{}\protected@file@percent }
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_comm.jpg}{{33}{43}{}{figure.33}{}}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}Software architecture and execution flow}{43}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}ARM–DSP communication and data exchange details}{43}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_comm.jpg}{{33}{45}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}Software architecture and execution flow}{45}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}ARM–DSP communication and data exchange details}{45}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
@@ -117,11 +117,11 @@
|
||||
\acronymused{PCM}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {34}{\ignorespaces Detailed visualization of the \ac {DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggered, either to the \ac {DSP} core or to the \ac {ARM} core, depending on, if triggered during a Read- or Write-operation.}}{45}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {34}{\ignorespaces Detailed visualization of the \ac {DMA} operations between the PCM interface to the shared memory section. When the memory buffer occupied, an interrupt is triggered, either to the \ac {DSP} core or to the \ac {ARM} core, depending on, if triggered during a Read- or Write-operation.}}{47}{}\protected@file@percent }
|
||||
\acronymused{DMA}
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
\newlabel{fig:fig_dsp_dma.jpg}{{34}{45}{}{figure.34}{}}
|
||||
\newlabel{fig:fig_dsp_dma.jpg}{{34}{47}{}{}{}}
|
||||
\acronymused{DMA}
|
||||
\acronymused{DMA}
|
||||
\acronymused{PCM}
|
||||
@@ -131,18 +131,18 @@
|
||||
\acronymused{ARM}
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.2}System control flow and main processing loop}{45}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.2}System control flow and main processing loop}{47}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Memory initialization and mapping}{45}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{Memory initialization and mapping}{47}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{PCM}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dps_code_memory}{{4.2.2}{46}{}{lstnumber.-2.13}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {35}{\ignorespaces Low-level implementation: Memory initialization and mapping}}{46}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {36}{\ignorespaces Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16-bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise addressing is a result of the compiler abstraction.}}{46}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_compiler.jpg}{{36}{46}{}{figure.36}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{46}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dps_code_memory}{{4.2.2}{48}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {35}{\ignorespaces Low-level implementation: Memory initialization and mapping}}{48}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {36}{\ignorespaces Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16-bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise addressing is a result of the compiler abstraction.}}{48}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_compiler.jpg}{{36}{48}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{48}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{ANR}
|
||||
\acronymused{ARM}
|
||||
@@ -150,76 +150,76 @@
|
||||
\acronymused{DSP}
|
||||
\acronymused{ARM}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {37}{\ignorespaces Low-level implementation: Main loop and interrupt handling}}{47}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dps_code_mainloop}{{37}{47}{}{figure.37}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {38}{\ignorespaces Flow diagram of the code implementation of the main loop and interrupt handling on the \ac {DSP} core.}}{48}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {37}{\ignorespaces Low-level implementation: Main loop and interrupt handling}}{49}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dps_code_mainloop}{{37}{49}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {38}{\ignorespaces Flow diagram of the code implementation of the main loop and interrupt handling on the \ac {DSP} core.}}{50}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_logic.jpg}{{38}{48}{}{figure.38}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{calculate\_output()-function}{48}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_logic.jpg}{{38}{50}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{calculate\_output()-function}{50}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.3}DSP-level implementation of the ANR algorithm}{49}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsection}{\numberline {4.3}DSP-level implementation of the ANR algorithm}{51}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}DSP-specific optimizations for real-time processing}{49}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}DSP-specific optimizations for real-time processing}{51}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Logic operations}{49}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{Logic operations}{51}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {39}{\ignorespaces Manual implementation of a max-function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operation.}}{49}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_find_max}{{39}{49}{}{figure.39}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Cyclic array iteration}{49}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {39}{\ignorespaces Manual implementation of a max-function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operation.}}{51}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_find_max}{{39}{51}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Cyclic array iteration}{51}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {40}{\ignorespaces Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute a pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}}{50}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{50}{}{figure.40}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {40}{\ignorespaces Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute a pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}}{52}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{52}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{Fractional fixed-point arithmetic}{50}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{Fractional fixed-point arithmetic}{52}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{MAC}
|
||||
\acronymused{ALU}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Performance quantization of the ANR calculation}{50}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Performance quantization of the ANR calculation}{52}{}\protected@file@percent }
|
||||
\acronymused{ANR}
|
||||
\acronymused{DSP}
|
||||
\acronymused{FIR}
|
||||
\acronymused{FIR}
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{write\_buffer}{51}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{write\_buffer}{53}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\@writefile{toc}{\contentsline {paragraph}{apply\_fir\_filter}{51}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{apply\_fir\_filter}{53}{}\protected@file@percent }
|
||||
\acronymused{FIR}
|
||||
\acronymused{MAC}
|
||||
\acronymused{DSP}
|
||||
\acronymused{DSP}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {41}{\ignorespaces Code snippet of the $apply\_fir\_filter$-function, showing the use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. The loop iterates through the filter coefficients and reference noise signal samples, performing two multiplications and two additions in each cycle.}}{52}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {41}{\ignorespaces Code snippet of the $apply\_fir\_filter$-function, showing the use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. The loop iterates through the filter coefficients and reference noise signal samples, performing two multiplications and two additions in each cycle.}}{54}{}\protected@file@percent }
|
||||
\acronymused{MAC}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{52}{}{figure.41}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {42}{\ignorespaces Visualization of the FIR filter calculation in the $apply\_fir\_filter$-function during the 2nd cyclce of a calculation loop. The reference noise signal samples are stored in the sample line, while the filter coefficients are stored in a separate memory section (filter line).}}{52}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{52}{}{figure.42}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_output}{53}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_filter\_coefficient}{53}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{54}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {42}{\ignorespaces Visualization of the FIR filter calculation in the $apply\_fir\_filter$-function during the 2nd cyclce of a calculation loop. The reference noise signal samples are stored in the sample line, while the filter coefficients are stored in a separate memory section (filter line).}}{54}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{54}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_output}{55}{}\protected@file@percent }
|
||||
\@writefile{toc}{\contentsline {paragraph}{update\_filter\_coefficient}{55}{}\protected@file@percent }
|
||||
\acronymused{DSP}
|
||||
\acronymused{MAC}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {43}{\ignorespaces Code snippet of the $update\_filter\_coefficient$-function, again making use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. Additionaly, 32-bit values are loaded and stored as 64-bit values, using two also intrinisc functions, allowing to update two filter coefficients in a single cycle.}}{53}{}\protected@file@percent }
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {43}{\ignorespaces Code snippet of the $update\_filter\_coefficient$-function, again making use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. Additionaly, 32-bit values are loaded and stored as 64-bit values, using two also intrinisc functions, allowing to update two filter coefficients in a single cycle.}}{55}{}\protected@file@percent }
|
||||
\acronymused{MAC}
|
||||
\acronymused{DSP}
|
||||
\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{53}{}{figure.43}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {44}{\ignorespaces Visualization of the coefficient calculation in the $update\_filter\_coefficient$-function during the 2nd cyclce of a calculation loop. The output is multiplied with the step size and the corresponding sample from the sample line, before being added to the current filter coefficient.}}{54}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{54}{}{figure.44}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{write\_output}{54}{}\protected@file@percent }
|
||||
\newlabel{equation_computing}{{24}{54}{}{equation.24}{}}
|
||||
\newlabel{equation_c_1}{{25}{54}{}{equation.25}{}}
|
||||
\newlabel{equation_c_2}{{26}{54}{}{equation.26}{}}
|
||||
\newlabel{equation_c_3}{{27}{54}{}{equation.27}{}}
|
||||
\newlabel{equation_c_4}{{28}{54}{}{equation.28}{}}
|
||||
\newlabel{equation_c_5}{{30}{54}{}{equation.30}{}}
|
||||
\newlabel{equation_computing_final}{{31}{55}{}{equation.31}{}}
|
||||
\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{55}{}{}{}}
|
||||
\@writefile{lof}{\contentsline {figure}{\numberline {44}{\ignorespaces Visualization of the coefficient calculation in the $update\_filter\_coefficient$-function during the 2nd cyclce of a calculation loop. The output is multiplied with the step size and the corresponding sample from the sample line, before being added to the current filter coefficient.}}{56}{}\protected@file@percent }
|
||||
\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{56}{}{}{}}
|
||||
\@writefile{toc}{\contentsline {paragraph}{write\_output}{56}{}\protected@file@percent }
|
||||
\newlabel{equation_computing}{{24}{56}{}{}{}}
|
||||
\newlabel{equation_c_1}{{25}{56}{}{}{}}
|
||||
\newlabel{equation_c_2}{{26}{56}{}{}{}}
|
||||
\newlabel{equation_c_3}{{27}{56}{}{}{}}
|
||||
\newlabel{equation_c_4}{{28}{56}{}{}{}}
|
||||
\newlabel{equation_c_5}{{30}{56}{}{}{}}
|
||||
\newlabel{equation_computing_final}{{31}{57}{}{}{}}
|
||||
\acronymused{DSP}
|
||||
\@setckpt{chapter_04}{
|
||||
\setcounter{page}{56}
|
||||
\setcounter{page}{58}
|
||||
\setcounter{equation}{31}
|
||||
\setcounter{enumi}{0}
|
||||
\setcounter{enumii}{0}
|
||||
@@ -354,7 +354,7 @@
|
||||
\setcounter{lstnumber}{15}
|
||||
\setcounter{FancyVerbLine}{0}
|
||||
\setcounter{linenumber}{1}
|
||||
\setcounter{LN@truepage}{55}
|
||||
\setcounter{LN@truepage}{57}
|
||||
\setcounter{FancyVerbWriteLine}{0}
|
||||
\setcounter{FancyVerbBufferLine}{0}
|
||||
\setcounter{FV@TrueTabGroupLevel}{0}
|
||||
|
||||
Reference in New Issue
Block a user