diff --git a/chapter_04.aux b/chapter_04.aux index 7ceab72..2196128 100644 --- a/chapter_04.aux +++ b/chapter_04.aux @@ -7,10 +7,10 @@ \acronymused{ANR} \@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Low-power system architecture and integration}{42}{}\protected@file@percent } \AC@undonewlabel{acro:SOC} -\newlabel{acro:SOC}{{4.1}{42}{}{}{}} +\newlabel{acro:SOC}{{4.1}{42}{}{subsection.4.1}{}} \acronymused{SOC} \AC@undonewlabel{acro:ARM} -\newlabel{acro:ARM}{{4.1}{42}{}{}{}} +\newlabel{acro:ARM}{{4.1}{42}{}{subsection.4.1}{}} \acronymused{ARM} \acronymused{DSP} \acronymused{ARM} @@ -22,7 +22,7 @@ \acronymused{DSP} \acronymused{DSP} \AC@undonewlabel{acro:MAC} -\newlabel{acro:MAC}{{4.1.1}{42}{}{}{}} +\newlabel{acro:MAC}{{4.1.1}{42}{}{subsubsection.4.1.1}{}} \acronymused{MAC} \acronymused{ARM} \acronymused{ANR} @@ -37,10 +37,10 @@ \acronymused{ARM} \acronymused{DSP} \AC@undonewlabel{acro:DMA} -\newlabel{acro:DMA}{{4.1.1}{43}{}{}{}} +\newlabel{acro:DMA}{{4.1.1}{43}{}{subsubsection.4.1.1}{}} \acronymused{DMA} \AC@undonewlabel{acro:PCM} -\newlabel{acro:PCM}{{4.1.1}{43}{}{}{}} +\newlabel{acro:PCM}{{4.1.1}{43}{}{subsubsection.4.1.1}{}} \acronymused{PCM} \acronymused{DSP} \acronymused{PCM} @@ -51,7 +51,7 @@ \acronymused{DSP} \acronymused{DSP} \AC@undonewlabel{acro:ALU} -\newlabel{acro:ALU}{{4.1.1}{43}{}{}{}} +\newlabel{acro:ALU}{{4.1.1}{43}{}{subsubsection.4.1.1}{}} \acronymused{ALU} \acronymused{DSP} \acronymused{MAC} @@ -70,7 +70,7 @@ \acronymused{ARM} \acronymused{DSP} \acronymused{PCM} -\newlabel{fig:fig_dsp_setup.jpg}{{32}{44}{}{}{}} +\newlabel{fig:fig_dsp_setup.jpg}{{32}{44}{}{figure.32}{}} \acronymused{ARM} \acronymused{PCM} \acronymused{DMA} @@ -85,7 +85,7 @@ \@writefile{lof}{\contentsline {figure}{\numberline {33}{\ignorespaces Simplified flowchart of the sample processing between the \ac {ARM} core and the \ac {DSP} core via interrupts and shared memory.}}{45}{}\protected@file@percent } \acronymused{ARM} \acronymused{DSP} -\newlabel{fig:fig_dsp_comm.jpg}{{33}{45}{}{}{}} +\newlabel{fig:fig_dsp_comm.jpg}{{33}{45}{}{figure.33}{}} \@writefile{toc}{\contentsline {subsection}{\numberline {4.2}Software architecture and execution flow}{45}{}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}ARM–DSP communication and data exchange details}{45}{}\protected@file@percent } \acronymused{ANR} @@ -121,7 +121,7 @@ \acronymused{DMA} \acronymused{DSP} \acronymused{ARM} -\newlabel{fig:fig_dsp_dma.jpg}{{34}{47}{}{}{}} +\newlabel{fig:fig_dsp_dma.jpg}{{34}{47}{}{figure.34}{}} \acronymused{DMA} \acronymused{DMA} \acronymused{PCM} @@ -138,10 +138,10 @@ \acronymused{DSP} \acronymused{PCM} \acronymused{DSP} -\newlabel{fig:fig_dps_code_memory}{{4.2.2}{48}{}{}{}} +\newlabel{fig:fig_dps_code_memory}{{4.2.2}{48}{}{lstnumber.-2.13}{}} \@writefile{lof}{\contentsline {figure}{\numberline {35}{\ignorespaces Low-level implementation: Memory initialization and mapping}}{48}{}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {36}{\ignorespaces Exemplary memory map of the 4-element input buffer array. As it is initialized as a 16-bit integer array, each element occupies 2 bytes of memory, resulting in a total size of 8 bytes for the entire array. As the DSP architecture works in 32-bit double-words, the bytewise addressing is a result of the compiler abstraction.}}{48}{}\protected@file@percent } -\newlabel{fig:fig_compiler.jpg}{{36}{48}{}{}{}} +\newlabel{fig:fig_compiler.jpg}{{36}{48}{}{figure.36}{}} \@writefile{toc}{\contentsline {paragraph}{Main loop and interrupt handling}{48}{}\protected@file@percent } \acronymused{DSP} \acronymused{ANR} @@ -151,10 +151,10 @@ \acronymused{ARM} \acronymused{DSP} \@writefile{lof}{\contentsline {figure}{\numberline {37}{\ignorespaces Low-level implementation: Main loop and interrupt handling}}{49}{}\protected@file@percent } -\newlabel{fig:fig_dps_code_mainloop}{{37}{49}{}{}{}} +\newlabel{fig:fig_dps_code_mainloop}{{37}{49}{}{figure.37}{}} \@writefile{lof}{\contentsline {figure}{\numberline {38}{\ignorespaces Flow diagram of the code implementation of the main loop and interrupt handling on the \ac {DSP} core.}}{50}{}\protected@file@percent } \acronymused{DSP} -\newlabel{fig:fig_dsp_logic.jpg}{{38}{50}{}{}{}} +\newlabel{fig:fig_dsp_logic.jpg}{{38}{50}{}{figure.38}{}} \@writefile{toc}{\contentsline {paragraph}{calculate\_output()-function}{50}{}\protected@file@percent } \acronymused{DSP} \acronymused{ANR} @@ -168,11 +168,11 @@ \acronymused{DSP} \acronymused{DSP} \@writefile{lof}{\contentsline {figure}{\numberline {39}{\ignorespaces Manual implementation of a max-function, returning the maximum of two integer values, taking 12 cycles to execute. The intrinsic functions of the DSP compiler allows a 4-cycle implementation of such an operation.}}{51}{}\protected@file@percent } -\newlabel{fig:fig_dsp_code_find_max}{{39}{51}{}{}{}} +\newlabel{fig:fig_dsp_code_find_max}{{39}{51}{}{figure.39}{}} \@writefile{toc}{\contentsline {paragraph}{Cyclic array iteration}{51}{}\protected@file@percent } \acronymused{ANR} \@writefile{lof}{\contentsline {figure}{\numberline {40}{\ignorespaces Manual implementation of a cyclic array iteration function in C, taking the core 20 cycles to execute a pointer inremen of 1. The intrinsic functions of the DSP compiler allows a single-cycle implementation of such cyclic additions.}}{52}{}\protected@file@percent } -\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{52}{}{}{}} +\newlabel{fig:fig_dsp_code_cyclic_add}{{40}{52}{}{figure.40}{}} \acronymused{DSP} \acronymused{DSP} \@writefile{toc}{\contentsline {paragraph}{Fractional fixed-point arithmetic}{52}{}\protected@file@percent } @@ -196,9 +196,9 @@ \@writefile{lof}{\contentsline {figure}{\numberline {41}{\ignorespaces Code snippet of the $apply\_fir\_filter$-function, showing the use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. The loop iterates through the filter coefficients and reference noise signal samples, performing two multiplications and two additions in each cycle.}}{54}{}\protected@file@percent } \acronymused{MAC} \acronymused{DSP} -\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{54}{}{}{}} +\newlabel{fig:fig_dsp_code_apply_fir_filter}{{41}{54}{}{figure.41}{}} \@writefile{lof}{\contentsline {figure}{\numberline {42}{\ignorespaces Visualization of the FIR filter calculation in the $apply\_fir\_filter$-function during the 2nd cyclce of a calculation loop. The reference noise signal samples are stored in the sample line, while the filter coefficients are stored in a separate memory section (filter line).}}{54}{}\protected@file@percent } -\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{54}{}{}{}} +\newlabel{fig:fig_dsp_fir_cycle.jpg}{{42}{54}{}{figure.42}{}} \@writefile{toc}{\contentsline {paragraph}{update\_output}{55}{}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{update\_filter\_coefficient}{55}{}\protected@file@percent } \acronymused{DSP} @@ -206,20 +206,20 @@ \@writefile{lof}{\contentsline {figure}{\numberline {43}{\ignorespaces Code snippet of the $update\_filter\_coefficient$-function, again making use of the dual \ac {MAC} architecture of the \ac {DSP} and the fractional multiplication function. Additionaly, 32-bit values are loaded and stored as 64-bit values, using two also intrinisc functions, allowing to update two filter coefficients in a single cycle.}}{55}{}\protected@file@percent } \acronymused{MAC} \acronymused{DSP} -\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{55}{}{}{}} +\newlabel{fig:fig_dsp_code_update_filter_coefficients}{{43}{55}{}{figure.43}{}} \@writefile{lof}{\contentsline {figure}{\numberline {44}{\ignorespaces Visualization of the coefficient calculation in the $update\_filter\_coefficient$-function during the 2nd cyclce of a calculation loop. The output is multiplied with the step size and the corresponding sample from the sample line, before being added to the current filter coefficient.}}{56}{}\protected@file@percent } -\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{56}{}{}{}} +\newlabel{fig:fig_dsp_coefficient_cycle.jpg}{{44}{56}{}{figure.44}{}} \@writefile{toc}{\contentsline {paragraph}{write\_output}{56}{}\protected@file@percent } -\newlabel{equation_computing}{{24}{56}{}{}{}} -\newlabel{equation_c_1}{{25}{56}{}{}{}} -\newlabel{equation_c_2}{{26}{56}{}{}{}} -\newlabel{equation_c_3}{{27}{56}{}{}{}} -\newlabel{equation_c_4}{{28}{56}{}{}{}} -\newlabel{equation_c_5}{{29}{56}{}{}{}} -\newlabel{equation_computing_final}{{31}{57}{}{}{}} +\newlabel{equation_computing}{{24}{56}{}{equation.24}{}} +\newlabel{equation_c_1}{{25}{56}{}{equation.25}{}} +\newlabel{equation_c_2}{{26}{56}{}{equation.26}{}} +\newlabel{equation_c_3}{{27}{56}{}{equation.27}{}} +\newlabel{equation_c_4}{{28}{56}{}{equation.28}{}} +\newlabel{equation_c_5}{{29}{56}{}{equation.29}{}} +\newlabel{equation_computing_final}{{31}{57}{}{equation.31}{}} \acronymused{DSP} \@writefile{lof}{\contentsline {figure}{\numberline {45}{\ignorespaces Dependence of the total computing effort on the filter length $N$ and update rate $1/U$.}}{57}{}\protected@file@percent } -\newlabel{fig:fig_c_total.png}{{45}{57}{}{}{}} +\newlabel{fig:fig_c_total.png}{{45}{57}{}{figure.45}{}} \@setckpt{chapter_04}{ \setcounter{page}{58} \setcounter{equation}{31} diff --git a/chapter_05.aux b/chapter_05.aux index 577a42e..0d33bd5 100644 --- a/chapter_05.aux +++ b/chapter_05.aux @@ -10,15 +10,15 @@ \@writefile{lof}{\contentsline {figure}{\numberline {46}{\ignorespaces Desired signal, corrupted signal, reference noise signal and filter output of the complex \ac {ANR} use case, simulated on the \ac {DSP}}}{58}{}\protected@file@percent } \acronymused{ANR} \acronymused{DSP} -\newlabel{fig:fig_plot_1_dsp_complex.png}{{46}{58}{}{}{}} +\newlabel{fig:fig_plot_1_dsp_complex.png}{{46}{58}{}{figure.46}{}} \@writefile{lof}{\contentsline {figure}{\numberline {47}{\ignorespaces Error signal of the complex \ac {ANR} use case, simulated on the \ac {DSP}}}{59}{}\protected@file@percent } \acronymused{ANR} \acronymused{DSP} -\newlabel{fig:fig_plot_2_dsp_complex.png}{{47}{59}{}{}{}} +\newlabel{fig:fig_plot_2_dsp_complex.png}{{47}{59}{}{figure.47}{}} \@writefile{lof}{\contentsline {figure}{\numberline {48}{\ignorespaces Comparison of the high- and low-level simulation output.}}{59}{}\protected@file@percent } -\newlabel{fig:fig_high_low_comparison.png}{{48}{59}{}{}{}} +\newlabel{fig:fig_high_low_comparison.png}{{48}{59}{}{figure.48}{}} \@writefile{lof}{\contentsline {figure}{\numberline {49}{\ignorespaces Histogram of the error amplitude between the high- and low-level simulation output.}}{60}{}\protected@file@percent } -\newlabel{fig:fig_high_low_comparison_hist.png}{{49}{60}{}{}{}} +\newlabel{fig:fig_high_low_comparison_hist.png}{{49}{60}{}{figure.49}{}} \acronymused{ANR} \acronymused{DSP} \acronymused{SNR} @@ -32,12 +32,12 @@ \acronymused{ANR} \acronymused{CI} \@writefile{lof}{\contentsline {figure}{\numberline {50}{\ignorespaces Noise signals used to corrupt the desired signal in the computational efficiency evaluation}}{61}{}\protected@file@percent } -\newlabel{fig:fig_noise_signals.png}{{50}{61}{}{}{}} +\newlabel{fig:fig_noise_signals.png}{{50}{61}{}{figure.50}{}} \acronymused{ANR} \acronymused{SNR} \@writefile{lof}{\contentsline {figure}{\numberline {51}{\ignorespaces Simulation of the to be expected \ac {SNR}-Gain for different noise signals and filter lengths applied to the desired signal of a male speaker. The applied delay between the signals amounts 2ms. The graphs are smoothed by a third order savigol filter.}}{62}{}\protected@file@percent } \acronymused{SNR} -\newlabel{fig:fig_snr_comparison.png}{{51}{62}{}{}{}} +\newlabel{fig:fig_snr_comparison.png}{{51}{62}{}{figure.51}{}} \acronymused{SNR} \acronymused{SNR} \acronymused{SNR} @@ -49,13 +49,13 @@ \acronymused{ANR} \@writefile{toc}{\contentsline {subsection}{\numberline {5.3}Evaluation of the computational load for fixed implementation}{62}{}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {5.3.1}Full-Update implementation}{62}{}\protected@file@percent } -\newlabel{equation_computing_calculation}{{32}{63}{}{}{}} +\newlabel{equation_computing_calculation}{{32}{63}{}{equation.32}{}} \acronymused{PCM} \acronymused{DSP} \acronymused{DSP} -\newlabel{equation_cycle_budget}{{33}{63}{}{}{}} +\newlabel{equation_cycle_budget}{{33}{63}{}{equation.33}{}} \acronymused{DSP} -\newlabel{equation_load_calculation}{{34}{63}{}{}{}} +\newlabel{equation_load_calculation}{{34}{63}{}{equation.34}{}} \acronymused{ANR} \acronymused{SNR} \acronymused{DSP} @@ -65,14 +65,14 @@ \acronymused{DSP} \acronymused{SNR} \@writefile{lof}{\contentsline {figure}{\numberline {52}{\ignorespaces Relative performance of the SNR-Gain, the cycles per samples and the DSP load in regard of the update rate of the ANR algorithm. The baseline is the full update variant the complex usecase. The marked dots represent the results of the simulation for an explicit setup.}}{64}{}\protected@file@percent } -\newlabel{fig:fig_snr_reduced_update.png}{{52}{64}{}{}{}} +\newlabel{fig:fig_snr_reduced_update.png}{{52}{64}{}{figure.52}{}} \acronymused{SNR} \acronymused{DSP} \acronymused{SNR} \acronymused{SNR} \acronymused{DSP} -\newlabel{equation_computing_calculation}{{35}{64}{}{}{}} -\newlabel{equation_load_calculation}{{36}{64}{}{}{}} +\newlabel{equation_computing_calculation}{{35}{64}{}{equation.35}{}} +\newlabel{equation_load_calculation}{{36}{64}{}{equation.36}{}} \acronymused{DSP} \acronymused{SNR} \@writefile{toc}{\contentsline {subsection}{\numberline {5.4}Evaluation of the computational load for error driven implementation}{64}{}\protected@file@percent } diff --git a/chapter_05.tex b/chapter_05.tex index e80623e..c1fdc9c 100644 --- a/chapter_05.tex +++ b/chapter_05.tex @@ -27,10 +27,10 @@ To verify the general performance of the \ac{DSP}-implemented \ac{ANR} algorithm \end{figure} \noindent Figure \ref{fig:fig_plot_1_dsp_complex.png} and \ref{fig:fig_plot_2_dsp_complex.png} show the results of the complex \ac{ANR} use case, simulated on the \ac{DSP} - with a \ac{SNR}-Gain of 10.26 dB it performs equivalent sucessful as the one of the high-level implementation. Figure \ref{fig:fig_high_low_comparison.png} shows both outputs seperately and then together in one subfigure, together with the plotted error amplitude. Figure \ref{fig:fig_high_low_comparison_hist.png} feautres a histogram of the error amplitude between the high- and low-level implemenation, indicating the correct functionality of the \ac{DSP} implementation. The small deviations can be explained by the fact that the \ac{DSP} implementation is based on fixed-point arithmetic, which leads to a slightly different convergence behavior. Nevertheless, the results show that the \ac{DSP} implementation of the \ac{ANR} algorithm is able to achieve the same performance as the high-level implementation. The next step is of evaluate the performance of the \ac{DSP} implementation in terms of computational efficiency under different scenarios and non-synchrone signals. \subsection{Determination of the optimal filter length} -\noindent The main focus for evaluating the computational efficiency is the determination of the optimal filter length. To achieve this goal, different signal combinations, which are to be expected everyday situiations for a \ac{CI} patient, are considered. Again, a delay of 2 ms bewteen the corruption noise signal and the reference noise signal is applied, increasing the need for a longer filter. The desired signal of a male voice over speaker is now corrupted with 5 different noise signals, ruling out, that a certain combination of signals is not representative for the overall performance of the \ac{ANR} algorithm: +\noindent The main focus for evaluating the computational efficiency is the determination of the optimal filter length. To achieve this goal, different signal combinations, which are to be expected every day situiations for a \ac{CI} patient, are considered. Again, a delay of 2 ms bewteen the corruption noise signal and the reference noise signal is applied, increasing the need for a longer filter. The desired signal of a male voice is now corrupted with 5 different noise signals, ruling out, that a certain combination of signals is not representative for the overall performance of the \ac{ANR} algorithm: \begin{itemize} \item Breathing noise: Already used in the high-level implementation, this noise signal is a typical noise source for \ac{CI} patients, especially in quiet environments. It consists out of slowly rising and falling maxima. - \item Coughing noise: This noise signal is generated by coughing and consists out few, but long lasting maxima, showing similarities to a rectangular function. + \item Coughing noise: This noise signal is generated by coughing and consists out few, but long-lasting maxima, showing similarities to a rectangular function. \item Scratching noise: This noise signal is generated by scratching some material with finger nails, like the hair or clothes. It consists out of a high number of sharp peaks. \item Drinking Noise: This noise signal is generated by swallowing a liquid and consists out of a low number of sharp peaks, featuring long pauses between them. \item Chewing Noise: This noise signal is generated by consuming food and consists out of a high number of peaks of different amplitude. @@ -49,8 +49,8 @@ The vizualization of the noise signals is shown in Figure \ref{fig:fig_noise_sig \caption{Simulation of the to be expected \ac{SNR}-Gain for different noise signals and filter lengths applied to the desired signal of a male speaker. The applied delay between the signals amounts 2ms. The graphs are smoothed by a third order savigol filter.} \label{fig:fig_snr_comparison.png} \end{figure} -\noindent Figure \ref{fig:fig_snr_comparison.png} shows the expected \ac{SNR}-Gain for the different noise signals and filter lengths. The results shows, that a minimum filter length of about 32 taps is required, before (in any case) a significant rise in the \ac{SNR}-Gain can be observed - this is highly contrary to the synchrone intermediate high level simulation, where a filter length of only 16 taps provided sufficent noise reduction. This circumstance can be explained by the fact, that the corruption noise signal is now delayed to the reference noise signal, meaning, that the filter needs a certain length before it can be sufficently adapted. The results also show, that the \ac{SNR}-Gain is different for the different noise signals, indicating, that the noise signals have different characteristics, like the number of peaks, their frequency spectrum an their amplitude.\\ \\ -The mean \ac{SNR}-Gain of the different noise signals, also shown in Figure \ref{fig:fig_snr_comparison.png}, signals, that after reaching 95\% of the maximum \ac{SNR}-Gain, the \ac{SNR}-Gain increase is slowing down. This threshold is reached at a filter length of 45 taps. This means, that a filter length of 45 taps represents an optimal solution for a statisfying performance of the \ac{ANR} algorithm, while a further increase of the filter length does not lead to a significant increase of the \ac{SNR}-Gain in this setup. This is an important finding, as it allows to optimize the computational efficiency of the \ac{ANR} algorithm by choosing an appropriate filter length. +\noindent Figure \ref{fig:fig_snr_comparison.png} shows the expected \ac{SNR}-Gain for the different noise signals and filter lengths. The results show, that a minimum filter length of about 32 taps is required, before (in any case) a significant rise in the \ac{SNR}-Gain can be observed - this is highly contrary to the synchrone intermediate high level simulation, where a filter length of only 16 taps provided sufficent noise reduction. This circumstance can be explained by the fact, that the corruption noise signal is now delayed to the reference noise signal, meaning, that the filter needs a certain length before it can be sufficently adapted. The results also show, that the \ac{SNR}-Gain is different for the different noise signals, indicating, that the noise signals have different characteristics, like the number of peaks, their frequency spectrum and their amplitude.\\ \\ +The mean \ac{SNR}-Gain of the different noise signals, also shown in Figure \ref{fig:fig_snr_comparison.png}, signals, that after reaching 95\% of the maximum \ac{SNR}-Gain, the \ac{SNR}-Gain increase is slowing down. This threshold is reached at a filter length of 45 taps. This means, that a filter length of 45 taps represents an optimal solution for a statisfying performance of the \ac{ANR} algorithm, while a further increase of the filter length does not lead to a significant increase of the \ac{SNR}-Gain in this setup. This is an important finding, as it allows optimizing the computational efficiency of the \ac{ANR} algorithm by choosing an appropriate filter length. \subsection{Evaluation of the computational load for fixed implementation} \subsubsection{Full-Update implementation} \noindent Equation \ref{equation_computing_final} can now be utilized to calculate the needed cycles for the calculation of one sample of the filter output, using a filter length of 45 taps and an update of the filter coefficients every cycle. The needed cycles are calculated as follows: @@ -69,11 +69,11 @@ As already mentioned in the previous chapters, the sampling rate of the audio da Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{357 \text{ cycles}}{800 \text{ cycles}} = 44.6 \% \end{equation} \noindent The results, calculated in Equation \ref{equation_computing_calculation} to \ref{equation_load_calculation} can be summarized as follows:\\ \\ -With the optimal filter length of 45 taps and an update rate of the filter coefficients every cycle, the \ac{ANR} algorithm is able to achieve a \ac{SNR}-Gain of about 11.54 dB, averaged over different signal/noise combinations. Under this circumstances, the computational load of the \ac{DSP} core amounts about 45\%, which means that 55\% of the time, which a new sample takes to arrive, it can be halted, and therefore, the overall power consumption can be reduced.\\ \\ -The initial signal/noise combination of a male speaker disturbed by a breathing noise, which is used for the verification of the \ac{DSP} implementation, delivers with 45 filter coefficients an \ac{SNR}-Gain of about 9.47 dB, which will be again used as a benchmark for the coming evaluations. +With the optimal filter length of 45 taps and an update rate of the filter coefficients every cycle, the \ac{ANR} algorithm is able to achieve a \ac{SNR}-Gain of about 11.54 dB, averaged over different signal/noise combinations. Under these circumstances, the computational load of the \ac{DSP} core amounts about 45\%, which means that 55\% of the time, which a new sample takes to arrive, it can be halted, and therefore, the overall power consumption can be reduced.\\ \\ +The initial signal/noise combination of a male speaker disturbed by a breathing noise, which is used for the verification of the \ac{DSP} implementation, delivers with 45 filter coefficients a \ac{SNR}-Gain of about 9.47 dB, which will be again used as a benchmark for the coming evaluations. \subsubsection{Reduced-update implementation} -The most straight-forward method to further reduce the computing effort for the \ac{DSP} core is to reduce the update frequency of the filter coeffcients. This means, that for every sample, the new filter coefficients are calculated, but not written to the into the Filter Line, meaning that the filter, calculated for the previous sample, is applied to the actual sample. Depending on the acoustic situation, the savings in computing power will most likely lead to a degredation of the noise reduction quality, depending if the current situation is highly dynamic (and therefore would require a frequent update of the filter coefficients) or is rather static. Changing the update frequency, changes the denominator in Equation \ref{equation_c_5} and therefore in Equation \ref{equation_computing_final}.\\ \\ -As already mentioned, the reduction of the update rate is evaluated for the signal/noise combination of a male speaker disturbed by a breathing noise. Therefore the \ac{SNR}-Gain of 9.47 dB with 45 filter coefficients represent 100\% achievable noise reduction with a maximum of 357 cycles. +The most straight-forward method to further reduce the computing effort for the \ac{DSP} core is to reduce the update frequency of the filter coeffcients. This means, that for every sample, the new filter coefficients are calculated, but not written to the into the Filter Line, meaning that the filter, calculated for the previous sample, is applied to the actual sample. Depending on the acoustic situation, the savings in computing power will most likely lead to a degredation of the noise reduction quality, depending on if the current situation is highly dynamic (and therefore would require a frequent update of the filter coefficients) or is rather static. Changing the update frequency, changes the denominator in Equation \ref{equation_c_5} and therefore in Equation \ref{equation_computing_final}.\\ \\ +As already mentioned, the reduction of the update rate is evaluated for the signal/noise combination of a male speaker disturbed by a breathing noise. Therefore, the \ac{SNR}-Gain of 9.47 dB with 45 filter coefficients represent 100\% achievable noise reduction with a maximum of 357 cycles. \begin{figure}[H] \centering \includegraphics[width=1.0\linewidth]{Bilder/fig_snr_reduced_update.png} @@ -90,7 +90,7 @@ The maximum offset bewteen the two graphs can be cound found at an updat rate of \label{equation_load_calculation} Load_{DSP} = \frac{C_{total}}{C_{budget}} = \frac{188 \text{ cycles}}{800 \text{ cycles}} = 23.5 \% \end{equation} -The interpreation of this results leads to the coclusion, that the most cost-effective way to reduce the load of the \ac{DSP} would be to reduce the update rate of the filter coefficients to 0.39. This action nearly halfs the processor load, while only reducing the \ac{SNR}-Gain by rougly 31 \% to 6.40 dB. The next step will be to determine the possibilites of a dynamic reduction of the update frequency to further improve the cost-value ratio of our implemenation. +The interpreation of these results leads to the coclusion, that the most cost-effective way to reduce the load of the \ac{DSP} would be to reduce the update rate of the filter coefficients to 0.39. This action nearly halfs the processor load, while only reducing the \ac{SNR}-Gain by rougly 31 \% to 6.40 dB. The next step will be to determine the possibilites of a dynamic reduction of the update frequency to further improve the cost-value ratio of our implemenation. \subsection{Evaluation of the computational load for error driven implementation} -The error-driven implemenation approach focuses on an error metric, over which the decision for an coefficient update is made. +The error-driven implemenation approach focuses on an error metric, over which the decision for a coefficient update is made. \subsection{Summary of the performance evaluation} \ No newline at end of file