Files
DSP_Simulation/testcode/Release/chesswork/main-520f39.sfg
2026-01-27 11:17:03 +01:00

196 lines
7.2 KiB
Plaintext

// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Tue Jan 20 12:04:50 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
/***
!! volatile int *cyclic_add_man(volatile int *, int, volatile int *, int)
F_Z14cyclic_add_manPViiS0_i : user_defined, called {
fnm : "cyclic_add_man" 'volatile int *cyclic_add_man(volatile int *, int, volatile int *, int)';
arg : ( dmaddr_:i dmaddr_:r dmaddr_:i int32_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] A[1] RA[0] A[2] RA[1] );
vac : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : _Z14cyclic_add_manPViiS0_i typ=uint20_ bnd=e stl=PM tref=__P__sint_____P__sint___sint___P__sint___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __rd___sp typ=dmaddr_ bnd=m
37 : __ct_0 typ=uint1_ val=0f bnd=m
38 : __la typ=dmaddr_ bnd=p tref=dmaddr___
40 : ptr typ=dmaddr_ bnd=p tref=__P__sint__
41 : i_pp typ=int32_ bnd=p tref=__sint__
42 : ptr_start typ=dmaddr_ bnd=p tref=__P__sint__
43 : buffer_len typ=int32_ bnd=p tref=__sint__
47 : p_ptr typ=dmaddr_ bnd=m tref=__P__sint__
50 : __ct_0 typ=int32_ val=0f bnd=m
52 : __tmp typ=int32_ bnd=m
53 : __tmp typ=bool bnd=m
78 : __cv typ=uint16_ bnd=m
83 : __ct_2 typ=int32_ val=2f bnd=m
86 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
109 : __tmp typ=bool bnd=m
114 : __ct_0S0 typ=int18_ val=0S0 bnd=m
115 : __ct_4 typ=int18_ val=4f bnd=m
118 : __ct_0s0 typ=int18_ val=0s0 bnd=m
122 : __tmp typ=uint3_ bnd=m
127 : __ct_2 typ=uint2_ val=2f bnd=m
137 : __tmp typ=uint3_ bnd=m
141 : __tmp typ=int18_ bnd=m
150 : __either typ=bool bnd=m
151 : __trgt typ=int10_ val=0j bnd=m
152 : __trgt typ=int10_ val=0j bnd=m
153 : __trgt typ=int10_ val=0j bnd=m
154 : __trgt typ=int10_ val=0j bnd=m
155 : __trgt typ=uint16_ val=0j bnd=m
156 : __vcnt typ=uint16_ bnd=m
]
F_Z14cyclic_add_manPViiS0_i {
#206 off=0
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__ct_0.35 var=37) const () <59>;
(__la.37 var=38 stl=LR off=0) inp () <61>;
(__la.38 var=38) deassign (__la.37) <62>;
(ptr.41 var=40 stl=A off=1) inp () <65>;
(ptr.42 var=40) deassign (ptr.41) <66>;
(i_pp.44 var=41 stl=RA off=0) inp () <68>;
(i_pp.45 var=41) deassign (i_pp.44) <69>;
(ptr_start.47 var=42 stl=A off=2) inp () <71>;
(ptr_start.48 var=42) deassign (ptr_start.47) <72>;
(buffer_len.50 var=43 stl=RA off=1) inp () <74>;
(buffer_len.51 var=43) deassign (buffer_len.50) <75>;
(__rd___sp.53 var=36) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.213 __sp.32) <81>;
(__ct_0.64 var=50) const () <88>;
(__tmp.66 var=52) __sint_abs___sint (i_pp.45) <90>;
(__rt.213 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.297) <264>;
(__ct_0S0.297 var=114) const () <381>;
(__tmp.304 var=122) uint3__cmp_int72__int72_ (__tmp.66 __ct_0.64) <394>;
(__tmp.329 var=53) bool_nplus_uint3_ (__tmp.304) <450>;
(__trgt.336 var=153) const () <468>;
() void_jump_bool_int10_ (__tmp.329 __trgt.336) <469>;
(__either.337 var=150) undefined () <470>;
if {
{
() if_expr (__either.337) <108>;
() chess_frequent_else () <109>;
() chess_rear_then () <471>;
} #5
{
(__trgt.338 var=154) const () <472>;
() void_jump_int10_ (__trgt.338) <473>;
} #18 off=7
{
#154 off=1
(__cv.196 var=78) uint16__uint16____sint (__tmp.66) <234>;
(__ct_2.199 var=83) const () <238>;
(__rt.257 var=86) __Pvoid__pl___Pvoid_int18_ (ptr_start.48 __tmp.310) <320>;
(__ct_4.298 var=115) const () <383>;
(__ct_2.309 var=127) const () <402>;
(__tmp.310 var=141) int72__shift_int72__int72__uint2_ (buffer_len.51 __ct_2.199 __ct_2.309) <403>;
(__trgt.333 var=151) const () <463>;
(__trgt.335 var=152) const () <466>;
(__trgt.339 var=155) const () <474>;
() void_doloop_uint16__uint16_ (__cv.196 __trgt.339) <475>;
(__vcnt.340 var=156) undefined () <476>;
for {
{
(p_ptr.92 var=47) entry (p_ptr.146 ptr.42) <118>;
} #8
{
#223 off=2
(__rt.235 var=86) __Pvoid__pl___Pvoid_int18_ (p_ptr.92 __ct_4.298) <292>;
(__tmp.319 var=137) uint3__cmp_int72__int72_ (__rt.235 __rt.257) <418>;
(__tmp.330 var=109) bool_neg_uint3_ (__tmp.319) <451>;
() void_jump_bool_int10_ (__tmp.330 __trgt.333) <464>;
(__either.334 var=150) undefined () <465>;
if {
{
() if_expr (__either.334) <150>;
} #12
{
} #14 off=4
{
() void_jump_int10_ (__trgt.335) <467>;
} #13 off=3
{
(p_ptr.124 var=47) merge (__rt.235 ptr_start.48) <151>;
} #15
} #11
} #9
{
() for_count (__vcnt.340) <157>;
(p_ptr.146 var=47 p_ptr.147 var=47) exit (p_ptr.124) <166>;
} #17
} #7 rng=[1,65535]
} #6
{
(p_ptr.162 var=47) merge (ptr.42 p_ptr.147) <174>;
} #19
} #4
#21 off=8 nxt=-2
(__rd___sp.165 var=36) rd_res_reg (__R_SP.24 __sp.58) <177>;
(__R_SP.169 var=26 __sp.170 var=34) wr_res_reg (__rt.284 __sp.58) <181>;
() void_ret_dmaddr_ (__la.38) <182>;
(p_ptr.171 var=47 stl=A off=0) assign (p_ptr.162) <183>;
() out (p_ptr.171) <184>;
() sink (__sp.170) <190>;
() sink (__ct_0.35) <192>;
(__rt.284 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.165 __ct_0s0.301) <356>;
(__ct_0s0.301 var=118) const () <389>;
} #0
0 : 'main.c';
----------
0 : (0,27:0,0);
4 : (0,29:8,3);
6 : (0,29:8,4);
7 : (0,29:8,4);
9 : (0,29:42,4);
11 : (0,31:16,7);
13 : (0,31:52,8);
14 : (0,31:16,11);
18 : (0,29:8,18);
21 : (0,35:8,21);
206 : (0,29:8,3);
223 : (0,31:26,7);
----------
77 : (0,27:14,0);
81 : (0,27:14,0);
88 : (0,29:19,0);
90 : (0,29:8,3);
108 : (0,29:8,3);
118 : (0,29:8,4);
150 : (0,31:16,7);
151 : (0,31:16,13);
157 : (0,29:8,16);
166 : (0,29:8,16);
174 : (0,29:8,20);
177 : (0,35:8,0);
181 : (0,35:8,21);
182 : (0,35:8,21);
183 : (0,35:15,0);
238 : (0,31:41,0);
264 : (0,27:14,0);
292 : (0,30:22,5);
320 : (0,31:39,7);
356 : (0,35:8,0);
381 : (0,27:14,0);
383 : (0,30:22,0);
389 : (0,35:8,0);
394 : (0,29:8,3);
402 : (0,31:41,0);
403 : (0,31:41,7);
418 : (0,31:26,7);
450 : (0,29:8,3);
451 : (0,31:26,7);
464 : (0,31:16,7);
469 : (0,29:8,3);
475 : (0,29:8,16);