// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:29:46 2026 // Copyright 2014-2025 Synopsys, Inc. All rights reserved. // C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32 /*** !! int sig_calc_weight(SingleSignalPath *, int) F_Z15sig_calc_weightP16SingleSignalPathi : user_defined, called { fnm : "sig_calc_weight" 'int sig_calc_weight(SingleSignalPath *, int)'; arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i ); loc : ( LR[0] RA[0] A[0] RA[1] ); vac : ( srIM[0] ); frm : ( ); } **** ***/ [ 0 : _Z15sig_calc_weightP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___3 11 : __M_WDMA typ=int32_ bnd=d stl=WDMA 26 : __R_SP typ=dmaddr_ bnd=d stl=SP 34 : __sp typ=dmaddr_ bnd=b stl=SP 36 : __extDM_SingleSignalPath_weight_actived typ=int8_ bnd=b stl=DM 38 : __extDM_SingleSignalPath_weight typ=int8_ bnd=b stl=DM 39 : __rd___sp typ=dmaddr_ bnd=m 40 : __ct_0 typ=uint1_ val=0f bnd=m 41 : __la typ=dmaddr_ bnd=p tref=dmaddr___ 42 : __rt typ=int32_ bnd=p tref=__sint__ 43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__ 44 : x typ=int32_ bnd=p tref=__sint__ 48 : acc typ=int72_ bnd=m lscp=144 tref=accum_t__ 52 : __fch___extDM_SingleSignalPath_weight_actived typ=int32_ bnd=m 53 : __ct_0 typ=int32_ val=0f bnd=m 55 : __tmp typ=bool bnd=m 59 : __fch___extDM_SingleSignalPath_weight typ=int32_ bnd=m 77 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__ 100 : __ct_0S0 typ=int18_ val=0S0 bnd=m 101 : __ct_132 typ=int18_ val=132f bnd=m 104 : __ct_136 typ=int18_ val=136f bnd=m 107 : __ct_0s0 typ=int18_ val=0s0 bnd=m 111 : __tmp typ=uint3_ bnd=m 121 : __either typ=bool bnd=m 122 : __trgt typ=int10_ val=0j bnd=m 123 : __trgt typ=int10_ val=0j bnd=m ] F_Z15sig_calc_weightP16SingleSignalPathi { #194 off=0 (__M_WDMA.9 var=11) st_def () <18>; (__R_SP.24 var=26) st_def () <48>; (__sp.32 var=34) source () <56>; (__extDM_SingleSignalPath_weight_actived.34 var=36) source () <58>; (__extDM_SingleSignalPath_weight.36 var=38) source () <60>; (__ct_0.38 var=40) const () <62>; (__la.40 var=41 stl=LR off=0) inp () <64>; (__la.41 var=41) deassign (__la.40) <65>; (signal.44 var=43 stl=A off=0) inp () <68>; (signal.45 var=43) deassign (signal.44) <69>; (x.47 var=44 stl=RA off=1) inp () <71>; (x.48 var=44) deassign (x.47) <72>; (__rd___sp.50 var=39) rd_res_reg (__R_SP.24 __sp.32) <74>; (__R_SP.54 var=26 __sp.55 var=34) wr_res_reg (__rt.133 __sp.32) <78>; (__fch___extDM_SingleSignalPath_weight_actived.60 var=52) load (__M_WDMA.9 __rt.155 __extDM_SingleSignalPath_weight_actived.34) <84>; (__ct_0.61 var=53) const () <85>; (__rt.133 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.50 __ct_0S0.212) <200>; (__rt.155 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_132.213) <228>; (__ct_0S0.212 var=100) const () <309>; (__ct_132.213 var=101) const () <311>; (__tmp.222 var=111) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_weight_actived.60 __ct_0.61) <328>; (__tmp.223 var=55) bool_equal_uint3_ (__tmp.222) <329>; (__trgt.231 var=122) const () <363>; () void_jump_bool_int10_ (__tmp.223 __trgt.231) <364>; (__either.232 var=121) undefined () <365>; if { { () if_expr (__either.232) <103>; } #5 { } #6 off=2 { (__fch___extDM_SingleSignalPath_weight.83 var=59) load (__M_WDMA.9 __rt.177 __extDM_SingleSignalPath_weight.36) <108>; (__rt.85 var=42) __sint_rnd_saturate_accum_t (acc.115) <110>; (acc.115 var=48) int72__multss_int32__int32__uint1_ (x.48 __fch___extDM_SingleSignalPath_weight.83 __ct_0.38) <161>; (__rt.177 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_136.216) <256>; (__ct_136.216 var=104) const () <317>; (__trgt.233 var=123) const () <366>; () void_jump_int10_ (__trgt.233) <367>; } #144 off=1 { (__rt.86 var=42) merge (x.48 __rt.85) <111>; } #8 } #4 #10 off=3 nxt=-2 (__rd___sp.88 var=39) rd_res_reg (__R_SP.24 __sp.55) <113>; (__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.199 __sp.55) <117>; () void_ret_dmaddr_ (__la.41) <118>; (__rt.94 var=42 stl=RA off=0) assign (__rt.86) <119>; () out (__rt.94) <120>; () sink (__sp.93) <126>; () sink (__ct_0.38) <131>; (__rt.199 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.219) <284>; (__ct_0s0.219 var=107) const () <323>; } #0 0 : 'signal_processing\\signal_path.c'; ---------- 0 : (0,211:0,0); 4 : (0,212:4,1); 6 : (0,212:37,2); 10 : (0,217:4,11); 144 : (0,217:11,7); 194 : (0,212:31,1); ---------- 74 : (0,211:4,0); 78 : (0,211:4,0); 84 : (0,212:14,1); 85 : (0,212:34,0); 103 : (0,212:4,1); 108 : (0,215:38,6); 110 : (0,217:11,7); 111 : (0,212:4,10); 113 : (0,217:4,0); 117 : (0,217:4,11); 118 : (0,217:4,11); 119 : (0,217:4,0); 161 : (0,215:18,6); 200 : (0,211:4,0); 228 : (0,212:14,1); 256 : (0,215:38,6); 284 : (0,217:4,0); 309 : (0,211:4,0); 311 : (0,212:14,0); 317 : (0,215:38,0); 323 : (0,217:4,0); 328 : (0,212:31,1); 329 : (0,212:31,1); 364 : (0,212:4,1);