// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026 // Copyright 2014-2025 Synopsys, Inc. All rights reserved. // C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32 /*** !! int main() F_main : user_defined, called { fnm : "main" 'int main()'; arg : ( dmaddr_:i int32_:r ); loc : ( LR[0] RA[0] ); vac : ( srIM[0] ); frm : ( l=88 b=8 ); } **** !! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int) F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called { fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)'; arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i ); loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] ); vac : ( srIM[0] ); } !! extern FILE *fopen(const char *, const char *) Ffopen : user_defined, called { fnm : "fopen" 'FILE *fopen(const char *, const char *)'; arg : ( dmaddr_:i dmaddr_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] A[0] A[1] A[2] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int feof(FILE *) Ffeof : user_defined, called { fnm : "feof" 'int feof(FILE *)'; arg : ( dmaddr_:i int32_:r dmaddr_:i ); loc : ( LR[0] RA[0] A[0] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int fscanf(FILE *, const char *, ...) Ffscanf : user_defined, called, varargs { fnm : "fscanf" 'int fscanf(FILE *, const char *, ...)'; arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] RA[0] A[0] A[1] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *) F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called { fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)'; arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i ); loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] ); vac : ( srIM[0] ); } !! extern int fprintf(FILE *, const char *, ...) Ffprintf : user_defined, called, varargs { fnm : "fprintf" 'int fprintf(FILE *, const char *, ...)'; arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] RA[0] A[0] A[1] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int fclose(FILE *) Ffclose : user_defined, called { fnm : "fclose" 'int fclose(FILE *)'; arg : ( dmaddr_:i int32_:r dmaddr_:i ); loc : ( LR[0] RA[0] A[0] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } ***/ [ 0 : _main typ=uint20_ bnd=e stl=PM tref=__sint____ 8 : __M_SDMB typ=int16_ bnd=d stl=SDMB 11 : __M_WDMA typ=int32_ bnd=d stl=WDMA 14 : __M_LDMA typ=int64_ bnd=d stl=LDMA 26 : __R_SP typ=dmaddr_ bnd=d stl=SP 29 : __vola typ=uint20_ bnd=b stl=PM 32 : __extDM typ=int8_ bnd=b stl=DM 33 : __extPM typ=uint20_ bnd=b stl=PM 34 : __sp typ=dmaddr_ bnd=b stl=SP 35 : b0 typ=int8_ val=8t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA 36 : b1 typ=int8_ val=48t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA 37 : _ZL17c_sensor_signal_t typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA 38 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM 39 : _ZL19acc_sensor_signal_t typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA 40 : _ZL13__str45bf45e5 typ=int8_ bnd=i sz=46 algn=1 stl=DMA tref=__A46__cchar_DMA 41 : _ZL13__str00f02b8f typ=int8_ bnd=i sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA 42 : _ZL13__str1747fd53 typ=int8_ bnd=i sz=42 algn=1 stl=DMA tref=__A42__cchar_DMA 43 : _ZL13__str31c2d68e typ=int8_ bnd=i sz=53 algn=1 stl=DMA tref=__A53__cchar_DMA 44 : _ZL13__str00f52cca typ=int8_ bnd=i sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA 45 : _ZL13__str41232700 typ=int8_ bnd=i sz=3 algn=1 stl=DMA tref=__A3__cchar_DMA 46 : d0 typ=int8_ val=88t0 bnd=a sz=4 algn=4 stl=DMA tref=__sint_DMA 47 : d1 typ=int8_ val=92t0 bnd=a sz=4 algn=4 stl=DMA tref=__sint_DMA 48 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB 49 : __extDM_int16_ typ=int8_ bnd=b stl=DM 50 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB 51 : _ZL13__str2eb09b76 typ=int8_ bnd=i sz=4 algn=1 stl=DMA tref=__A4__cchar_DMA 52 : __extDM_void typ=int8_ bnd=b stl=DM 53 : __extPM_void typ=uint20_ bnd=b stl=PM 54 : __extDM_int64_ typ=int8_ bnd=b stl=DM 55 : __extDM_int8_ typ=int8_ bnd=b stl=DM 56 : __extPM_FILE typ=uint20_ bnd=b stl=PM 57 : __extDM_int32_ typ=int8_ bnd=b stl=DM 58 : __rd___sp typ=dmaddr_ bnd=m 59 : __ptr_c_sensor_signal_t typ=dmaddr_ bnd=m 60 : __ptr_c_sensor_signal_t typ=dmaddr_ val=0a bnd=m adro=37 61 : __ptr_acc_sensor_signal_t typ=dmaddr_ bnd=m 62 : __ptr_acc_sensor_signal_t typ=dmaddr_ val=0a bnd=m adro=39 63 : __ptr___str45bf45e5 typ=dmaddr_ bnd=m 64 : __ptr___str45bf45e5 typ=dmaddr_ val=0a bnd=m adro=40 65 : __ptr___str00f02b8f typ=dmaddr_ bnd=m 66 : __ptr___str00f02b8f typ=dmaddr_ val=0a bnd=m adro=41 67 : __ptr___str1747fd53 typ=dmaddr_ bnd=m 68 : __ptr___str1747fd53 typ=dmaddr_ val=0a bnd=m adro=42 69 : __ptr___str31c2d68e typ=dmaddr_ bnd=m 70 : __ptr___str31c2d68e typ=dmaddr_ val=0a bnd=m adro=43 71 : __ptr___str00f52cca typ=dmaddr_ bnd=m 72 : __ptr___str00f52cca typ=dmaddr_ val=0a bnd=m adro=44 73 : __ptr___str41232700 typ=dmaddr_ bnd=m 74 : __ptr___str41232700 typ=dmaddr_ val=0a bnd=m adro=45 76 : __ct_8388608 typ=dmaddr_ val=8388608f bnd=m 77 : __ptr_output_port typ=dmaddr_ bnd=m 78 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m 79 : __ptr___str2eb09b76 typ=dmaddr_ bnd=m 80 : __ptr___str2eb09b76 typ=dmaddr_ val=0a bnd=m adro=51 81 : __ct_0 typ=uint1_ val=0f bnd=m 82 : __la typ=dmaddr_ bnd=p tref=dmaddr___ 83 : __rt typ=int32_ bnd=p tref=__sint__ 87 : __ptr_b0 typ=dmaddr_ bnd=m 91 : __ptr_b1 typ=dmaddr_ bnd=m 95 : __ptr_d0 typ=dmaddr_ bnd=m 99 : __ptr_d1 typ=dmaddr_ bnd=m 103 : fp1 typ=dmaddr_ bnd=m tref=__PFILE__ 104 : fp2 typ=dmaddr_ bnd=m tref=__PFILE__ 105 : fp3 typ=dmaddr_ bnd=m tref=__PFILE__ 110 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m 112 : __ct_0 typ=int32_ val=0f bnd=m 115 : __ct_0 typ=uint40_ val=0f bnd=m 160 : __ct_2 typ=int32_ val=2f bnd=m 161 : __ct typ=int32_ bnd=m 163 : __ct typ=int32_ bnd=m 164 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m 165 : __ct typ=int64_ bnd=m 167 : __ct typ=int64_ bnd=m 168 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m 169 : __ct typ=int64_ bnd=m 170 : __ct_64 typ=int32_ val=64f bnd=m 171 : __ct typ=int32_ bnd=m 172 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m 174 : __link typ=dmaddr_ bnd=m 175 : fopen typ=dmaddr_ val=0r bnd=m 177 : __link typ=dmaddr_ bnd=m 178 : __tmp typ=dmaddr_ bnd=m 181 : __link typ=dmaddr_ bnd=m 182 : __tmp typ=dmaddr_ bnd=m 185 : __link typ=dmaddr_ bnd=m 186 : __tmp typ=dmaddr_ bnd=m 187 : feof typ=dmaddr_ val=0r bnd=m 189 : __link typ=dmaddr_ bnd=m 190 : __tmp typ=int32_ bnd=m 198 : __link typ=dmaddr_ bnd=m 199 : __tmp typ=int32_ bnd=m 202 : __tmp typ=bool bnd=m 203 : __tmp typ=bool bnd=m 210 : fscanf typ=dmaddr_ val=0r bnd=m 212 : __link typ=dmaddr_ bnd=m 213 : __tmp typ=int32_ bnd=m 216 : __link typ=dmaddr_ bnd=m 217 : __tmp typ=int32_ bnd=m 218 : __fch_d0 typ=int32_ bnd=m 219 : __tmp typ=int16_ bnd=m 224 : __fch_d1 typ=int32_ bnd=m 225 : __tmp typ=int16_ bnd=m 241 : __tmp typ=dmaddr_ bnd=m 244 : __tmp typ=dmaddr_ bnd=m 245 : _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=dmaddr_ val=0r bnd=m 247 : __link typ=dmaddr_ bnd=m 257 : __fch__ZL11output_port typ=int16_ bnd=m 258 : __fch__ZL11output_port typ=int32_ bnd=m 259 : fprintf typ=dmaddr_ val=0r bnd=m 261 : __link typ=dmaddr_ bnd=m 262 : __tmp typ=int32_ bnd=m 271 : __link typ=dmaddr_ bnd=m 272 : __tmp typ=int32_ bnd=m 280 : __link typ=dmaddr_ bnd=m 281 : __tmp typ=int32_ bnd=m 284 : __tmp typ=bool bnd=m 285 : __tmp typ=bool bnd=m 287 : fclose typ=dmaddr_ val=0r bnd=m 289 : __link typ=dmaddr_ bnd=m 290 : __tmp typ=int32_ bnd=m 293 : __link typ=dmaddr_ bnd=m 294 : __tmp typ=int32_ bnd=m 297 : __link typ=dmaddr_ bnd=m 298 : __tmp typ=int32_ bnd=m 333 : __shv___ptr_input_port typ=dmaddr_ bnd=m 357 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__ 382 : __tmp typ=bool bnd=m 398 : __ct_m88S0 typ=int18_ val=-96S0 bnd=m 399 : __ct_88s0 typ=int18_ val=96s0 bnd=m 400 : __ct_0t0 typ=int18_ val=8t0 bnd=m 401 : __ct_40t0 typ=int18_ val=48t0 bnd=m 404 : __ct_80t0 typ=int18_ val=88t0 bnd=m 407 : __ct_84t0 typ=int18_ val=92t0 bnd=m 410 : __ct_2 typ=int18_ val=2f bnd=m 412 : __ct_8t0 typ=int18_ val=16t0 bnd=m 415 : __ct_16t0 typ=int18_ val=24t0 bnd=m 418 : __ct_24t0 typ=int18_ val=32t0 bnd=m 421 : __ct_32t0 typ=int18_ val=40t0 bnd=m 424 : __ct_48t0 typ=int18_ val=56t0 bnd=m 427 : __ct_56t0 typ=int18_ val=64t0 bnd=m 430 : __ct_64t0 typ=int18_ val=72t0 bnd=m 433 : __ct_72t0 typ=int18_ val=80t0 bnd=m 439 : __tmp typ=uint3_ bnd=m 450 : __true typ=bool val=1f bnd=m 451 : __false typ=bool val=0f bnd=m 452 : __either typ=bool bnd=m 453 : __trgt typ=int10_ val=0j bnd=m 454 : __trgt typ=int10_ val=0j bnd=m 455 : __trgt typ=int10_ val=0j bnd=m 456 : __trgt typ=int10_ val=0j bnd=m 457 : __trgt typ=int10_ val=0j bnd=m ] F_main { #368 off=0 (__M_SDMB.6 var=8) st_def () <12>; (__M_WDMA.9 var=11) st_def () <18>; (__R_SP.24 var=26) st_def () <48>; (__vola.27 var=29) source () <51>; (__extDM.30 var=32) source () <54>; (__extPM.31 var=33) source () <55>; (__sp.32 var=34) source () <56>; (b0.33 var=35) source () <57>; (b1.34 var=36) source () <58>; (_ZL17c_sensor_signal_t.35 var=37) source () <59>; (__extDM_SingleSignalPath.36 var=38) source () <60>; (_ZL19acc_sensor_signal_t.37 var=39) source () <61>; (d0.44 var=46) source () <68>; (d1.45 var=47) source () <69>; (_ZL10input_port.46 var=48) source () <70>; (__extDM_int16_.47 var=49) source () <71>; (_ZL11output_port.48 var=50) source () <72>; (__extDM_void.50 var=52) source () <74>; (__extPM_void.51 var=53) source () <75>; (__extDM_int64_.52 var=54) source () <76>; (__extDM_int8_.53 var=55) source () <77>; (__extPM_FILE.54 var=56) source () <78>; (__extDM_int32_.55 var=57) source () <79>; (__ptr_c_sensor_signal_t.57 var=60) const () <81>; (__ptr_acc_sensor_signal_t.59 var=62) const () <83>; (__ct_0.81 var=81) const () <105>; (__la.83 var=82 stl=LR off=0) inp () <107>; (__la.84 var=82) deassign (__la.83) <108>; (__rd___sp.87 var=58) rd_res_reg (__R_SP.24 __sp.32) <111>; (__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.1692 __sp.32) <115>; (__rd___sp.93 var=58) rd_res_reg (__R_SP.24 __sp.92) <117>; (__ct_4604930618986332160.120 var=110) const () <144>; (__M_LDMA.125 var=14 b0.126 var=35) store (__ct_4604930618986332160.120 __rt.1714 b0.33) <149>; (__ct_0.127 var=115) const () <150>; (__M_LDMA.132 var=14 b0.133 var=35) store (__ct_0.127 __rt.1878 b0.126) <155>; (__M_LDMA.139 var=14 b0.140 var=35) store (__ct_0.127 __rt.1900 b0.133) <161>; (__M_LDMA.146 var=14 b0.147 var=35) store (__ct_0.127 __rt.1922 b0.140) <167>; (__M_LDMA.153 var=14 b0.154 var=35) store (__ct_0.127 __rt.1944 b0.147) <173>; (__M_LDMA.160 var=14 b1.161 var=36) store (__ct_4604930618986332160.120 __rt.1736 b1.34) <179>; (__M_LDMA.167 var=14 b1.168 var=36) store (__ct_0.127 __rt.1966 b1.161) <185>; (__M_LDMA.174 var=14 b1.175 var=36) store (__ct_0.127 __rt.1988 b1.168) <191>; (__M_LDMA.181 var=14 b1.182 var=36) store (__ct_0.127 __rt.2010 b1.175) <197>; (__M_LDMA.188 var=14 b1.189 var=36) store (__ct_0.127 __rt.2032 b1.182) <203>; (__ct_2.194 var=160) const () <208>; (__ct_4606281698874543309.200 var=164) const () <214>; (__ct_4576918229304087675.206 var=168) const () <220>; (__ct_64.209 var=170) const () <223>; (_Z4initP16SingleSignalPathS0_PdS1_iidddi.212 var=172) const () <226>; (__link.214 var=174) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.212) <228>; (__rt.1692 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_m88S0.2045) <1439>; (__rt.1714 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_0t0.2047) <1467>; (__rt.1736 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_40t0.2048) <1495>; (__rt.1878 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_8t0.2059) <1679>; (__rt.1900 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_16t0.2062) <1707>; (__rt.1922 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_24t0.2065) <1735>; (__rt.1944 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_32t0.2068) <1763>; (__rt.1966 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_48t0.2071) <1791>; (__rt.1988 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_56t0.2074) <1819>; (__rt.2010 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_64t0.2077) <1847>; (__rt.2032 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_72t0.2080) <1875>; (__ct_m88S0.2045 var=398) const () <1935>; (__ct_0t0.2047 var=400) const () <1939>; (__ct_40t0.2048 var=401) const () <1941>; (__ct_8t0.2059 var=412) const () <1963>; (__ct_16t0.2062 var=415) const () <1969>; (__ct_24t0.2065 var=418) const () <1975>; (__ct_32t0.2068 var=421) const () <1981>; (__ct_48t0.2071 var=424) const () <1987>; (__ct_56t0.2074 var=427) const () <1993>; (__ct_64t0.2077 var=430) const () <1999>; (__ct_72t0.2080 var=433) const () <2005>; call { (__ptr_c_sensor_signal_t.190 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <204>; (__ptr_acc_sensor_signal_t.191 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <205>; (__ptr_b0.192 var=87 stl=A off=2) assign (__rt.1714) <206>; (__ptr_b1.193 var=91 stl=A off=3) assign (__rt.1736) <207>; (__ct.196 var=161 stl=RA off=0) assign (__ct_2.194) <210>; (__ct.199 var=163 stl=RA off=1) assign (__ct_2.194) <213>; (__ct.202 var=165 stl=AX off=0) assign (__ct_4606281698874543309.200) <216>; (__ct.205 var=167 stl=AX off=1) assign (__ct_4606281698874543309.200) <219>; (__ct.208 var=169 stl=BX off=0) assign (__ct_4576918229304087675.206) <222>; (__ct.211 var=171 stl=RB off=0) assign (__ct_64.209) <225>; (__link.215 var=174 stl=LR off=0) assign (__link.214) <229>; (_ZL10input_port.216 var=48 _ZL11output_port.217 var=50 _ZL17c_sensor_signal_t.218 var=37 _ZL19acc_sensor_signal_t.219 var=39 __extDM.220 var=32 __extDM_SingleSignalPath.221 var=38 __extDM_int16_.222 var=49 __extDM_int32_.223 var=57 __extDM_int64_.224 var=54 __extDM_int8_.225 var=55 __extDM_void.226 var=52 __extPM.227 var=33 __extPM_FILE.228 var=56 __extPM_void.229 var=53 b0.230 var=35 b1.231 var=36 __vola.232 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.215 __ptr_c_sensor_signal_t.190 __ptr_acc_sensor_signal_t.191 __ptr_b0.192 __ptr_b1.193 __ct.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 _ZL10input_port.46 _ZL11output_port.48 _ZL17c_sensor_signal_t.35 _ZL19acc_sensor_signal_t.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.55 __extDM_int64_.52 __extDM_int8_.53 __extDM_void.50 __extPM.31 __extPM_FILE.54 __extPM_void.51 b0.154 b1.189 __vola.27) <230>; } #4 off=1 #5 off=2 (__ptr___str45bf45e5.61 var=64) const () <85>; (__ptr___str00f02b8f.63 var=66) const () <87>; (fopen.236 var=175) const () <234>; (__link.238 var=177) dmaddr__call_dmaddr_ (fopen.236) <236>; call { (__ptr___str45bf45e5.234 var=63 stl=A off=1) assign (__ptr___str45bf45e5.61) <232>; (__ptr___str00f02b8f.235 var=65 stl=A off=2) assign (__ptr___str00f02b8f.63) <233>; (__link.239 var=177 stl=LR off=0) assign (__link.238) <237>; (__tmp.240 var=178 stl=A off=0 _ZL10input_port.243 var=48 _ZL11output_port.244 var=50 _ZL17c_sensor_signal_t.245 var=37 _ZL19acc_sensor_signal_t.246 var=39 __extDM.247 var=32 __extDM_SingleSignalPath.248 var=38 __extDM_int16_.249 var=49 __extDM_int32_.250 var=57 __extDM_int64_.251 var=54 __extDM_int8_.252 var=55 __extDM_void.253 var=52 __extPM.254 var=33 __extPM_FILE.255 var=56 __extPM_void.256 var=53 b0.257 var=35 b1.258 var=36 __vola.259 var=29) Ffopen (__link.239 __ptr___str45bf45e5.234 __ptr___str00f02b8f.235 _ZL10input_port.216 _ZL11output_port.217 _ZL17c_sensor_signal_t.218 _ZL19acc_sensor_signal_t.219 __extDM.220 __extDM_SingleSignalPath.221 __extDM_int16_.222 __extDM_int32_.223 __extDM_int64_.224 __extDM_int8_.225 __extDM_void.226 __extPM.227 __extPM_FILE.228 __extPM_void.229 b0.230 b1.231 __vola.232) <238>; (__tmp.241 var=178) deassign (__tmp.240) <239>; } #6 off=3 #7 off=4 (__ptr___str1747fd53.65 var=68) const () <89>; (__link.265 var=181) dmaddr__call_dmaddr_ (fopen.236) <246>; call { (__ptr___str1747fd53.261 var=67 stl=A off=1) assign (__ptr___str1747fd53.65) <242>; (__ptr___str00f02b8f.262 var=65 stl=A off=2) assign (__ptr___str00f02b8f.63) <243>; (__link.266 var=181 stl=LR off=0) assign (__link.265) <247>; (__tmp.267 var=182 stl=A off=0 _ZL10input_port.270 var=48 _ZL11output_port.271 var=50 _ZL17c_sensor_signal_t.272 var=37 _ZL19acc_sensor_signal_t.273 var=39 __extDM.274 var=32 __extDM_SingleSignalPath.275 var=38 __extDM_int16_.276 var=49 __extDM_int32_.277 var=57 __extDM_int64_.278 var=54 __extDM_int8_.279 var=55 __extDM_void.280 var=52 __extPM.281 var=33 __extPM_FILE.282 var=56 __extPM_void.283 var=53 b0.284 var=35 b1.285 var=36 __vola.286 var=29) Ffopen (__link.266 __ptr___str1747fd53.261 __ptr___str00f02b8f.262 _ZL10input_port.243 _ZL11output_port.244 _ZL17c_sensor_signal_t.245 _ZL19acc_sensor_signal_t.246 __extDM.247 __extDM_SingleSignalPath.248 __extDM_int16_.249 __extDM_int32_.250 __extDM_int64_.251 __extDM_int8_.252 __extDM_void.253 __extPM.254 __extPM_FILE.255 __extPM_void.256 b0.257 b1.258 __vola.259) <248>; (__tmp.268 var=182) deassign (__tmp.267) <249>; } #8 off=5 #9 off=6 (__ptr___str31c2d68e.67 var=70) const () <91>; (__ptr___str00f52cca.69 var=72) const () <93>; (__link.292 var=185) dmaddr__call_dmaddr_ (fopen.236) <256>; call { (__ptr___str31c2d68e.288 var=69 stl=A off=1) assign (__ptr___str31c2d68e.67) <252>; (__ptr___str00f52cca.289 var=71 stl=A off=2) assign (__ptr___str00f52cca.69) <253>; (__link.293 var=185 stl=LR off=0) assign (__link.292) <257>; (__tmp.294 var=186 stl=A off=0 _ZL10input_port.297 var=48 _ZL11output_port.298 var=50 _ZL17c_sensor_signal_t.299 var=37 _ZL19acc_sensor_signal_t.300 var=39 __extDM.301 var=32 __extDM_SingleSignalPath.302 var=38 __extDM_int16_.303 var=49 __extDM_int32_.304 var=57 __extDM_int64_.305 var=54 __extDM_int8_.306 var=55 __extDM_void.307 var=52 __extPM.308 var=33 __extPM_FILE.309 var=56 __extPM_void.310 var=53 b0.311 var=35 b1.312 var=36 __vola.313 var=29) Ffopen (__link.293 __ptr___str31c2d68e.288 __ptr___str00f52cca.289 _ZL10input_port.270 _ZL11output_port.271 _ZL17c_sensor_signal_t.272 _ZL19acc_sensor_signal_t.273 __extDM.274 __extDM_SingleSignalPath.275 __extDM_int16_.276 __extDM_int32_.277 __extDM_int64_.278 __extDM_int8_.279 __extDM_void.280 __extPM.281 __extPM_FILE.282 __extPM_void.283 b0.284 b1.285 __vola.286) <258>; (__tmp.295 var=186) deassign (__tmp.294) <259>; } #10 off=7 #11 off=8 (feof.315 var=187) const () <262>; (__link.317 var=189) dmaddr__call_dmaddr_ (feof.315) <264>; call { (fp1.314 var=103 stl=A off=0) assign (__tmp.241) <261>; (__link.318 var=189 stl=LR off=0) assign (__link.317) <265>; (__tmp.319 var=190 stl=RA off=0 _ZL10input_port.322 var=48 _ZL11output_port.323 var=50 _ZL17c_sensor_signal_t.324 var=37 _ZL19acc_sensor_signal_t.325 var=39 __extDM.326 var=32 __extDM_SingleSignalPath.327 var=38 __extDM_int16_.328 var=49 __extDM_int32_.329 var=57 __extDM_int64_.330 var=54 __extDM_int8_.331 var=55 __extDM_void.332 var=52 __extPM.333 var=33 __extPM_FILE.334 var=56 __extPM_void.335 var=53 b0.336 var=35 b1.337 var=36 __vola.338 var=29) Ffeof (__link.318 fp1.314 _ZL10input_port.297 _ZL11output_port.298 _ZL17c_sensor_signal_t.299 _ZL19acc_sensor_signal_t.300 __extDM.301 __extDM_SingleSignalPath.302 __extDM_int16_.303 __extDM_int32_.304 __extDM_int64_.305 __extDM_int8_.306 __extDM_void.307 __extPM.308 __extPM_FILE.309 __extPM_void.310 b0.311 b1.312 __vola.313) <266>; (__tmp.320 var=190) deassign (__tmp.319) <267>; } #12 off=9 #717 off=10 (__ct_0.122 var=112) const () <146>; (__tmp.2095 var=439) uint3__cmp_int72__int72_ (__tmp.320 __ct_0.122) <2030>; (__tmp.2105 var=382) bool_nequal_uint3_ (__tmp.2095) <2088>; (__trgt.2114 var=453) const () <2183>; () void_jump_bool_int10_ (__tmp.2105 __trgt.2114) <2184>; (__either.2115 var=452) undefined () <2185>; if { { () if_expr (__either.2115) <325>; } #15 { (__true.2121 var=450) const () <2193>; } #16 { #18 off=11 (__link.400 var=198) dmaddr__call_dmaddr_ (feof.315) <331>; call { (fp2.397 var=104 stl=A off=0) assign (__tmp.268) <328>; (__link.401 var=198 stl=LR off=0) assign (__link.400) <332>; (__tmp.402 var=199 stl=RA off=0 _ZL10input_port.405 var=48 _ZL11output_port.406 var=50 _ZL17c_sensor_signal_t.407 var=37 _ZL19acc_sensor_signal_t.408 var=39 __extDM.409 var=32 __extDM_SingleSignalPath.410 var=38 __extDM_int16_.411 var=49 __extDM_int32_.412 var=57 __extDM_int64_.413 var=54 __extDM_int8_.414 var=55 __extDM_void.415 var=52 __extPM.416 var=33 __extPM_FILE.417 var=56 __extPM_void.418 var=53 b0.419 var=35 b1.420 var=36 __vola.421 var=29) Ffeof (__link.401 fp2.397 _ZL10input_port.322 _ZL11output_port.323 _ZL17c_sensor_signal_t.324 _ZL19acc_sensor_signal_t.325 __extDM.326 __extDM_SingleSignalPath.327 __extDM_int16_.328 __extDM_int32_.329 __extDM_int64_.330 __extDM_int8_.331 __extDM_void.332 __extPM.333 __extPM_FILE.334 __extPM_void.335 b0.336 b1.337 __vola.338) <333>; (__tmp.403 var=199) deassign (__tmp.402) <334>; } #19 off=12 #711 off=13 (__tmp.2085 var=439) uint3__cmp_int72__int72_ (__tmp.403 __ct_0.122) <2014>; (__tmp.2110 var=202) bool_nequal_uint3_ (__tmp.2085) <2136>; (__trgt.2122 var=456) const () <2194>; () void_jump_bool_int10_ (__tmp.2110 __trgt.2122) <2195>; (__either.2123 var=452) undefined () <2196>; } #17 { (__vola.426 var=29) merge (__vola.338 __vola.421) <340>; (__extDM.427 var=32) merge (__extDM.326 __extDM.409) <341>; (__extPM.428 var=33) merge (__extPM.333 __extPM.416) <342>; (b0.429 var=35) merge (b0.336 b0.419) <343>; (b1.430 var=36) merge (b1.337 b1.420) <344>; (_ZL17c_sensor_signal_t.431 var=37) merge (_ZL17c_sensor_signal_t.324 _ZL17c_sensor_signal_t.407) <345>; (__extDM_SingleSignalPath.432 var=38) merge (__extDM_SingleSignalPath.327 __extDM_SingleSignalPath.410) <346>; (_ZL19acc_sensor_signal_t.433 var=39) merge (_ZL19acc_sensor_signal_t.325 _ZL19acc_sensor_signal_t.408) <347>; (_ZL10input_port.434 var=48) merge (_ZL10input_port.322 _ZL10input_port.405) <348>; (__extDM_int16_.435 var=49) merge (__extDM_int16_.328 __extDM_int16_.411) <349>; (_ZL11output_port.436 var=50) merge (_ZL11output_port.323 _ZL11output_port.406) <350>; (__extDM_void.437 var=52) merge (__extDM_void.332 __extDM_void.415) <351>; (__extPM_void.438 var=53) merge (__extPM_void.335 __extPM_void.418) <352>; (__extDM_int64_.439 var=54) merge (__extDM_int64_.330 __extDM_int64_.413) <353>; (__extDM_int8_.440 var=55) merge (__extDM_int8_.331 __extDM_int8_.414) <354>; (__extPM_FILE.441 var=56) merge (__extPM_FILE.334 __extPM_FILE.417) <355>; (__extDM_int32_.442 var=57) merge (__extDM_int32_.329 __extDM_int32_.412) <356>; (__tmp.2111 var=203) merge (__true.2121 __either.2123) <2137>; } #21 } #14 if { { () if_expr (__tmp.2111) <411>; () chess_frequent_else () <412>; () chess_rear_then () <2197>; } #24 { (__trgt.2124 var=457) const () <2198>; () void_jump_int10_ (__trgt.2124) <2199>; } #72 off=30 { #760 off=14 (__ptr___str41232700.71 var=74) const () <95>; (__ct_8388608.73 var=76) const () <97>; (__ct_8388624.76 var=78) const () <100>; (__ptr___str2eb09b76.79 var=80) const () <103>; (fscanf.665 var=210) const () <583>; (_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884 var=245) const () <709>; (fprintf.1030 var=259) const () <837>; (__rt.1758 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_80t0.2051) <1523>; (__rt.1780 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_84t0.2054) <1551>; (__ct_80t0.2051 var=404) const () <1947>; (__ct_84t0.2054 var=407) const () <1953>; (__ct_2.2057 var=410) const () <1959>; (__trgt.2116 var=454) const () <2186>; (__trgt.2119 var=455) const () <2190>; do { { (__vola.497 var=29) entry (__vola.1325 __vola.426) <413>; (__extDM.500 var=32) entry (__extDM.1331 __extDM.427) <416>; (__extPM.501 var=33) entry (__extPM.1333 __extPM.428) <417>; (b0.503 var=35) entry (b0.1337 b0.429) <419>; (b1.504 var=36) entry (b1.1339 b1.430) <420>; (_ZL17c_sensor_signal_t.505 var=37) entry (_ZL17c_sensor_signal_t.1341 _ZL17c_sensor_signal_t.431) <421>; (__extDM_SingleSignalPath.506 var=38) entry (__extDM_SingleSignalPath.1343 __extDM_SingleSignalPath.432) <422>; (_ZL19acc_sensor_signal_t.507 var=39) entry (_ZL19acc_sensor_signal_t.1345 _ZL19acc_sensor_signal_t.433) <423>; (d0.514 var=46) entry (d0.1359 d0.44) <430>; (d1.515 var=47) entry (d1.1361 d1.45) <431>; (_ZL10input_port.516 var=48) entry (_ZL10input_port.1363 _ZL10input_port.434) <432>; (__extDM_int16_.517 var=49) entry (__extDM_int16_.1365 __extDM_int16_.435) <433>; (_ZL11output_port.518 var=50) entry (_ZL11output_port.1367 _ZL11output_port.436) <434>; (__extDM_void.520 var=52) entry (__extDM_void.1371 __extDM_void.437) <436>; (__extPM_void.521 var=53) entry (__extPM_void.1373 __extPM_void.438) <437>; (__extDM_int64_.522 var=54) entry (__extDM_int64_.1375 __extDM_int64_.439) <438>; (__extDM_int8_.523 var=55) entry (__extDM_int8_.1377 __extDM_int8_.440) <439>; (__extPM_FILE.524 var=56) entry (__extPM_FILE.1379 __extPM_FILE.441) <440>; (__extDM_int32_.525 var=57) entry (__extDM_int32_.1381 __extDM_int32_.442) <441>; (__shv___ptr_input_port.1646 var=333) entry (__shv___ptr_input_port.1644 __ct_8388608.73) <1338>; } #27 { #36 off=15 (__link.667 var=212) dmaddr__call_dmaddr_ (fscanf.665) <585>; call { (fp1.662 var=103 stl=A off=0) assign (__tmp.241) <580>; (__ptr___str41232700.663 var=73 stl=A off=1) assign (__ptr___str41232700.71) <581>; (__ptr_d0.664 var=95 stl=__spill_WDMA off=0) assign (__rt.1758) <582>; (__link.668 var=212 stl=LR off=0) assign (__link.667) <586>; (__tmp.669 var=213 stl=RA off=0 _ZL10input_port.672 var=48 _ZL11output_port.673 var=50 _ZL17c_sensor_signal_t.674 var=37 _ZL19acc_sensor_signal_t.675 var=39 __extDM.676 var=32 __extDM_SingleSignalPath.677 var=38 __extDM_int16_.678 var=49 __extDM_int32_.679 var=57 __extDM_int64_.680 var=54 __extDM_int8_.681 var=55 __extDM_void.682 var=52 __extPM.683 var=33 __extPM_FILE.684 var=56 __extPM_void.685 var=53 b0.686 var=35 b1.687 var=36 d0.688 var=46 __vola.689 var=29) VA0Ffscanf (__link.668 fp1.662 __ptr___str41232700.663 __ptr_d0.664 _ZL10input_port.516 _ZL11output_port.518 _ZL17c_sensor_signal_t.505 _ZL19acc_sensor_signal_t.507 __extDM.500 __extDM_SingleSignalPath.506 __extDM_int16_.517 __extDM_int32_.525 __extDM_int64_.522 __extDM_int8_.523 __extDM_void.520 __extPM.501 __extPM_FILE.524 __extPM_void.521 b0.503 b1.504 d0.514 __vola.497) <587>; } #37 off=16 #38 off=17 (__link.695 var=216) dmaddr__call_dmaddr_ (fscanf.665) <595>; call { (fp2.690 var=104 stl=A off=0) assign (__tmp.268) <590>; (__ptr___str41232700.691 var=73 stl=A off=1) assign (__ptr___str41232700.71) <591>; (__ptr_d1.692 var=99 stl=__spill_WDMA off=0) assign (__rt.1780) <592>; (__link.696 var=216 stl=LR off=0) assign (__link.695) <596>; (__tmp.697 var=217 stl=RA off=0 _ZL10input_port.700 var=48 _ZL11output_port.701 var=50 _ZL17c_sensor_signal_t.702 var=37 _ZL19acc_sensor_signal_t.703 var=39 __extDM.704 var=32 __extDM_SingleSignalPath.705 var=38 __extDM_int16_.706 var=49 __extDM_int32_.707 var=57 __extDM_int64_.708 var=54 __extDM_int8_.709 var=55 __extDM_void.710 var=52 __extPM.711 var=33 __extPM_FILE.712 var=56 __extPM_void.713 var=53 b0.714 var=35 b1.715 var=36 d0.716 var=46 d1.717 var=47 __vola.718 var=29) VA1Ffscanf (__link.696 fp2.690 __ptr___str41232700.691 __ptr_d1.692 _ZL10input_port.672 _ZL11output_port.673 _ZL17c_sensor_signal_t.674 _ZL19acc_sensor_signal_t.675 __extDM.676 __extDM_SingleSignalPath.677 __extDM_int16_.678 __extDM_int32_.679 __extDM_int64_.680 __extDM_int8_.681 __extDM_void.682 __extPM.683 __extPM_FILE.684 __extPM_void.685 b0.686 b1.687 d0.688 d1.515 __vola.689) <597>; } #39 off=18 #490 off=19 (__fch_d0.719 var=218) load (__M_WDMA.9 __rt.1758 d0.716) <600>; (__tmp.720 var=219) __sshort___sshort___sint (__fch_d0.719) <601>; (__M_SDMB.725 var=8 _ZL10input_port.726 var=48 __vola.727 var=29) store (__tmp.720 __shv___ptr_input_port.1646 _ZL10input_port.700 __vola.718) <606>; (__fch_d1.728 var=224) load (__M_WDMA.9 __rt.1780 d1.717) <607>; (__tmp.729 var=225) __sshort___sshort___sint (__fch_d1.728) <608>; (__M_SDMB.737 var=8 _ZL10input_port.738 var=48 __vola.739 var=29) store (__tmp.729 __rt.1834 _ZL10input_port.726 __vola.727) <616>; (__link.886 var=247) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884) <711>; (__rt.1834 var=357) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1646 __ct_2.2057) <1623>; (__rt.1856 var=357) __Pvoid__mi___Pvoid_int18_ (__rt.1834 __ct_2.2057) <1651>; call { (__ptr_c_sensor_signal_t.873 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <698>; (__ptr_acc_sensor_signal_t.874 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <699>; (__tmp.878 var=241 stl=A off=4) assign (__shv___ptr_input_port.1646) <703>; (__tmp.882 var=244 stl=A off=5) assign (__rt.1834) <707>; (__ptr_output_port.883 var=77 stl=__spill_WDMA off=0) assign (__ct_8388624.76) <708>; (__link.887 var=247 stl=LR off=0) assign (__link.886) <712>; (_ZL10input_port.888 var=48 _ZL11output_port.889 var=50 _ZL17c_sensor_signal_t.890 var=37 _ZL19acc_sensor_signal_t.891 var=39 __extDM.892 var=32 __extDM_SingleSignalPath.893 var=38 __extDM_int16_.894 var=49 __extDM_int32_.895 var=57 __extDM_int64_.896 var=54 __extDM_int8_.897 var=55 __extDM_void.898 var=52 __extPM.899 var=33 __extPM_FILE.900 var=56 __extPM_void.901 var=53 b0.902 var=35 b1.903 var=36 d0.904 var=46 d1.905 var=47 __vola.906 var=29) F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ (__link.887 __ptr_c_sensor_signal_t.873 __ptr_acc_sensor_signal_t.874 __tmp.878 __tmp.882 __ptr_output_port.883 _ZL10input_port.738 _ZL11output_port.701 _ZL17c_sensor_signal_t.702 _ZL19acc_sensor_signal_t.703 __extDM.704 __extDM_SingleSignalPath.705 __extDM_int16_.706 __extDM_int32_.707 __extDM_int64_.708 __extDM_int8_.709 __extDM_void.710 __extPM.711 __extPM_FILE.712 __extPM_void.713 b0.714 b1.715 d0.716 d1.717 __vola.739) <713>; } #45 off=20 #53 off=21 (__fch__ZL11output_port.1025 var=257 _ZL11output_port.1026 var=50 __vola.1027 var=29) load (__M_SDMB.6 __ct_8388624.76 _ZL11output_port.889 __vola.906) <834>; (__link.1032 var=261) dmaddr__call_dmaddr_ (fprintf.1030) <839>; call { (fp3.1019 var=105 stl=A off=0) assign (__tmp.295) <828>; (__ptr___str2eb09b76.1020 var=79 stl=A off=1) assign (__ptr___str2eb09b76.79) <829>; (__fch__ZL11output_port.1029 var=258 stl=__spill_WDMA off=0) assign (__fch__ZL11output_port.1025) <836>; (__link.1033 var=261 stl=LR off=0) assign (__link.1032) <840>; (__tmp.1034 var=262 stl=RA off=0 _ZL10input_port.1037 var=48 _ZL11output_port.1038 var=50 _ZL17c_sensor_signal_t.1039 var=37 _ZL19acc_sensor_signal_t.1040 var=39 __extDM.1041 var=32 __extDM_SingleSignalPath.1042 var=38 __extDM_int16_.1043 var=49 __extDM_int32_.1044 var=57 __extDM_int64_.1045 var=54 __extDM_int8_.1046 var=55 __extDM_void.1047 var=52 __extPM.1048 var=33 __extPM_FILE.1049 var=56 __extPM_void.1050 var=53 b0.1051 var=35 b1.1052 var=36 d0.1053 var=46 d1.1054 var=47 __vola.1055 var=29) VA2Ffprintf (__link.1033 fp3.1019 __ptr___str2eb09b76.1020 __fch__ZL11output_port.1029 _ZL10input_port.888 _ZL11output_port.1026 _ZL17c_sensor_signal_t.890 _ZL19acc_sensor_signal_t.891 __extDM.892 __extDM_SingleSignalPath.893 __extDM_int16_.894 __extDM_int32_.895 __extDM_int64_.896 __extDM_int8_.897 __extDM_void.898 __extPM.899 __extPM_FILE.900 __extPM_void.901 b0.902 b1.903 d0.904 d1.905 __vola.1027) <841>; } #54 off=22 #59 off=23 (__link.1192 var=271) dmaddr__call_dmaddr_ (feof.315) <928>; call { (fp1.1189 var=103 stl=A off=0) assign (__tmp.241) <925>; (__link.1193 var=271 stl=LR off=0) assign (__link.1192) <929>; (__tmp.1194 var=272 stl=RA off=0 _ZL10input_port.1197 var=48 _ZL11output_port.1198 var=50 _ZL17c_sensor_signal_t.1199 var=37 _ZL19acc_sensor_signal_t.1200 var=39 __extDM.1201 var=32 __extDM_SingleSignalPath.1202 var=38 __extDM_int16_.1203 var=49 __extDM_int32_.1204 var=57 __extDM_int64_.1205 var=54 __extDM_int8_.1206 var=55 __extDM_void.1207 var=52 __extPM.1208 var=33 __extPM_FILE.1209 var=56 __extPM_void.1210 var=53 b0.1211 var=35 b1.1212 var=36 d0.1213 var=46 d1.1214 var=47 __vola.1215 var=29) Ffeof (__link.1193 fp1.1189 _ZL10input_port.1037 _ZL11output_port.1038 _ZL17c_sensor_signal_t.1039 _ZL19acc_sensor_signal_t.1040 __extDM.1041 __extDM_SingleSignalPath.1042 __extDM_int16_.1043 __extDM_int32_.1044 __extDM_int64_.1045 __extDM_int8_.1046 __extDM_void.1047 __extPM.1048 __extPM_FILE.1049 __extPM_void.1050 b0.1051 b1.1052 d0.1053 d1.1054 __vola.1055) <930>; (__tmp.1195 var=272) deassign (__tmp.1194) <931>; } #60 off=24 #722 off=25 (__tmp.2100 var=439) uint3__cmp_int72__int72_ (__tmp.1195 __ct_0.122) <2038>; (__tmp.2106 var=382) bool_nequal_uint3_ (__tmp.2100) <2089>; () void_jump_bool_int10_ (__tmp.2106 __trgt.2116) <2187>; (__either.2117 var=452) undefined () <2188>; if { { () if_expr (__either.2117) <989>; } #63 { (__false.2118 var=451) const () <2189>; } #64 { #66 off=26 (__link.1277 var=280) dmaddr__call_dmaddr_ (feof.315) <995>; call { (fp2.1274 var=104 stl=A off=0) assign (__tmp.268) <992>; (__link.1278 var=280 stl=LR off=0) assign (__link.1277) <996>; (__tmp.1279 var=281 stl=RA off=0 _ZL10input_port.1282 var=48 _ZL11output_port.1283 var=50 _ZL17c_sensor_signal_t.1284 var=37 _ZL19acc_sensor_signal_t.1285 var=39 __extDM.1286 var=32 __extDM_SingleSignalPath.1287 var=38 __extDM_int16_.1288 var=49 __extDM_int32_.1289 var=57 __extDM_int64_.1290 var=54 __extDM_int8_.1291 var=55 __extDM_void.1292 var=52 __extPM.1293 var=33 __extPM_FILE.1294 var=56 __extPM_void.1295 var=53 b0.1296 var=35 b1.1297 var=36 d0.1298 var=46 d1.1299 var=47 __vola.1300 var=29) Ffeof (__link.1278 fp2.1274 _ZL10input_port.1197 _ZL11output_port.1198 _ZL17c_sensor_signal_t.1199 _ZL19acc_sensor_signal_t.1200 __extDM.1201 __extDM_SingleSignalPath.1202 __extDM_int16_.1203 __extDM_int32_.1204 __extDM_int64_.1205 __extDM_int8_.1206 __extDM_void.1207 __extPM.1208 __extPM_FILE.1209 __extPM_void.1210 b0.1211 b1.1212 d0.1213 d1.1214 __vola.1215) <997>; (__tmp.1280 var=281) deassign (__tmp.1279) <998>; } #67 off=27 #714 off=28 (__tmp.2090 var=439) uint3__cmp_int72__int72_ (__tmp.1280 __ct_0.122) <2022>; (__tmp.2091 var=284) bool_equal_uint3_ (__tmp.2090) <2023>; () void_jump_bool_int10_ (__tmp.2091 __trgt.2119) <2191>; (__either.2120 var=452) undefined () <2192>; } #65 { (__vola.1305 var=29) merge (__vola.1215 __vola.1300) <1004>; (__extDM.1306 var=32) merge (__extDM.1201 __extDM.1286) <1005>; (__extPM.1307 var=33) merge (__extPM.1208 __extPM.1293) <1006>; (b0.1308 var=35) merge (b0.1211 b0.1296) <1007>; (b1.1309 var=36) merge (b1.1212 b1.1297) <1008>; (_ZL17c_sensor_signal_t.1310 var=37) merge (_ZL17c_sensor_signal_t.1199 _ZL17c_sensor_signal_t.1284) <1009>; (__extDM_SingleSignalPath.1311 var=38) merge (__extDM_SingleSignalPath.1202 __extDM_SingleSignalPath.1287) <1010>; (_ZL19acc_sensor_signal_t.1312 var=39) merge (_ZL19acc_sensor_signal_t.1200 _ZL19acc_sensor_signal_t.1285) <1011>; (d0.1313 var=46) merge (d0.1213 d0.1298) <1012>; (d1.1314 var=47) merge (d1.1214 d1.1299) <1013>; (_ZL10input_port.1315 var=48) merge (_ZL10input_port.1197 _ZL10input_port.1282) <1014>; (__extDM_int16_.1316 var=49) merge (__extDM_int16_.1203 __extDM_int16_.1288) <1015>; (_ZL11output_port.1317 var=50) merge (_ZL11output_port.1198 _ZL11output_port.1283) <1016>; (__extDM_void.1318 var=52) merge (__extDM_void.1207 __extDM_void.1292) <1017>; (__extPM_void.1319 var=53) merge (__extPM_void.1210 __extPM_void.1295) <1018>; (__extDM_int64_.1320 var=54) merge (__extDM_int64_.1205 __extDM_int64_.1290) <1019>; (__extDM_int8_.1321 var=55) merge (__extDM_int8_.1206 __extDM_int8_.1291) <1020>; (__extPM_FILE.1322 var=56) merge (__extPM_FILE.1209 __extPM_FILE.1294) <1021>; (__extDM_int32_.1323 var=57) merge (__extDM_int32_.1204 __extDM_int32_.1289) <1022>; (__tmp.1604 var=285) merge (__false.2118 __either.2120) <1299>; } #69 } #62 } #28 { () while_expr (__tmp.1604) <1024>; (__vola.1325 var=29 __vola.1326 var=29) exit (__vola.1305) <1025>; (__extDM.1331 var=32 __extDM.1332 var=32) exit (__extDM.1306) <1028>; (__extPM.1333 var=33 __extPM.1334 var=33) exit (__extPM.1307) <1029>; (b0.1337 var=35 b0.1338 var=35) exit (b0.1308) <1031>; (b1.1339 var=36 b1.1340 var=36) exit (b1.1309) <1032>; (_ZL17c_sensor_signal_t.1341 var=37 _ZL17c_sensor_signal_t.1342 var=37) exit (_ZL17c_sensor_signal_t.1310) <1033>; (__extDM_SingleSignalPath.1343 var=38 __extDM_SingleSignalPath.1344 var=38) exit (__extDM_SingleSignalPath.1311) <1034>; (_ZL19acc_sensor_signal_t.1345 var=39 _ZL19acc_sensor_signal_t.1346 var=39) exit (_ZL19acc_sensor_signal_t.1312) <1035>; (d0.1359 var=46 d0.1360 var=46) exit (d0.1313) <1042>; (d1.1361 var=47 d1.1362 var=47) exit (d1.1314) <1043>; (_ZL10input_port.1363 var=48 _ZL10input_port.1364 var=48) exit (_ZL10input_port.1315) <1044>; (__extDM_int16_.1365 var=49 __extDM_int16_.1366 var=49) exit (__extDM_int16_.1316) <1045>; (_ZL11output_port.1367 var=50 _ZL11output_port.1368 var=50) exit (_ZL11output_port.1317) <1046>; (__extDM_void.1371 var=52 __extDM_void.1372 var=52) exit (__extDM_void.1318) <1048>; (__extPM_void.1373 var=53 __extPM_void.1374 var=53) exit (__extPM_void.1319) <1049>; (__extDM_int64_.1375 var=54 __extDM_int64_.1376 var=54) exit (__extDM_int64_.1320) <1050>; (__extDM_int8_.1377 var=55 __extDM_int8_.1378 var=55) exit (__extDM_int8_.1321) <1051>; (__extPM_FILE.1379 var=56 __extPM_FILE.1380 var=56) exit (__extPM_FILE.1322) <1052>; (__extDM_int32_.1381 var=57 __extDM_int32_.1382 var=57) exit (__extDM_int32_.1323) <1053>; (__shv___ptr_input_port.1644 var=333 __shv___ptr_input_port.1645 var=333) exit (__rt.1856) <1337>; } #71 } #26 rng=[1,65535] } #25 { (__vola.1431 var=29) merge (__vola.426 __vola.1326) <1078>; (__extDM.1432 var=32) merge (__extDM.427 __extDM.1332) <1079>; (__extPM.1433 var=33) merge (__extPM.428 __extPM.1334) <1080>; (b0.1434 var=35) merge (b0.429 b0.1338) <1081>; (b1.1435 var=36) merge (b1.430 b1.1340) <1082>; (_ZL17c_sensor_signal_t.1436 var=37) merge (_ZL17c_sensor_signal_t.431 _ZL17c_sensor_signal_t.1342) <1083>; (__extDM_SingleSignalPath.1437 var=38) merge (__extDM_SingleSignalPath.432 __extDM_SingleSignalPath.1344) <1084>; (_ZL19acc_sensor_signal_t.1438 var=39) merge (_ZL19acc_sensor_signal_t.433 _ZL19acc_sensor_signal_t.1346) <1085>; (d0.1439 var=46) merge (d0.44 d0.1360) <1086>; (d1.1440 var=47) merge (d1.45 d1.1362) <1087>; (_ZL10input_port.1441 var=48) merge (_ZL10input_port.434 _ZL10input_port.1364) <1088>; (__extDM_int16_.1442 var=49) merge (__extDM_int16_.435 __extDM_int16_.1366) <1089>; (_ZL11output_port.1443 var=50) merge (_ZL11output_port.436 _ZL11output_port.1368) <1090>; (__extDM_void.1444 var=52) merge (__extDM_void.437 __extDM_void.1372) <1091>; (__extPM_void.1445 var=53) merge (__extPM_void.438 __extPM_void.1374) <1092>; (__extDM_int64_.1446 var=54) merge (__extDM_int64_.439 __extDM_int64_.1376) <1093>; (__extDM_int8_.1447 var=55) merge (__extDM_int8_.440 __extDM_int8_.1378) <1094>; (__extPM_FILE.1448 var=56) merge (__extPM_FILE.441 __extPM_FILE.1380) <1095>; (__extDM_int32_.1449 var=57) merge (__extDM_int32_.442 __extDM_int32_.1382) <1096>; } #73 } #23 #74 off=31 (fclose.1455 var=287) const () <1102>; (__link.1457 var=289) dmaddr__call_dmaddr_ (fclose.1455) <1104>; call { (fp1.1454 var=103 stl=A off=0) assign (__tmp.241) <1101>; (__link.1458 var=289 stl=LR off=0) assign (__link.1457) <1105>; (__tmp.1459 var=290 stl=RA off=0 _ZL10input_port.1462 var=48 _ZL11output_port.1463 var=50 _ZL17c_sensor_signal_t.1464 var=37 _ZL19acc_sensor_signal_t.1465 var=39 __extDM.1466 var=32 __extDM_SingleSignalPath.1467 var=38 __extDM_int16_.1468 var=49 __extDM_int32_.1469 var=57 __extDM_int64_.1470 var=54 __extDM_int8_.1471 var=55 __extDM_void.1472 var=52 __extPM.1473 var=33 __extPM_FILE.1474 var=56 __extPM_void.1475 var=53 b0.1476 var=35 b1.1477 var=36 d0.1478 var=46 d1.1479 var=47 __vola.1480 var=29) Ffclose (__link.1458 fp1.1454 _ZL10input_port.1441 _ZL11output_port.1443 _ZL17c_sensor_signal_t.1436 _ZL19acc_sensor_signal_t.1438 __extDM.1432 __extDM_SingleSignalPath.1437 __extDM_int16_.1442 __extDM_int32_.1449 __extDM_int64_.1446 __extDM_int8_.1447 __extDM_void.1444 __extPM.1433 __extPM_FILE.1448 __extPM_void.1445 b0.1434 b1.1435 d0.1439 d1.1440 __vola.1431) <1106>; } #75 off=32 #76 off=33 (__link.1484 var=293) dmaddr__call_dmaddr_ (fclose.1455) <1112>; call { (fp2.1481 var=104 stl=A off=0) assign (__tmp.268) <1109>; (__link.1485 var=293 stl=LR off=0) assign (__link.1484) <1113>; (__tmp.1486 var=294 stl=RA off=0 _ZL10input_port.1489 var=48 _ZL11output_port.1490 var=50 _ZL17c_sensor_signal_t.1491 var=37 _ZL19acc_sensor_signal_t.1492 var=39 __extDM.1493 var=32 __extDM_SingleSignalPath.1494 var=38 __extDM_int16_.1495 var=49 __extDM_int32_.1496 var=57 __extDM_int64_.1497 var=54 __extDM_int8_.1498 var=55 __extDM_void.1499 var=52 __extPM.1500 var=33 __extPM_FILE.1501 var=56 __extPM_void.1502 var=53 b0.1503 var=35 b1.1504 var=36 d0.1505 var=46 d1.1506 var=47 __vola.1507 var=29) Ffclose (__link.1485 fp2.1481 _ZL10input_port.1462 _ZL11output_port.1463 _ZL17c_sensor_signal_t.1464 _ZL19acc_sensor_signal_t.1465 __extDM.1466 __extDM_SingleSignalPath.1467 __extDM_int16_.1468 __extDM_int32_.1469 __extDM_int64_.1470 __extDM_int8_.1471 __extDM_void.1472 __extPM.1473 __extPM_FILE.1474 __extPM_void.1475 b0.1476 b1.1477 d0.1478 d1.1479 __vola.1480) <1114>; } #77 off=34 #78 off=35 (__link.1511 var=297) dmaddr__call_dmaddr_ (fclose.1455) <1120>; call { (fp3.1508 var=105 stl=A off=0) assign (__tmp.295) <1117>; (__link.1512 var=297 stl=LR off=0) assign (__link.1511) <1121>; (__tmp.1513 var=298 stl=RA off=0 _ZL10input_port.1516 var=48 _ZL11output_port.1517 var=50 _ZL17c_sensor_signal_t.1518 var=37 _ZL19acc_sensor_signal_t.1519 var=39 __extDM.1520 var=32 __extDM_SingleSignalPath.1521 var=38 __extDM_int16_.1522 var=49 __extDM_int32_.1523 var=57 __extDM_int64_.1524 var=54 __extDM_int8_.1525 var=55 __extDM_void.1526 var=52 __extPM.1527 var=33 __extPM_FILE.1528 var=56 __extPM_void.1529 var=53 b0.1530 var=35 b1.1531 var=36 d0.1532 var=46 d1.1533 var=47 __vola.1534 var=29) Ffclose (__link.1512 fp3.1508 _ZL10input_port.1489 _ZL11output_port.1490 _ZL17c_sensor_signal_t.1491 _ZL19acc_sensor_signal_t.1492 __extDM.1493 __extDM_SingleSignalPath.1494 __extDM_int16_.1495 __extDM_int32_.1496 __extDM_int64_.1497 __extDM_int8_.1498 __extDM_void.1499 __extPM.1500 __extPM_FILE.1501 __extPM_void.1502 b0.1503 b1.1504 d0.1505 d1.1506 __vola.1507) <1122>; } #79 off=36 #82 off=37 nxt=-2 (__R_SP.1541 var=26 __sp.1542 var=34) wr_res_reg (__rt.1812 __sp.92) <1131>; () void_ret_dmaddr_ (__la.84) <1132>; (__rt.1543 var=83 stl=RA off=0) assign (__ct_0.122) <1133>; () out (__rt.1543) <1134>; () sink (__vola.1534) <1135>; () sink (__extDM.1520) <1138>; () sink (__extPM.1527) <1139>; () sink (__sp.1542) <1140>; () sink (_ZL17c_sensor_signal_t.1518) <1141>; () sink (__extDM_SingleSignalPath.1521) <1142>; () sink (_ZL19acc_sensor_signal_t.1519) <1143>; () sink (_ZL10input_port.1516) <1150>; () sink (__extDM_int16_.1522) <1151>; () sink (_ZL11output_port.1517) <1152>; () sink (__extDM_void.1526) <1154>; () sink (__extPM_void.1529) <1155>; () sink (__extDM_int64_.1524) <1156>; () sink (__extDM_int8_.1525) <1157>; () sink (__extPM_FILE.1528) <1158>; () sink (__extDM_int32_.1523) <1159>; () sink (__ct_0.81) <1160>; (__rt.1812 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_88s0.2046) <1595>; (__ct_88s0.2046 var=399) const () <1937>; } #0 0 : 'main.c'; ---------- 0 : (0,28:0,0); 4 : (0,37:4,14); 5 : (0,49:71,15); 6 : (0,49:16,15); 7 : (0,50:67,16); 8 : (0,50:16,16); 9 : (0,51:78,17); 10 : (0,51:16,17); 11 : (0,55:4,19); 12 : (0,55:4,19); 14 : (0,55:4,19); 16 : (0,55:4,20); 17 : (0,55:4,21); 18 : (0,55:4,21); 19 : (0,55:4,21); 23 : (0,55:4,23); 25 : (0,55:4,24); 26 : (0,55:4,24); 28 : (0,55:37,24); 36 : (0,57:22,26); 37 : (0,57:12,26); 38 : (0,58:22,27); 39 : (0,58:12,27); 45 : (0,62:8,39); 53 : (0,65:23,42); 54 : (0,65:12,42); 59 : (0,55:18,53); 60 : (0,55:13,53); 62 : (0,55:23,53); 64 : (0,55:23,54); 65 : (0,55:23,55); 66 : (0,55:31,55); 67 : (0,55:26,55); 72 : (0,55:4,59); 74 : (0,68:11,62); 75 : (0,68:4,62); 76 : (0,69:11,63); 77 : (0,69:4,63); 78 : (0,70:11,64); 79 : (0,70:4,64); 82 : (0,71:0,65); 368 : (0,37:4,14); 490 : (0,62:8,39); 711 : (0,55:4,21); 714 : (0,55:23,55); 717 : (0,55:4,19); 722 : (0,55:23,53); ---------- 85 : (0,49:22,0); 87 : (0,49:71,0); 89 : (0,50:22,0); 91 : (0,51:22,0); 93 : (0,51:78,0); 111 : (0,28:4,0); 115 : (0,28:4,0); 117 : (0,31:11,0); 144 : (0,31:18,0); 146 : (0,31:18,0); 149 : (0,31:18,1); 150 : (0,31:24,0); 155 : (0,31:24,2); 161 : (0,31:28,3); 167 : (0,31:32,4); 173 : (0,31:36,5); 179 : (0,32:18,7); 185 : (0,32:24,8); 191 : (0,32:28,9); 197 : (0,32:32,10); 203 : (0,32:36,11); 204 : (0,38:8,0); 205 : (0,38:28,0); 206 : (0,39:8,0); 207 : (0,40:8,0); 208 : (0,41:8,0); 210 : (0,41:8,0); 213 : (0,42:8,0); 214 : (0,43:8,0); 216 : (0,43:8,0); 219 : (0,44:8,0); 220 : (0,45:8,0); 222 : (0,45:8,0); 223 : (0,46:8,0); 225 : (0,46:8,0); 228 : (0,37:4,14); 229 : (0,37:4,0); 230 : (0,37:4,14); 232 : (0,49:22,0); 233 : (0,49:71,0); 236 : (0,49:16,15); 237 : (0,49:16,0); 238 : (0,49:16,15); 242 : (0,50:22,0); 243 : (0,50:67,0); 246 : (0,50:16,16); 247 : (0,50:16,0); 248 : (0,50:16,16); 252 : (0,51:22,0); 253 : (0,51:78,0); 256 : (0,51:16,17); 257 : (0,51:16,0); 258 : (0,51:16,17); 261 : (0,55:4,0); 264 : (0,55:4,19); 265 : (0,55:4,0); 266 : (0,55:4,19); 325 : (0,55:4,19); 328 : (0,55:4,0); 331 : (0,55:4,21); 332 : (0,55:4,0); 333 : (0,55:4,21); 340 : (0,55:4,22); 341 : (0,55:4,22); 342 : (0,55:4,22); 343 : (0,55:4,22); 344 : (0,55:4,22); 345 : (0,55:4,22); 346 : (0,55:4,22); 347 : (0,55:4,22); 348 : (0,55:4,22); 349 : (0,55:4,22); 350 : (0,55:4,22); 351 : (0,55:4,22); 352 : (0,55:4,22); 353 : (0,55:4,22); 354 : (0,55:4,22); 355 : (0,55:4,22); 356 : (0,55:4,22); 411 : (0,55:4,23); 413 : (0,55:4,24); 416 : (0,55:4,24); 417 : (0,55:4,24); 419 : (0,55:4,24); 420 : (0,55:4,24); 421 : (0,55:4,24); 422 : (0,55:4,24); 423 : (0,55:4,24); 430 : (0,55:4,24); 431 : (0,55:4,24); 432 : (0,55:4,24); 433 : (0,55:4,24); 434 : (0,55:4,24); 436 : (0,55:4,24); 437 : (0,55:4,24); 438 : (0,55:4,24); 439 : (0,55:4,24); 440 : (0,55:4,24); 441 : (0,55:4,24); 580 : (0,57:19,0); 581 : (0,57:24,0); 582 : (0,57:22,0); 585 : (0,57:12,26); 586 : (0,57:12,0); 587 : (0,57:12,26); 590 : (0,58:19,0); 591 : (0,58:24,0); 592 : (0,58:22,0); 595 : (0,58:12,27); 596 : (0,58:12,0); 597 : (0,58:12,27); 600 : (0,59:38,28); 601 : (0,59:28,28); 606 : (0,59:22,28); 607 : (0,60:40,29); 608 : (0,60:30,29); 616 : (0,60:22,29); 698 : (0,63:12,0); 699 : (0,63:32,0); 703 : (0,63:65,0); 707 : (0,63:81,0); 708 : (0,63:86,0); 711 : (0,62:8,39); 712 : (0,62:8,0); 713 : (0,62:8,39); 828 : (0,65:20,0); 829 : (0,65:25,0); 834 : (0,65:44,42); 836 : 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