// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Tue Jan 27 11:15:58 2026 // Copyright 2014-2025 Synopsys, Inc. All rights reserved. // C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32 /*** !! void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *) F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called { fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)'; arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i ); loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] ); vac : ( srIM[0] ); frm : ( ); } **** !! void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int) F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called { fnm : "sig_cirular_buffer_ptr_put_sample_DMB" 'void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)'; arg : ( dmaddr_:i dmaddr_:i int32_:i ); loc : ( LR[0] A[4] RA[0] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } ***/ [ 0 : _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___PSingleSignalPath_OutputMode___PDMB__sshort___PDMB__sshort___PDMB__sshort__ 8 : __M_SDMB typ=int16_ bnd=d stl=SDMB 11 : __M_WDMA typ=int32_ bnd=d stl=WDMA 12 : __M_WDMB typ=int32_ bnd=d stl=WDMB 14 : __M_LDMA typ=int64_ bnd=d stl=LDMA 26 : __R_SP typ=dmaddr_ bnd=d stl=SP 29 : __vola typ=uint20_ bnd=b stl=PM 32 : __extDM typ=int8_ bnd=b stl=DM 33 : __extPM typ=uint20_ bnd=b stl=PM 34 : __sp typ=dmaddr_ bnd=b stl=SP 35 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA 36 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA 37 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA 38 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA 39 : ptr_fir_lms_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB 40 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM 41 : ptr_fir_lms_coeffs typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA 42 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM 43 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB 44 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB 45 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA 46 : __extDM_int32_ typ=int8_ bnd=b stl=DM 47 : __extDM_int16_ typ=int8_ bnd=b stl=DM 48 : __extDM_void typ=int8_ bnd=b stl=DM 49 : __extPM_void typ=uint20_ bnd=b stl=PM 50 : ptr_fir_lms_delay_line_ptr_current typ=int8_ bnd=b stl=DM 51 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM 52 : ptr_fir_lms_delay_line_ptr_start typ=int8_ bnd=b stl=DM 53 : ptr_fir_lms_coeffs_ptr_current typ=int8_ bnd=b stl=DM 54 : ptr_fir_lms_delay_line_buffer_len typ=int8_ bnd=b stl=DM 55 : ptr_fir_lms_coeffs_buffer_len typ=int8_ bnd=b stl=DM 56 : ptr_fir_lms_coeffs_ptr_start typ=int8_ bnd=b stl=DM 57 : __extDM_int64_ typ=int8_ bnd=b stl=DM 58 : __rd___sp typ=dmaddr_ bnd=m 60 : __ptr_cSensor_32 typ=dmaddr_ val=0a bnd=m adro=35 62 : __ptr_accSensor_32 typ=dmaddr_ val=0a bnd=m adro=36 64 : __ptr_c_block_pre typ=dmaddr_ val=0a bnd=m adro=37 66 : __ptr_acc_block_pre typ=dmaddr_ val=0a bnd=m adro=38 67 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ bnd=m 68 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ val=0a bnd=m adro=39 70 : __ptr_ptr_fir_lms_coeffs typ=dmaddr_ val=0a bnd=m adro=41 72 : __ptr_acc_block_filt typ=dmaddr_ val=0a bnd=m adro=43 74 : __ptr_out_32 typ=dmaddr_ val=0a bnd=m adro=44 76 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=45 77 : __ct_0 typ=uint1_ val=0f bnd=m 78 : __la typ=dmaddr_ bnd=p tref=dmaddr___ 79 : cSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__ 80 : accSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__ 81 : output_mode typ=int32_ bnd=p tref=OutputMode__ 82 : cSensor typ=dmaddr_ bnd=p tref=__PDMB__sshort__ 83 : accSensor typ=dmaddr_ bnd=p tref=__PDMB__sshort__ 84 : out_16 typ=dmaddr_ bnd=p tref=__PDMB__sshort__ 92 : __tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=int32_ bnd=m tref=__sint__ 97 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__ 99 : __inl_p_h typ=dmaddr_ bnd=m tref=__P__sint__ 102 : __inl_acc1_A typ=int72_ bnd=m tref=accum_t__ 103 : __inl_acc1_B typ=int72_ bnd=m tref=accum_t__ 111 : __inl_acc1_C typ=int72_ bnd=m tref=accum_t__ 118 : __inl_p_h0 typ=dmaddr_ bnd=m tref=__P__sint__ 119 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__ 120 : __inl_p_x1 typ=dmaddr_ bnd=m tref=__PDMB__sint__ 124 : __inl_acc_C typ=int72_ bnd=m tref=accum_t__ 125 : __inl_prod typ=int32_ bnd=m tref=__sint__ 127 : __inl_h0 typ=int32_ bnd=m tref=__sint__ 128 : __inl_h1 typ=int32_ bnd=m tref=__sint__ 129 : __inl_acc_A typ=int72_ bnd=m tref=accum_t__ 130 : __inl_acc_B typ=int72_ bnd=m tref=accum_t__ 137 : __ct_2 typ=int32_ val=2f bnd=m 141 : __fch___extDM_int16_ typ=int16_ bnd=m 143 : __ct_16 typ=int32_ val=16f bnd=m 145 : __tmp typ=int32_ bnd=m 156 : __fch___extDM_int16_ typ=int16_ bnd=m 160 : __tmp typ=int32_ bnd=m 202 : __ct_0 typ=int32_ val=0f bnd=m 205 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int32_ bnd=m 206 : _Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi typ=dmaddr_ val=0r bnd=m 208 : __link typ=dmaddr_ bnd=m 212 : __fch_ptr_fir_lms_delay_line_ptr_current typ=dmaddr_ bnd=m 216 : __fch_ptr_fir_lms_delay_line_ptr_start typ=dmaddr_ bnd=m 220 : __fch_ptr_fir_lms_coeffs_ptr_current typ=dmaddr_ bnd=m 224 : __fch_ptr_fir_lms_delay_line_buffer_len typ=int32_ bnd=m 228 : __fch_ptr_fir_lms_coeffs_buffer_len typ=int32_ bnd=m 237 : __fchtmp typ=int32_ bnd=m 238 : __fchtmp typ=int32_ bnd=m 248 : __fchtmp typ=int32_ bnd=m 249 : __fchtmp typ=int32_ bnd=m 259 : __tmp typ=int72_ bnd=m 261 : __tmp typ=int72_ bnd=m 275 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int32_ bnd=m 280 : __tmp typ=int32_ bnd=m 291 : __fch_ptr_fir_lms_coeffs_ptr_start typ=dmaddr_ bnd=m 328 : __fch__ZL2mu typ=int32_ bnd=m 333 : __fchtmp typ=int64_ bnd=m 339 : __fchtmp typ=int32_ bnd=m 340 : __tmp typ=int72_ bnd=m 342 : __fchtmp typ=int32_ bnd=m 343 : __tmp typ=int72_ bnd=m 357 : __tmp typ=int32_ bnd=m 358 : __tmp typ=int32_ bnd=m 359 : __tmp typ=int64_ bnd=m 378 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int32_ bnd=m 382 : __tmp typ=int72_ bnd=m 383 : __tmp typ=int32_ bnd=m 384 : __tmp typ=int16_ bnd=m 424 : __ct_m4 typ=int18_ val=-4f bnd=m 425 : __ct_m8 typ=int18_ val=-8f bnd=m 449 : __vcnt typ=int32_ bnd=m 450 : __ct_m1 typ=int32_ val=-1f bnd=m 451 : __ct_1 typ=int32_ val=1f bnd=m 452 : __cv typ=uint16_ bnd=m 478 : __ptr_ptr_fir_lms_coeffs__a8 typ=dmaddr_ val=8a bnd=m adro=41 481 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__ 509 : __ct_0S0 typ=int18_ val=0S0 bnd=m 510 : __ct_0s0 typ=int18_ val=0s0 bnd=m 511 : __ct_4 typ=int18_ val=4f bnd=m 512 : __ct_8 typ=int18_ val=8f bnd=m 516 : __ct_2 typ=uint2_ val=2f bnd=m 523 : __ct_1 typ=uint2_ val=1f bnd=m 528 : __tmp typ=int72_ bnd=m 533 : __tmp typ=int18_ bnd=m 541 : __trgt typ=uint16_ val=0j bnd=m 542 : __vcnt typ=uint16_ bnd=m 543 : __trgt typ=uint16_ val=0j bnd=m 544 : __vcnt typ=uint16_ bnd=m ] F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ { #594 off=0 (__M_SDMB.6 var=8) st_def () <12>; (__M_WDMA.9 var=11) st_def () <18>; (__M_WDMB.10 var=12) st_def () <20>; (__M_LDMA.12 var=14) st_def () <24>; (__R_SP.24 var=26) st_def () <48>; (__vola.27 var=29) source () <51>; (__extDM.30 var=32) source () <54>; (__extPM.31 var=33) source () <55>; (__sp.32 var=34) source () <56>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.33 var=35) source () <57>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.34 var=36) source () <58>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.35 var=37) source () <59>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.36 var=38) source () <60>; (ptr_fir_lms_delay_line.37 var=39) source () <61>; (__extDM_BufferPtrDMB.38 var=40) source () <62>; (ptr_fir_lms_coeffs.39 var=41) source () <63>; (__extDM_BufferPtr.40 var=42) source () <64>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.41 var=43) source () <65>; (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.42 var=44) source () <66>; (_ZL2mu.43 var=45) source () <67>; (__extDM_int32_.44 var=46) source () <68>; (__extDM_int16_.45 var=47) source () <69>; (__extDM_void.46 var=48) source () <70>; (__extPM_void.47 var=49) source () <71>; (ptr_fir_lms_delay_line_ptr_current.48 var=50) source () <72>; (__extDM___PDMint32_.49 var=51) source () <73>; (ptr_fir_lms_delay_line_ptr_start.50 var=52) source () <74>; (ptr_fir_lms_coeffs_ptr_current.51 var=53) source () <75>; (ptr_fir_lms_delay_line_buffer_len.52 var=54) source () <76>; (ptr_fir_lms_coeffs_buffer_len.53 var=55) source () <77>; (ptr_fir_lms_coeffs_ptr_start.54 var=56) source () <78>; (__extDM_int64_.55 var=57) source () <79>; (__ptr_cSensor_32.57 var=60) const () <81>; (__ptr_accSensor_32.59 var=62) const () <83>; (__ptr_c_block_pre.61 var=64) const () <85>; (__ptr_acc_block_pre.63 var=66) const () <87>; (__ptr_ptr_fir_lms_delay_line.65 var=68) const () <89>; (__ct_0.75 var=77) const () <99>; (__la.77 var=78 stl=LR off=0) inp () <101>; (__la.78 var=78) deassign (__la.77) <102>; (cSensorSignal.80 var=79 stl=A off=0) inp () <104>; (accSensorSignal.83 var=80 stl=A off=1) inp () <107>; (output_mode.86 var=81 stl=RA off=0) inp () <110>; (cSensor.89 var=82 stl=A off=4) inp () <113>; (cSensor.90 var=82) deassign (cSensor.89) <114>; (accSensor.92 var=83 stl=A off=5) inp () <116>; (accSensor.93 var=83) deassign (accSensor.92) <117>; (out_16.95 var=84 stl=__spill_WDMA off=0) inp () <119>; (out_16.96 var=84) deassign (out_16.95) <120>; (__rd___sp.98 var=58) rd_res_reg (__R_SP.24 __sp.32) <122>; (__R_SP.102 var=26 __sp.103 var=34) wr_res_reg (__rt.2219 __sp.32) <126>; (__fch___extDM_int16_.246 var=141 __extDM_int16_.247 var=47 __vola.248 var=29) load (__M_SDMB.6 cSensor.90 __extDM_int16_.45 __vola.27) <270>; (__ct_16.250 var=143) const () <272>; (__M_WDMA.258 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.259 var=35) store (__tmp.2415 __ptr_cSensor_32.57 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.33) <280>; (__fch___extDM_int16_.265 var=156 __extDM_int16_.266 var=47 __vola.267 var=29) load (__M_SDMB.6 accSensor.93 __extDM_int16_.247 __vola.248) <286>; (__M_WDMA.277 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.278 var=36) store (__tmp.2420 __ptr_accSensor_32.59 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.34) <296>; (__M_WDMA.563 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564 var=37) store (__tmp.2415 __ptr_c_block_pre.61 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.35) <494>; (__M_WDMA.576 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.577 var=38) store (__tmp.2420 __ptr_acc_block_pre.63 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.36) <506>; (_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi.766 var=206) const () <608>; (__link.768 var=208) dmaddr__call_dmaddr_ (_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi.766) <610>; (__rt.2219 var=481) __Pvoid__pl___Pvoid_int18_ (__rd___sp.98 __ct_0S0.2408) <1905>; (__ct_0S0.2408 var=509) const () <2172>; (__ct_2.2414 var=516) const () <2183>; (__tmp.2415 var=145) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.246 __ct_16.250 __ct_2.2414) <2184>; (__tmp.2420 var=160) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.265 __ct_16.250 __ct_2.2414) <2192>; call { (__ptr_ptr_fir_lms_delay_line.760 var=67 stl=A off=4) assign (__ptr_ptr_fir_lms_delay_line.65) <602>; (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.765 var=205 stl=RA off=0) assign (__tmp.2420) <607>; (__link.769 var=208 stl=LR off=0) assign (__link.768) <611>; (_ZL2mu.770 var=45 __extDM.771 var=32 __extDM_BufferPtr.772 var=42 __extDM_BufferPtrDMB.773 var=40 __extDM___PDMint32_.774 var=51 __extDM_int16_.775 var=47 __extDM_int32_.776 var=46 __extDM_int64_.777 var=57 __extDM_void.778 var=48 __extPM.779 var=33 __extPM_void.780 var=49 ptr_fir_lms_coeffs.781 var=41 ptr_fir_lms_coeffs_buffer_len.782 var=55 ptr_fir_lms_coeffs_ptr_current.783 var=53 ptr_fir_lms_coeffs_ptr_start.784 var=56 ptr_fir_lms_delay_line.785 var=39 ptr_fir_lms_delay_line_buffer_len.786 var=54 ptr_fir_lms_delay_line_ptr_current.787 var=50 ptr_fir_lms_delay_line_ptr_start.788 var=52 __vola.789 var=29) F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi (__link.769 __ptr_ptr_fir_lms_delay_line.760 __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.765 _ZL2mu.43 __extDM.30 __extDM_BufferPtr.40 __extDM_BufferPtrDMB.38 __extDM___PDMint32_.49 __extDM_int16_.266 __extDM_int32_.44 __extDM_int64_.55 __extDM_void.46 __extPM.31 __extPM_void.47 ptr_fir_lms_coeffs.39 ptr_fir_lms_coeffs_buffer_len.53 ptr_fir_lms_coeffs_ptr_current.51 ptr_fir_lms_coeffs_ptr_start.54 ptr_fir_lms_delay_line.37 ptr_fir_lms_delay_line_buffer_len.52 ptr_fir_lms_delay_line_ptr_current.48 ptr_fir_lms_delay_line_ptr_start.50 __vola.267) <612>; } #14 off=1 #616 off=2 (__ptr_ptr_fir_lms_coeffs.67 var=70) const () <91>; (__ct_2.242 var=137) const () <266>; (__ct_0.761 var=202) const () <603>; (__fch_ptr_fir_lms_delay_line_ptr_current.799 var=212) load (__M_WDMB.10 __rt.2329 ptr_fir_lms_delay_line_ptr_current.787) <622>; (__fch_ptr_fir_lms_delay_line_ptr_start.804 var=216) load (__M_WDMB.10 __rt.2351 ptr_fir_lms_delay_line_ptr_start.788) <627>; (__fch_ptr_fir_lms_coeffs_ptr_current.809 var=220) load (__M_WDMA.9 __ptr_ptr_fir_lms_coeffs__a8.2205 ptr_fir_lms_coeffs_ptr_current.783) <632>; (__fch_ptr_fir_lms_delay_line_buffer_len.814 var=224) load (__M_WDMB.10 __rt.2373 ptr_fir_lms_delay_line_buffer_len.786) <637>; (__fch_ptr_fir_lms_coeffs_buffer_len.819 var=228) load (__M_WDMA.9 __ptr_ptr_fir_lms_coeffs.67 ptr_fir_lms_coeffs_buffer_len.782) <642>; (__ct_m4.2076 var=424) const () <1738>; (__ct_m1.2137 var=450) const () <1790>; (__vcnt.2138 var=449) __sint__pl___sint___sint (__fch_ptr_fir_lms_coeffs_buffer_len.819 __ct_m1.2137) <1792>; (__ct_1.2140 var=451) const () <1794>; (__vcnt.2141 var=449) __sint__pl___sint___sint (__vcnt.2436 __ct_1.2140) <1796>; (__cv.2142 var=452) uint16__uint16____sint (__vcnt.2141) <1797>; (__ptr_ptr_fir_lms_coeffs__a8.2205 var=478) const () <1861>; (__rt.2329 var=481) __Pvoid__pl___Pvoid_int18_ (__ptr_ptr_fir_lms_delay_line.65 __ct_8.2411) <2045>; (__rt.2351 var=481) __Pvoid__mi___Pvoid_int18_ (__rt.2329 __ct_4.2410) <2073>; (__rt.2373 var=481) __Pvoid__mi___Pvoid_int18_ (__rt.2351 __ct_4.2410) <2101>; (__rt.2395 var=481) __Pvoid__pl___Pvoid_int18_ (__ptr_ptr_fir_lms_coeffs.67 __ct_4.2410) <2129>; (__ct_4.2410 var=511) const () <2176>; (__ct_8.2411 var=512) const () <2178>; (__tmp.2425 var=533) int72__shift_int72__int72__uint2_ (__fch_ptr_fir_lms_delay_line_buffer_len.814 __ct_2.242 __ct_2.2414) <2200>; (__ct_1.2429 var=523) const () <2207>; (__tmp.2435 var=528) int72__shift_int72__int72__uint2_ (__vcnt.2138 __ct_1.2140 __ct_1.2429) <2216>; (__vcnt.2436 var=449) int32__extract_high_int72_ (__tmp.2435) <2217>; (__trgt.2444 var=541) const () <2308>; () void_doloop_uint16__uint16_ (__cv.2142 __trgt.2444) <2309>; (__vcnt.2445 var=542) undefined () <2310>; for { { (__inl_p_x0.883 var=97) entry (__inl_p_x0.1048 __fch_ptr_fir_lms_delay_line_ptr_current.799) <706>; (__inl_p_h.885 var=99) entry (__inl_p_h.1052 __fch_ptr_fir_lms_coeffs_ptr_current.809) <708>; (__inl_acc1_A.888 var=102) entry (__inl_acc1_A.1058 __ct_0.761) <711>; (__inl_acc1_B.889 var=103) entry (__inl_acc1_B.1060 __ct_0.761) <712>; } #17 { (__fchtmp.924 var=237) load (__M_WDMB.10 __inl_p_x0.883 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <747>; (__fchtmp.925 var=238) load (__M_WDMA.9 __inl_p_h.885 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <748>; (__fchtmp.935 var=248) load (__M_WDMB.10 __inl_p_x0.2015 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <758>; (__fchtmp.936 var=249) load (__M_WDMA.9 __rt.2263 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <759>; (__inl_acc1_A.947 var=102) accum_t__pl_accum_t_accum_t (__inl_acc1_A.888 __tmp.2028) <770>; (__inl_acc1_B.949 var=103) accum_t__pl_accum_t_accum_t (__inl_acc1_B.889 __tmp.2033) <772>; (__inl_p_x0.2015 var=97) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.883 __ct_m4.2076 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2425) <1624>; (__inl_p_x0.2023 var=97) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.2015 __ct_m4.2076 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2425) <1635>; (__tmp.2028 var=259) int72__multss_int32__int32__uint1_ (__fchtmp.924 __fchtmp.925 __ct_0.75) <1643>; (__tmp.2033 var=261) int72__multss_int32__int32__uint1_ (__fchtmp.935 __fchtmp.936 __ct_0.75) <1651>; (__rt.2263 var=481) __Pvoid__pl___Pvoid_int18_ (__inl_p_h.885 __ct_4.2410) <1961>; (__rt.2285 var=481) __Pvoid__pl___Pvoid_int18_ (__rt.2263 __ct_4.2410) <1989>; } #404 off=3 { () for_count (__vcnt.2445) <777>; (__inl_p_x0.1048 var=97 __inl_p_x0.1049 var=97) exit (__inl_p_x0.2023) <825>; (__inl_p_h.1052 var=99 __inl_p_h.1053 var=99) exit (__rt.2285) <827>; (__inl_acc1_A.1058 var=102 __inl_acc1_A.1059 var=102) exit (__inl_acc1_A.947) <830>; (__inl_acc1_B.1060 var=103 __inl_acc1_B.1061 var=103) exit (__inl_acc1_B.949) <831>; } #19 } #16 rng=[1,65535] #99 off=4 (__ptr_acc_block_filt.69 var=72) const () <93>; (__ptr_out_32.71 var=74) const () <95>; (__ptr_mu.73 var=76) const () <97>; (__inl_acc1_C.1130 var=111) accum_t__pl_accum_t_accum_t (__inl_acc1_A.1059 __inl_acc1_B.1061) <866>; (__tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1131 var=92) __sint_rnd_saturate_accum_t (__inl_acc1_C.1130) <867>; (__M_WDMB.1135 var=12 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.1136 var=43) store (__tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1131 __ptr_acc_block_filt.69 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.41) <871>; (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.1140 var=275) load (__M_WDMA.9 __ptr_c_block_pre.61 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564) <875>; (__tmp.1145 var=280) __sint__mi___sint___sint (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.1140 __tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1131) <880>; (__M_WDMB.1149 var=12 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1150 var=44) store (__tmp.1145 __ptr_out_32.71 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.42) <884>; (__fch_ptr_fir_lms_coeffs_ptr_start.1166 var=291) load (__M_WDMA.9 __rt.2395 ptr_fir_lms_coeffs_ptr_start.784) <900>; (__fch__ZL2mu.1214 var=328) load (__M_WDMA.9 __ptr_mu.73 _ZL2mu.770) <948>; (__inl_prod.1216 var=125) __sint_rnd_saturate_accum_t (__inl_acc_C.2046) <950>; (__inl_p_x1.2041 var=120) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch_ptr_fir_lms_delay_line_ptr_current.799 __ct_m4.2076 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2425) <1662>; (__inl_acc_C.2046 var=124) int72__multss_int32__int32__uint1_ (__fch__ZL2mu.1214 __tmp.1145 __ct_0.75) <1670>; (__ct_m8.2077 var=425) const () <1740>; (__trgt.2446 var=543) const () <2311>; () void_doloop_uint16__uint16_ (__cv.2142 __trgt.2446) <2312>; (__vcnt.2447 var=544) undefined () <2313>; for { { (_ZL2mu.1236 var=45) entry (_ZL2mu.1381 _ZL2mu.770) <970>; (__extDM_int32_.1237 var=46) entry (__extDM_int32_.1383 __extDM_int32_.776) <971>; (ptr_fir_lms_delay_line_buffer_len.1245 var=54) entry (ptr_fir_lms_delay_line_buffer_len.1399 ptr_fir_lms_delay_line_buffer_len.786) <979>; (ptr_fir_lms_coeffs_buffer_len.1246 var=55) entry (ptr_fir_lms_coeffs_buffer_len.1401 ptr_fir_lms_coeffs_buffer_len.782) <980>; (__extDM_int64_.1248 var=57) entry (__extDM_int64_.1405 __extDM_int64_.777) <982>; (__inl_p_h0.1290 var=118) entry (__inl_p_h0.1489 __fch_ptr_fir_lms_coeffs_ptr_start.1166) <1024>; (__inl_p_x0.1291 var=119) entry (__inl_p_x0.1491 __fch_ptr_fir_lms_delay_line_ptr_current.799) <1025>; (__inl_p_x1.1292 var=120) entry (__inl_p_x1.1493 __inl_p_x1.2041) <1026>; } #22 { (__fchtmp.1308 var=333) load (__M_LDMA.12 __inl_p_h0.1290 _ZL2mu.1236 __extDM_int32_.1237 __extDM_int64_.1248 ptr_fir_lms_coeffs_buffer_len.1246 ptr_fir_lms_delay_line_buffer_len.1245) <1042>; (__inl_h0.1310 var=127 __inl_h1.1311 var=128) void_lldecompose___ulonglong___sint___sint (__fchtmp.1308) <1044>; (__fchtmp.1314 var=339) load (__M_WDMB.10 __inl_p_x0.1291 _ZL2mu.1236 __extDM_int32_.1237 ptr_fir_lms_coeffs_buffer_len.1246 ptr_fir_lms_delay_line_buffer_len.1245) <1047>; (__inl_acc_A.1316 var=129) accum_t__pl_accum_t_accum_t (__inl_h0.1310 __tmp.2051) <1049>; (__fchtmp.1317 var=342) load (__M_WDMB.10 __inl_p_x1.1292 _ZL2mu.1236 __extDM_int32_.1237 ptr_fir_lms_coeffs_buffer_len.1246 ptr_fir_lms_delay_line_buffer_len.1245) <1050>; (__inl_acc_B.1319 var=130) accum_t__pl_accum_t_accum_t (__inl_h1.1311 __tmp.2056) <1052>; (__tmp.1332 var=357) __sint_rnd_saturate_accum_t (__inl_acc_A.1316) <1065>; (__tmp.1333 var=358) __sint_rnd_saturate_accum_t (__inl_acc_B.1319) <1066>; (__tmp.1334 var=359) __ulonglong_llcompose___sint___sint (__tmp.1332 __tmp.1333) <1067>; (__M_LDMA.1336 var=14 _ZL2mu.1337 var=45 __extDM_int32_.1338 var=46 __extDM_int64_.1339 var=57 ptr_fir_lms_coeffs_buffer_len.1340 var=55 ptr_fir_lms_delay_line_buffer_len.1341 var=54) store (__tmp.1334 __inl_p_h0.1290 _ZL2mu.1236 __extDM_int32_.1237 __extDM_int64_.1248 ptr_fir_lms_coeffs_buffer_len.1246 ptr_fir_lms_delay_line_buffer_len.1245) <1069>; (__tmp.2051 var=340) int72__multss_int32__int32__uint1_ (__inl_prod.1216 __fchtmp.1314 __ct_0.75) <1678>; (__tmp.2056 var=343) int72__multss_int32__int32__uint1_ (__inl_prod.1216 __fchtmp.1317 __ct_0.75) <1686>; (__inl_p_x0.2064 var=119) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.1291 __ct_m8.2077 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2425) <1697>; (__inl_p_x1.2072 var=120) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x1.1292 __ct_m8.2077 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2425) <1708>; (__rt.2307 var=481) __Pvoid__pl___Pvoid_int18_ (__inl_p_h0.1290 __ct_8.2411) <2017>; } #474 off=5 { () for_count (__vcnt.2447) <1077>; (_ZL2mu.1381 var=45 _ZL2mu.1382 var=45) exit (_ZL2mu.1337) <1094>; (__extDM_int32_.1383 var=46 __extDM_int32_.1384 var=46) exit (__extDM_int32_.1338) <1095>; (ptr_fir_lms_delay_line_buffer_len.1399 var=54 ptr_fir_lms_delay_line_buffer_len.1400 var=54) exit (ptr_fir_lms_delay_line_buffer_len.1341) <1103>; (ptr_fir_lms_coeffs_buffer_len.1401 var=55 ptr_fir_lms_coeffs_buffer_len.1402 var=55) exit (ptr_fir_lms_coeffs_buffer_len.1340) <1104>; (__extDM_int64_.1405 var=57 __extDM_int64_.1406 var=57) exit (__extDM_int64_.1339) <1106>; (__inl_p_h0.1489 var=118 __inl_p_h0.1490 var=118) exit (__rt.2307) <1148>; (__inl_p_x0.1491 var=119 __inl_p_x0.1492 var=119) exit (__inl_p_x0.2064) <1149>; (__inl_p_x1.1493 var=120 __inl_p_x1.1494 var=120) exit (__inl_p_x1.2072) <1150>; } #24 } #21 rng=[1,65535] #36 off=6 nxt=-2 (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1712 var=378) load (__M_WDMB.10 __ptr_out_32.71 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1150) <1355>; (__tmp.1717 var=383) __sint_rnd_saturate_accum_t (__tmp.2430) <1360>; (__tmp.1718 var=384) __sshort___sshort___sint (__tmp.1717) <1361>; (__M_SDMB.1724 var=8 __extDM_int16_.1725 var=47 __vola.1726 var=29) store (__tmp.1718 out_16.96 __extDM_int16_.775 __vola.789) <1367>; (__rd___sp.1913 var=58) rd_res_reg (__R_SP.24 __sp.103) <1467>; (__R_SP.1917 var=26 __sp.1918 var=34) wr_res_reg (__rt.2241 __sp.103) <1471>; () void_ret_dmaddr_ (__la.78) <1472>; () sink (__vola.1726) <1473>; () sink (__extDM.771) <1476>; () sink (__extPM.779) <1477>; () sink (__sp.1918) <1478>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.259) <1479>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.278) <1480>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564) <1481>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.577) <1482>; () sink (ptr_fir_lms_delay_line.785) <1483>; () sink (__extDM_BufferPtrDMB.773) <1484>; () sink (ptr_fir_lms_coeffs.781) <1485>; () sink (__extDM_BufferPtr.772) <1486>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.1136) <1487>; () sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1150) <1488>; () sink (_ZL2mu.1382) <1489>; () sink (__extDM_int32_.1384) <1490>; () sink (__extDM_int16_.1725) <1491>; () sink (__extDM_void.778) <1492>; () sink (__extPM_void.780) <1493>; () sink (ptr_fir_lms_delay_line_ptr_current.787) <1494>; () sink (__extDM___PDMint32_.774) <1495>; () sink (ptr_fir_lms_delay_line_ptr_start.788) <1496>; () sink (ptr_fir_lms_coeffs_ptr_current.783) <1497>; () sink (ptr_fir_lms_delay_line_buffer_len.1400) <1498>; () sink (ptr_fir_lms_coeffs_buffer_len.1402) <1499>; () sink (ptr_fir_lms_coeffs_ptr_start.784) <1500>; () sink (__extDM_int64_.1406) <1501>; () sink (__ct_0.75) <1502>; (__rt.2241 var=481) __Pvoid__pl___Pvoid_int18_ (__rd___sp.1913 __ct_0s0.2409) <1933>; (__ct_0s0.2409 var=510) const () <2174>; (__tmp.2430 var=382) int72__shift_int72__int72__uint2_ (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1712 __ct_16.250 __ct_1.2429) <2208>; } #0 0 : 'signal_processing\\signal_path.c'; ---------- 0 : (0,343:0,0); 14 : (0,381:4,26); 16 : (0,384:23,43); 21 : (0,388:4,85); 36 : (0,396:0,113); 99 : (0,388:4,83); 404 : (0,384:23,56); 474 : (0,388:4,0); 594 : (0,381:4,26); 616 : (0,384:23,43); ---------- 85 : (0,386:16,0); 87 : (0,381:67,0); 89 : (0,384:23,0); 91 : (0,384:23,0); 93 : (0,384:4,0); 95 : (0,386:4,0); 122 : (0,343:5,0); 126 : (0,343:5,0); 266 : (0,368:39,0); 270 : (0,368:39,11); 272 : (0,368:47,0); 280 : (0,368:18,11); 286 : (0,369:42,12); 296 : (0,369:20,12); 494 : (0,374:20,19); 506 : (0,375:22,20); 602 : (0,381:42,0); 603 : (0,381:81,0); 607 : (0,381:80,0); 610 : (0,381:4,26); 611 : (0,381:4,0); 612 : (0,381:4,26); 622 : (0,384:23,33); 627 : (0,384:23,34); 632 : (0,384:23,35); 637 : (0,384:23,36); 642 : (0,384:23,37); 706 : (0,384:23,43); 708 : (0,384:23,43); 711 : (0,384:23,43); 712 : (0,384:23,43); 747 : (0,384:23,43); 748 : (0,384:23,44); 758 : (0,384:23,49); 759 : (0,384:23,50); 770 : (0,384:23,55); 772 : (0,384:23,56); 777 : (0,384:23,59); 825 : (0,384:23,59); 827 : (0,384:23,59); 830 : (0,384:23,59); 831 : (0,384:23,59); 866 : (0,384:23,60); 867 : (0,384:23,61); 871 : (0,384:18,64); 875 : (0,386:27,65); 880 : (0,386:31,65); 884 : (0,386:10,65); 900 : (0,388:4,73); 948 : (0,388:4,82); 950 : (0,388:4,83); 970 : (0,388:4,85); 971 : (0,388:4,85); 979 : (0,388:4,85); 980 : (0,388:4,85); 982 : (0,388:4,85); 1024 : (0,388:4,85); 1025 : (0,388:4,85); 1026 : (0,388:4,85); 1042 : (0,388:4,85); 1044 : (0,388:4,85); 1047 : (0,388:4,88); 1049 : (0,388:4,88); 1050 : (0,388:4,89); 1052 : (0,388:4,89); 1065 : (0,388:4,92); 1066 : (0,388:4,92); 1067 : (0,388:4,92); 1069 : (0,388:4,92); 1077 : (0,388:4,96); 1094 : (0,388:4,96); 1095 : (0,388:4,96); 1103 : (0,388:4,96); 1104 : (0,388:4,96); 1106 : (0,388:4,96); 1148 : (0,388:4,96); 1149 : (0,388:4,96); 1150 : (0,388:4,96); 1355 : (0,393:48,103); 1360 : (0,393:20,103); 1361 : (0,393:18,103); 1367 : (0,393:14,103); 1467 : (0,396:0,0); 1471 : (0,396:0,113); 1472 : (0,396:0,113); 1624 : (0,384:23,48); 1635 : (0,384:23,54); 1643 : (0,384:23,55); 1651 : (0,384:23,56); 1662 : (0,388:4,80); 1670 : (0,388:4,82); 1678 : (0,388:4,88); 1686 : (0,388:4,89); 1697 : (0,388:4,90); 1708 : (0,388:4,91); 1738 : (0,384:23,0); 1740 : (0,388:4,0); 1861 : (0,384:23,0); 1905 : (0,343:5,0); 1933 : (0,396:0,0); 1961 : (0,384:23,0); 1989 : (0,384:23,0); 2017 : (0,388:4,0); 2045 : (0,384:23,0); 2073 : (0,384:23,0); 2101 : (0,384:23,0); 2129 : (0,388:4,0); 2172 : (0,343:5,0); 2174 : (0,396:0,0); 2176 : (0,384:23,0); 2178 : (0,388:4,0); 2183 : (0,368:44,0); 2184 : (0,368:44,11); 2192 : (0,369:47,12); 2200 : (0,384:23,48); 2207 : (0,393:53,0); 2208 : (0,393:53,103); 2309 : (0,384:23,59); 2312 : (0,388:4,96);