// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Tue Jan 20 09:59:26 2026 // Copyright 2014-2025 Synopsys, Inc. All rights reserved. // C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32 /*** !! int main() F_main : user_defined, called { fnm : "main" 'int main()'; arg : ( dmaddr_:i int32_:r ); loc : ( LR[0] RA[0] ); vac : ( srIM[0] ); frm : ( l=88 b=8 ); } **** !! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int) F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called { fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)'; arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i ); loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] ); vac : ( srIM[0] ); } !! extern FILE *fopen(const char *, const char *) Ffopen : user_defined, called { fnm : "fopen" 'FILE *fopen(const char *, const char *)'; arg : ( dmaddr_:i dmaddr_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] A[0] A[1] A[2] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int feof(FILE *) Ffeof : user_defined, called { fnm : "feof" 'int feof(FILE *)'; arg : ( dmaddr_:i int32_:r dmaddr_:i ); loc : ( LR[0] RA[0] A[0] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int fscanf(FILE *, const char *, ...) Ffscanf : user_defined, called, varargs { fnm : "fscanf" 'int fscanf(FILE *, const char *, ...)'; arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] RA[0] A[0] A[1] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *) F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called { fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)'; arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i ); loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] ); vac : ( srIM[0] ); } !! extern int fprintf(FILE *, const char *, ...) Ffprintf : user_defined, called, varargs { fnm : "fprintf" 'int fprintf(FILE *, const char *, ...)'; arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i ); loc : ( LR[0] RA[0] A[0] A[1] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } !! extern int fclose(FILE *) Ffclose : user_defined, called { fnm : "fclose" 'int fclose(FILE *)'; arg : ( dmaddr_:i int32_:r dmaddr_:i ); loc : ( LR[0] RA[0] A[0] ); vac : ( srIM[0] ); llv : 0 0 0 0 0 ; } ***/ [ 0 : _main typ=uint20_ bnd=e stl=PM tref=__sint____ 8 : __M_SDMB typ=int16_ bnd=d stl=SDMB 11 : __M_WDMA typ=int32_ bnd=d stl=WDMA 14 : __M_LDMA typ=int64_ bnd=d stl=LDMA 26 : __R_SP typ=dmaddr_ bnd=d stl=SP 29 : __vola typ=uint20_ bnd=b stl=PM 32 : __extDM typ=int8_ bnd=b stl=DM 33 : __extPM typ=uint20_ bnd=b stl=PM 34 : __sp typ=dmaddr_ bnd=b stl=SP 35 : b0 typ=int8_ val=8t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA 36 : b1 typ=int8_ val=48t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA 37 : _ZL16corrupted_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA 38 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM 39 : _ZL22reference_noise_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA 40 : _ZL13__str8a4fef85 typ=int8_ bnd=i sz=47 algn=1 stl=DMA tref=__A47__cchar_DMA 41 : _ZL13__str00f02b8f typ=int8_ bnd=i sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA 42 : _ZL13__strff0646f3 typ=int8_ bnd=i sz=43 algn=1 stl=DMA tref=__A43__cchar_DMA 43 : _ZL13__str8a32ec0e typ=int8_ bnd=i sz=54 algn=1 stl=DMA tref=__A54__cchar_DMA 44 : _ZL13__str00f52cca typ=int8_ bnd=i sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA 45 : _ZL13__str41232700 typ=int8_ bnd=i sz=3 algn=1 stl=DMA tref=__A3__cchar_DMA 46 : d0 typ=int8_ val=88t0 bnd=a sz=4 algn=4 stl=DMA tref=__sint_DMA 47 : d1 typ=int8_ val=92t0 bnd=a sz=4 algn=4 stl=DMA tref=__sint_DMA 48 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB 49 : __extDM_int16_ typ=int8_ bnd=b stl=DM 50 : _ZZ4mainvE4mode typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=OutputMode_DMA 51 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB 52 : _ZL13__str2eb09b76 typ=int8_ bnd=i sz=4 algn=1 stl=DMA tref=__A4__cchar_DMA 53 : __extDM_void typ=int8_ bnd=b stl=DM 54 : __extPM_void typ=uint20_ bnd=b stl=PM 55 : __extDM_int64_ typ=int8_ bnd=b stl=DM 56 : __extDM_int8_ typ=int8_ bnd=b stl=DM 57 : __extPM_FILE typ=uint20_ bnd=b stl=PM 58 : __extDM_int32_ typ=int8_ bnd=b stl=DM 59 : __rd___sp typ=dmaddr_ bnd=m 60 : __ptr_corrupted_signal typ=dmaddr_ bnd=m 61 : __ptr_corrupted_signal typ=dmaddr_ val=0a bnd=m adro=37 62 : __ptr_reference_noise_signal typ=dmaddr_ bnd=m 63 : __ptr_reference_noise_signal typ=dmaddr_ val=0a bnd=m adro=39 64 : __ptr___str8a4fef85 typ=dmaddr_ bnd=m 65 : __ptr___str8a4fef85 typ=dmaddr_ val=0a bnd=m adro=40 66 : __ptr___str00f02b8f typ=dmaddr_ bnd=m 67 : __ptr___str00f02b8f typ=dmaddr_ val=0a bnd=m adro=41 68 : __ptr___strff0646f3 typ=dmaddr_ bnd=m 69 : __ptr___strff0646f3 typ=dmaddr_ val=0a bnd=m adro=42 70 : __ptr___str8a32ec0e typ=dmaddr_ bnd=m 71 : __ptr___str8a32ec0e typ=dmaddr_ val=0a bnd=m adro=43 72 : __ptr___str00f52cca typ=dmaddr_ bnd=m 73 : __ptr___str00f52cca typ=dmaddr_ val=0a bnd=m adro=44 74 : __ptr___str41232700 typ=dmaddr_ bnd=m 75 : __ptr___str41232700 typ=dmaddr_ val=0a bnd=m adro=45 77 : __ct_8388608 typ=dmaddr_ val=8388608f bnd=m 79 : __ptr_mode typ=dmaddr_ val=0a bnd=m adro=50 80 : __ptr_output_port typ=dmaddr_ bnd=m 81 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m 82 : __ptr___str2eb09b76 typ=dmaddr_ bnd=m 83 : __ptr___str2eb09b76 typ=dmaddr_ val=0a bnd=m adro=52 84 : __ct_0 typ=uint1_ val=0f bnd=m 85 : __la typ=dmaddr_ bnd=p tref=dmaddr___ 86 : __rt typ=int32_ bnd=p tref=__sint__ 90 : __ptr_b0 typ=dmaddr_ bnd=m 94 : __ptr_b1 typ=dmaddr_ bnd=m 98 : __ptr_d0 typ=dmaddr_ bnd=m 102 : __ptr_d1 typ=dmaddr_ bnd=m 106 : fp1 typ=dmaddr_ bnd=m tref=__PFILE__ 107 : fp2 typ=dmaddr_ bnd=m tref=__PFILE__ 108 : fp3 typ=dmaddr_ bnd=m tref=__PFILE__ 113 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m 115 : __ct_0 typ=int32_ val=0f bnd=m 118 : __ct_0 typ=uint40_ val=0f bnd=m 163 : __ct_2 typ=int32_ val=2f bnd=m 164 : __ct typ=int32_ bnd=m 166 : __ct typ=int32_ bnd=m 167 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m 168 : __ct typ=int64_ bnd=m 170 : __ct typ=int64_ bnd=m 171 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m 172 : __ct typ=int64_ bnd=m 173 : __ct_64 typ=int32_ val=64f bnd=m 174 : __ct typ=int32_ bnd=m 175 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m 177 : __link typ=dmaddr_ bnd=m 178 : fopen typ=dmaddr_ val=0r bnd=m 180 : __link typ=dmaddr_ bnd=m 181 : __tmp typ=dmaddr_ bnd=m 184 : __link typ=dmaddr_ bnd=m 185 : __tmp typ=dmaddr_ bnd=m 188 : __link typ=dmaddr_ bnd=m 189 : __tmp typ=dmaddr_ bnd=m 190 : feof typ=dmaddr_ val=0r bnd=m 192 : __link typ=dmaddr_ bnd=m 193 : __tmp typ=int32_ bnd=m 201 : __link typ=dmaddr_ bnd=m 202 : __tmp typ=int32_ bnd=m 205 : __tmp typ=bool bnd=m 206 : __tmp typ=bool bnd=m 213 : fscanf typ=dmaddr_ val=0r bnd=m 215 : __link typ=dmaddr_ bnd=m 216 : __tmp typ=int32_ bnd=m 219 : __link typ=dmaddr_ bnd=m 220 : __tmp typ=int32_ bnd=m 221 : __fch_d0 typ=int32_ bnd=m 222 : __tmp typ=int16_ bnd=m 227 : __fch_d1 typ=int32_ bnd=m 228 : __tmp typ=int16_ bnd=m 242 : __fch__ZZ4mainvE4mode typ=int32_ bnd=m 245 : __tmp typ=dmaddr_ bnd=m 248 : __tmp typ=dmaddr_ bnd=m 249 : _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=dmaddr_ val=0r bnd=m 251 : __link typ=dmaddr_ bnd=m 261 : __fch__ZL11output_port typ=int16_ bnd=m 262 : __fch__ZL11output_port typ=int32_ bnd=m 263 : fprintf typ=dmaddr_ val=0r bnd=m 265 : __link typ=dmaddr_ bnd=m 266 : __tmp typ=int32_ bnd=m 275 : __link typ=dmaddr_ bnd=m 276 : __tmp typ=int32_ bnd=m 284 : __link typ=dmaddr_ bnd=m 285 : __tmp typ=int32_ bnd=m 288 : __tmp typ=bool bnd=m 289 : __tmp typ=bool bnd=m 291 : fclose typ=dmaddr_ val=0r bnd=m 293 : __link typ=dmaddr_ bnd=m 294 : __tmp typ=int32_ bnd=m 297 : __link typ=dmaddr_ bnd=m 298 : __tmp typ=int32_ bnd=m 301 : __link typ=dmaddr_ bnd=m 302 : __tmp typ=int32_ bnd=m 337 : __shv___ptr_input_port typ=dmaddr_ bnd=m 361 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__ 386 : __tmp typ=bool bnd=m 402 : __ct_m88S0 typ=int18_ val=-96S0 bnd=m 403 : __ct_88s0 typ=int18_ val=96s0 bnd=m 404 : __ct_0t0 typ=int18_ val=8t0 bnd=m 405 : __ct_40t0 typ=int18_ val=48t0 bnd=m 408 : __ct_80t0 typ=int18_ val=88t0 bnd=m 411 : __ct_84t0 typ=int18_ val=92t0 bnd=m 414 : __ct_2 typ=int18_ val=2f bnd=m 416 : __ct_8t0 typ=int18_ val=16t0 bnd=m 419 : __ct_16t0 typ=int18_ val=24t0 bnd=m 422 : __ct_24t0 typ=int18_ val=32t0 bnd=m 425 : __ct_32t0 typ=int18_ val=40t0 bnd=m 428 : __ct_48t0 typ=int18_ val=56t0 bnd=m 431 : __ct_56t0 typ=int18_ val=64t0 bnd=m 434 : __ct_64t0 typ=int18_ val=72t0 bnd=m 437 : __ct_72t0 typ=int18_ val=80t0 bnd=m 443 : __tmp typ=uint3_ bnd=m 454 : __true typ=bool val=1f bnd=m 455 : __false typ=bool val=0f bnd=m 456 : __either typ=bool bnd=m 457 : __trgt typ=int10_ val=0j bnd=m 458 : __trgt typ=int10_ val=0j bnd=m 459 : __trgt typ=int10_ val=0j bnd=m 460 : __trgt typ=int10_ val=0j bnd=m 461 : __trgt typ=int10_ val=0j bnd=m ] F_main { #352 off=0 (__M_SDMB.6 var=8) st_def () <12>; (__M_WDMA.9 var=11) st_def () <18>; (__R_SP.24 var=26) st_def () <48>; (__vola.27 var=29) source () <51>; (__extDM.30 var=32) source () <54>; (__extPM.31 var=33) source () <55>; (__sp.32 var=34) source () <56>; (b0.33 var=35) source () <57>; (b1.34 var=36) source () <58>; (_ZL16corrupted_signal.35 var=37) source () <59>; (__extDM_SingleSignalPath.36 var=38) source () <60>; (_ZL22reference_noise_signal.37 var=39) source () <61>; (d0.44 var=46) source () <68>; (d1.45 var=47) source () <69>; (_ZL10input_port.46 var=48) source () <70>; (__extDM_int16_.47 var=49) source () <71>; (_ZZ4mainvE4mode.48 var=50) source () <72>; (_ZL11output_port.49 var=51) source () <73>; (__extDM_void.51 var=53) source () <75>; (__extPM_void.52 var=54) source () <76>; (__extDM_int64_.53 var=55) source () <77>; (__extDM_int8_.54 var=56) source () <78>; (__extPM_FILE.55 var=57) source () <79>; (__extDM_int32_.56 var=58) source () <80>; (__ptr_corrupted_signal.58 var=61) const () <82>; (__ptr_reference_noise_signal.60 var=63) const () <84>; (__ct_0.84 var=84) const () <108>; (__la.86 var=85 stl=LR off=0) inp () <110>; (__la.87 var=85) deassign (__la.86) <111>; (__rd___sp.90 var=59) rd_res_reg (__R_SP.24 __sp.32) <114>; (__R_SP.94 var=26 __sp.95 var=34) wr_res_reg (__rt.1727 __sp.32) <118>; (__rd___sp.96 var=59) rd_res_reg (__R_SP.24 __sp.95) <120>; (__ct_4604930618986332160.123 var=113) const () <147>; (__M_LDMA.128 var=14 b0.129 var=35) store (__ct_4604930618986332160.123 __rt.1749 b0.33) <152>; (__ct_0.130 var=118) const () <153>; (__M_LDMA.135 var=14 b0.136 var=35) store (__ct_0.130 __rt.1913 b0.129) <158>; (__M_LDMA.142 var=14 b0.143 var=35) store (__ct_0.130 __rt.1935 b0.136) <164>; (__M_LDMA.149 var=14 b0.150 var=35) store (__ct_0.130 __rt.1957 b0.143) <170>; (__M_LDMA.156 var=14 b0.157 var=35) store (__ct_0.130 __rt.1979 b0.150) <176>; (__M_LDMA.163 var=14 b1.164 var=36) store (__ct_4604930618986332160.123 __rt.1771 b1.34) <182>; (__M_LDMA.170 var=14 b1.171 var=36) store (__ct_0.130 __rt.2001 b1.164) <188>; (__M_LDMA.177 var=14 b1.178 var=36) store (__ct_0.130 __rt.2023 b1.171) <194>; (__M_LDMA.184 var=14 b1.185 var=36) store (__ct_0.130 __rt.2045 b1.178) <200>; (__M_LDMA.191 var=14 b1.192 var=36) store (__ct_0.130 __rt.2067 b1.185) <206>; (__ct_2.197 var=163) const () <211>; (__ct_4606281698874543309.203 var=167) const () <217>; (__ct_4576918229304087675.209 var=171) const () <223>; (__ct_64.212 var=173) const () <226>; (_Z4initP16SingleSignalPathS0_PdS1_iidddi.215 var=175) const () <229>; (__link.217 var=177) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.215) <231>; (__rt.1727 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.90 __ct_m88S0.2080) <1472>; (__rt.1749 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_0t0.2082) <1500>; (__rt.1771 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_40t0.2083) <1528>; (__rt.1913 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_8t0.2094) <1712>; (__rt.1935 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_16t0.2097) <1740>; (__rt.1957 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_24t0.2100) <1768>; (__rt.1979 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_32t0.2103) <1796>; (__rt.2001 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_48t0.2106) <1824>; (__rt.2023 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_56t0.2109) <1852>; (__rt.2045 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_64t0.2112) <1880>; (__rt.2067 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_72t0.2115) <1908>; (__ct_m88S0.2080 var=402) const () <1969>; (__ct_0t0.2082 var=404) const () <1973>; (__ct_40t0.2083 var=405) const () <1975>; (__ct_8t0.2094 var=416) const () <1997>; (__ct_16t0.2097 var=419) const () <2003>; (__ct_24t0.2100 var=422) const () <2009>; (__ct_32t0.2103 var=425) const () <2015>; (__ct_48t0.2106 var=428) const () <2021>; (__ct_56t0.2109 var=431) const () <2027>; (__ct_64t0.2112 var=434) const () <2033>; (__ct_72t0.2115 var=437) const () <2039>; call { (__ptr_corrupted_signal.193 var=60 stl=A off=0) assign (__ptr_corrupted_signal.58) <207>; (__ptr_reference_noise_signal.194 var=62 stl=A off=1) assign (__ptr_reference_noise_signal.60) <208>; (__ptr_b0.195 var=90 stl=A off=2) assign (__rt.1749) <209>; (__ptr_b1.196 var=94 stl=A off=3) assign (__rt.1771) <210>; (__ct.199 var=164 stl=RA off=0) assign (__ct_2.197) <213>; (__ct.202 var=166 stl=RA off=1) assign (__ct_2.197) <216>; (__ct.205 var=168 stl=AX off=0) assign (__ct_4606281698874543309.203) <219>; (__ct.208 var=170 stl=AX off=1) assign (__ct_4606281698874543309.203) <222>; (__ct.211 var=172 stl=BX off=0) assign (__ct_4576918229304087675.209) <225>; (__ct.214 var=174 stl=RB off=0) assign (__ct_64.212) <228>; (__link.218 var=177 stl=LR off=0) assign (__link.217) <232>; (_ZL10input_port.219 var=48 _ZL11output_port.220 var=51 _ZL16corrupted_signal.221 var=37 _ZL22reference_noise_signal.222 var=39 __extDM.223 var=32 __extDM_SingleSignalPath.224 var=38 __extDM_int16_.225 var=49 __extDM_int32_.226 var=58 __extDM_int64_.227 var=55 __extDM_int8_.228 var=56 __extDM_void.229 var=53 __extPM.230 var=33 __extPM_FILE.231 var=57 __extPM_void.232 var=54 b0.233 var=35 b1.234 var=36 __vola.235 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.218 __ptr_corrupted_signal.193 __ptr_reference_noise_signal.194 __ptr_b0.195 __ptr_b1.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 __ct.214 _ZL10input_port.46 _ZL11output_port.49 _ZL16corrupted_signal.35 _ZL22reference_noise_signal.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.56 __extDM_int64_.53 __extDM_int8_.54 __extDM_void.51 __extPM.31 __extPM_FILE.55 __extPM_void.52 b0.157 b1.192 __vola.27) <233>; } #4 off=1 #5 off=2 (__ptr___str8a4fef85.62 var=65) const () <86>; (__ptr___str00f02b8f.64 var=67) const () <88>; (fopen.239 var=178) const () <237>; (__link.241 var=180) dmaddr__call_dmaddr_ (fopen.239) <239>; call { (__ptr___str8a4fef85.237 var=64 stl=A off=1) assign (__ptr___str8a4fef85.62) <235>; (__ptr___str00f02b8f.238 var=66 stl=A off=2) assign (__ptr___str00f02b8f.64) <236>; (__link.242 var=180 stl=LR off=0) assign (__link.241) <240>; (__tmp.243 var=181 stl=A off=0 _ZL10input_port.246 var=48 _ZL11output_port.247 var=51 _ZL16corrupted_signal.248 var=37 _ZL22reference_noise_signal.249 var=39 __extDM.250 var=32 __extDM_SingleSignalPath.251 var=38 __extDM_int16_.252 var=49 __extDM_int32_.253 var=58 __extDM_int64_.254 var=55 __extDM_int8_.255 var=56 __extDM_void.256 var=53 __extPM.257 var=33 __extPM_FILE.258 var=57 __extPM_void.259 var=54 b0.260 var=35 b1.261 var=36 __vola.262 var=29) Ffopen (__link.242 __ptr___str8a4fef85.237 __ptr___str00f02b8f.238 _ZL10input_port.219 _ZL11output_port.220 _ZL16corrupted_signal.221 _ZL22reference_noise_signal.222 __extDM.223 __extDM_SingleSignalPath.224 __extDM_int16_.225 __extDM_int32_.226 __extDM_int64_.227 __extDM_int8_.228 __extDM_void.229 __extPM.230 __extPM_FILE.231 __extPM_void.232 b0.233 b1.234 __vola.235) <241>; (__tmp.244 var=181) deassign (__tmp.243) <242>; } #6 off=3 #7 off=4 (__ptr___strff0646f3.66 var=69) const () <90>; (__link.268 var=184) dmaddr__call_dmaddr_ (fopen.239) <249>; call { (__ptr___strff0646f3.264 var=68 stl=A off=1) assign (__ptr___strff0646f3.66) <245>; (__ptr___str00f02b8f.265 var=66 stl=A off=2) assign (__ptr___str00f02b8f.64) <246>; (__link.269 var=184 stl=LR off=0) assign (__link.268) <250>; (__tmp.270 var=185 stl=A off=0 _ZL10input_port.273 var=48 _ZL11output_port.274 var=51 _ZL16corrupted_signal.275 var=37 _ZL22reference_noise_signal.276 var=39 __extDM.277 var=32 __extDM_SingleSignalPath.278 var=38 __extDM_int16_.279 var=49 __extDM_int32_.280 var=58 __extDM_int64_.281 var=55 __extDM_int8_.282 var=56 __extDM_void.283 var=53 __extPM.284 var=33 __extPM_FILE.285 var=57 __extPM_void.286 var=54 b0.287 var=35 b1.288 var=36 __vola.289 var=29) Ffopen (__link.269 __ptr___strff0646f3.264 __ptr___str00f02b8f.265 _ZL10input_port.246 _ZL11output_port.247 _ZL16corrupted_signal.248 _ZL22reference_noise_signal.249 __extDM.250 __extDM_SingleSignalPath.251 __extDM_int16_.252 __extDM_int32_.253 __extDM_int64_.254 __extDM_int8_.255 __extDM_void.256 __extPM.257 __extPM_FILE.258 __extPM_void.259 b0.260 b1.261 __vola.262) <251>; (__tmp.271 var=185) deassign (__tmp.270) <252>; } #8 off=5 #9 off=6 (__ptr___str8a32ec0e.68 var=71) const () <92>; (__ptr___str00f52cca.70 var=73) const () <94>; (__link.295 var=188) dmaddr__call_dmaddr_ (fopen.239) <259>; call { (__ptr___str8a32ec0e.291 var=70 stl=A off=1) assign (__ptr___str8a32ec0e.68) <255>; (__ptr___str00f52cca.292 var=72 stl=A off=2) assign (__ptr___str00f52cca.70) <256>; (__link.296 var=188 stl=LR off=0) assign (__link.295) <260>; (__tmp.297 var=189 stl=A off=0 _ZL10input_port.300 var=48 _ZL11output_port.301 var=51 _ZL16corrupted_signal.302 var=37 _ZL22reference_noise_signal.303 var=39 __extDM.304 var=32 __extDM_SingleSignalPath.305 var=38 __extDM_int16_.306 var=49 __extDM_int32_.307 var=58 __extDM_int64_.308 var=55 __extDM_int8_.309 var=56 __extDM_void.310 var=53 __extPM.311 var=33 __extPM_FILE.312 var=57 __extPM_void.313 var=54 b0.314 var=35 b1.315 var=36 __vola.316 var=29) Ffopen (__link.296 __ptr___str8a32ec0e.291 __ptr___str00f52cca.292 _ZL10input_port.273 _ZL11output_port.274 _ZL16corrupted_signal.275 _ZL22reference_noise_signal.276 __extDM.277 __extDM_SingleSignalPath.278 __extDM_int16_.279 __extDM_int32_.280 __extDM_int64_.281 __extDM_int8_.282 __extDM_void.283 __extPM.284 __extPM_FILE.285 __extPM_void.286 b0.287 b1.288 __vola.289) <261>; (__tmp.298 var=189) deassign (__tmp.297) <262>; } #10 off=7 #11 off=8 (feof.318 var=190) const () <265>; (__link.320 var=192) dmaddr__call_dmaddr_ (feof.318) <267>; call { (fp1.317 var=106 stl=A off=0) assign (__tmp.244) <264>; (__link.321 var=192 stl=LR off=0) assign (__link.320) <268>; (__tmp.322 var=193 stl=RA off=0 _ZL10input_port.325 var=48 _ZL11output_port.326 var=51 _ZL16corrupted_signal.327 var=37 _ZL22reference_noise_signal.328 var=39 __extDM.329 var=32 __extDM_SingleSignalPath.330 var=38 __extDM_int16_.331 var=49 __extDM_int32_.332 var=58 __extDM_int64_.333 var=55 __extDM_int8_.334 var=56 __extDM_void.335 var=53 __extPM.336 var=33 __extPM_FILE.337 var=57 __extPM_void.338 var=54 b0.339 var=35 b1.340 var=36 __vola.341 var=29) Ffeof (__link.321 fp1.317 _ZL10input_port.300 _ZL11output_port.301 _ZL16corrupted_signal.302 _ZL22reference_noise_signal.303 __extDM.304 __extDM_SingleSignalPath.305 __extDM_int16_.306 __extDM_int32_.307 __extDM_int64_.308 __extDM_int8_.309 __extDM_void.310 __extPM.311 __extPM_FILE.312 __extPM_void.313 b0.314 b1.315 __vola.316) <269>; (__tmp.323 var=193) deassign (__tmp.322) <270>; } #12 off=9 #692 off=10 (__ct_0.125 var=115) const () <149>; (__tmp.2130 var=443) uint3__cmp_int72__int72_ (__tmp.323 __ct_0.125) <2064>; (__tmp.2140 var=386) bool_nequal_uint3_ (__tmp.2130) <2123>; (__trgt.2149 var=457) const () <2220>; () void_jump_bool_int10_ (__tmp.2140 __trgt.2149) <2221>; (__either.2150 var=456) undefined () <2222>; if { { () if_expr (__either.2150) <330>; } #15 { (__true.2156 var=454) const () <2230>; } #16 { #18 off=11 (__link.405 var=201) dmaddr__call_dmaddr_ (feof.318) <336>; call { (fp2.402 var=107 stl=A off=0) assign (__tmp.271) <333>; (__link.406 var=201 stl=LR off=0) assign (__link.405) <337>; (__tmp.407 var=202 stl=RA off=0 _ZL10input_port.410 var=48 _ZL11output_port.411 var=51 _ZL16corrupted_signal.412 var=37 _ZL22reference_noise_signal.413 var=39 __extDM.414 var=32 __extDM_SingleSignalPath.415 var=38 __extDM_int16_.416 var=49 __extDM_int32_.417 var=58 __extDM_int64_.418 var=55 __extDM_int8_.419 var=56 __extDM_void.420 var=53 __extPM.421 var=33 __extPM_FILE.422 var=57 __extPM_void.423 var=54 b0.424 var=35 b1.425 var=36 __vola.426 var=29) Ffeof (__link.406 fp2.402 _ZL10input_port.325 _ZL11output_port.326 _ZL16corrupted_signal.327 _ZL22reference_noise_signal.328 __extDM.329 __extDM_SingleSignalPath.330 __extDM_int16_.331 __extDM_int32_.332 __extDM_int64_.333 __extDM_int8_.334 __extDM_void.335 __extPM.336 __extPM_FILE.337 __extPM_void.338 b0.339 b1.340 __vola.341) <338>; (__tmp.408 var=202) deassign (__tmp.407) <339>; } #19 off=12 #686 off=13 (__tmp.2120 var=443) uint3__cmp_int72__int72_ (__tmp.408 __ct_0.125) <2048>; (__tmp.2145 var=205) bool_nequal_uint3_ (__tmp.2120) <2172>; (__trgt.2157 var=460) const () <2231>; () void_jump_bool_int10_ (__tmp.2145 __trgt.2157) <2232>; (__either.2158 var=456) undefined () <2233>; } #17 { (__vola.431 var=29) merge (__vola.341 __vola.426) <345>; (__extDM.432 var=32) merge (__extDM.329 __extDM.414) <346>; (__extPM.433 var=33) merge (__extPM.336 __extPM.421) <347>; (b0.434 var=35) merge (b0.339 b0.424) <348>; (b1.435 var=36) merge (b1.340 b1.425) <349>; (_ZL16corrupted_signal.436 var=37) merge (_ZL16corrupted_signal.327 _ZL16corrupted_signal.412) <350>; (__extDM_SingleSignalPath.437 var=38) merge (__extDM_SingleSignalPath.330 __extDM_SingleSignalPath.415) <351>; (_ZL22reference_noise_signal.438 var=39) merge (_ZL22reference_noise_signal.328 _ZL22reference_noise_signal.413) <352>; (_ZL10input_port.439 var=48) merge (_ZL10input_port.325 _ZL10input_port.410) <353>; (__extDM_int16_.440 var=49) merge (__extDM_int16_.331 __extDM_int16_.416) <354>; (_ZL11output_port.441 var=51) merge (_ZL11output_port.326 _ZL11output_port.411) <355>; (__extDM_void.442 var=53) merge (__extDM_void.335 __extDM_void.420) <356>; (__extPM_void.443 var=54) merge (__extPM_void.338 __extPM_void.423) <357>; (__extDM_int64_.444 var=55) merge (__extDM_int64_.333 __extDM_int64_.418) <358>; (__extDM_int8_.445 var=56) merge (__extDM_int8_.334 __extDM_int8_.419) <359>; (__extPM_FILE.446 var=57) merge (__extPM_FILE.337 __extPM_FILE.422) <360>; (__extDM_int32_.447 var=58) merge (__extDM_int32_.332 __extDM_int32_.417) <361>; (__tmp.2146 var=206) merge (__true.2156 __either.2158) <2173>; } #21 } #14 if { { () if_expr (__tmp.2146) <418>; () chess_frequent_else () <419>; () chess_rear_then () <2234>; } #24 { (__trgt.2159 var=461) const () <2235>; () void_jump_int10_ (__trgt.2159) <2236>; } #72 off=30 { #92 off=14 (__ptr___str41232700.72 var=75) const () <96>; (__ct_8388608.74 var=77) const () <98>; (__ptr_mode.77 var=79) const () <101>; (__ct_8388624.79 var=81) const () <103>; (__ptr___str2eb09b76.82 var=83) const () <106>; (fscanf.678 var=213) const () <596>; (__fch__ZZ4mainvE4mode.892 var=242) load (__M_WDMA.9 __ptr_mode.77 _ZZ4mainvE4mode.48) <715>; (_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.903 var=249) const () <726>; (fprintf.1053 var=263) const () <858>; (__rt.1793 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_80t0.2086) <1556>; (__rt.1815 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_84t0.2089) <1584>; (__ct_80t0.2086 var=408) const () <1981>; (__ct_84t0.2089 var=411) const () <1987>; (__ct_2.2092 var=414) const () <1993>; (__trgt.2151 var=458) const () <2223>; (__trgt.2154 var=459) const () <2227>; do { { (__vola.504 var=29) entry (__vola.1354 __vola.431) <420>; (__extDM.507 var=32) entry (__extDM.1360 __extDM.432) <423>; (__extPM.508 var=33) entry (__extPM.1362 __extPM.433) <424>; (b0.510 var=35) entry (b0.1366 b0.434) <426>; (b1.511 var=36) entry (b1.1368 b1.435) <427>; (_ZL16corrupted_signal.512 var=37) entry (_ZL16corrupted_signal.1370 _ZL16corrupted_signal.436) <428>; (__extDM_SingleSignalPath.513 var=38) entry (__extDM_SingleSignalPath.1372 __extDM_SingleSignalPath.437) <429>; (_ZL22reference_noise_signal.514 var=39) entry (_ZL22reference_noise_signal.1374 _ZL22reference_noise_signal.438) <430>; (d0.521 var=46) entry (d0.1388 d0.44) <437>; (d1.522 var=47) entry (d1.1390 d1.45) <438>; (_ZL10input_port.523 var=48) entry (_ZL10input_port.1392 _ZL10input_port.439) <439>; (__extDM_int16_.524 var=49) entry (__extDM_int16_.1394 __extDM_int16_.440) <440>; (_ZL11output_port.526 var=51) entry (_ZL11output_port.1398 _ZL11output_port.441) <442>; (__extDM_void.528 var=53) entry (__extDM_void.1402 __extDM_void.442) <444>; (__extPM_void.529 var=54) entry (__extPM_void.1404 __extPM_void.443) <445>; (__extDM_int64_.530 var=55) entry (__extDM_int64_.1406 __extDM_int64_.444) <446>; (__extDM_int8_.531 var=56) entry (__extDM_int8_.1408 __extDM_int8_.445) <447>; (__extPM_FILE.532 var=57) entry (__extPM_FILE.1410 __extPM_FILE.446) <448>; (__extDM_int32_.533 var=58) entry (__extDM_int32_.1412 __extDM_int32_.447) <449>; (__shv___ptr_input_port.1681 var=337) entry (__shv___ptr_input_port.1679 __ct_8388608.74) <1370>; } #27 { #36 off=15 (__link.680 var=215) dmaddr__call_dmaddr_ (fscanf.678) <598>; call { (fp1.675 var=106 stl=A off=0) assign (__tmp.244) <593>; (__ptr___str41232700.676 var=74 stl=A off=1) assign (__ptr___str41232700.72) <594>; (__ptr_d0.677 var=98 stl=__spill_WDMA off=0) assign (__rt.1793) <595>; (__link.681 var=215 stl=LR off=0) assign (__link.680) <599>; (__tmp.682 var=216 stl=RA off=0 _ZL10input_port.685 var=48 _ZL11output_port.686 var=51 _ZL16corrupted_signal.687 var=37 _ZL22reference_noise_signal.688 var=39 __extDM.689 var=32 __extDM_SingleSignalPath.690 var=38 __extDM_int16_.691 var=49 __extDM_int32_.692 var=58 __extDM_int64_.693 var=55 __extDM_int8_.694 var=56 __extDM_void.695 var=53 __extPM.696 var=33 __extPM_FILE.697 var=57 __extPM_void.698 var=54 b0.699 var=35 b1.700 var=36 d0.701 var=46 __vola.702 var=29) VA0Ffscanf (__link.681 fp1.675 __ptr___str41232700.676 __ptr_d0.677 _ZL10input_port.523 _ZL11output_port.526 _ZL16corrupted_signal.512 _ZL22reference_noise_signal.514 __extDM.507 __extDM_SingleSignalPath.513 __extDM_int16_.524 __extDM_int32_.533 __extDM_int64_.530 __extDM_int8_.531 __extDM_void.528 __extPM.508 __extPM_FILE.532 __extPM_void.529 b0.510 b1.511 d0.521 __vola.504) <600>; } #37 off=16 #38 off=17 (__link.708 var=219) dmaddr__call_dmaddr_ (fscanf.678) <608>; call { (fp2.703 var=107 stl=A off=0) assign (__tmp.271) <603>; (__ptr___str41232700.704 var=74 stl=A off=1) assign (__ptr___str41232700.72) <604>; (__ptr_d1.705 var=102 stl=__spill_WDMA off=0) assign (__rt.1815) <605>; (__link.709 var=219 stl=LR off=0) assign (__link.708) <609>; (__tmp.710 var=220 stl=RA off=0 _ZL10input_port.713 var=48 _ZL11output_port.714 var=51 _ZL16corrupted_signal.715 var=37 _ZL22reference_noise_signal.716 var=39 __extDM.717 var=32 __extDM_SingleSignalPath.718 var=38 __extDM_int16_.719 var=49 __extDM_int32_.720 var=58 __extDM_int64_.721 var=55 __extDM_int8_.722 var=56 __extDM_void.723 var=53 __extPM.724 var=33 __extPM_FILE.725 var=57 __extPM_void.726 var=54 b0.727 var=35 b1.728 var=36 d0.729 var=46 d1.730 var=47 __vola.731 var=29) VA1Ffscanf (__link.709 fp2.703 __ptr___str41232700.704 __ptr_d1.705 _ZL10input_port.685 _ZL11output_port.686 _ZL16corrupted_signal.687 _ZL22reference_noise_signal.688 __extDM.689 __extDM_SingleSignalPath.690 __extDM_int16_.691 __extDM_int32_.692 __extDM_int64_.693 __extDM_int8_.694 __extDM_void.695 __extPM.696 __extPM_FILE.697 __extPM_void.698 b0.699 b1.700 d0.701 d1.522 __vola.702) <610>; } #39 off=18 #474 off=19 (__fch_d0.732 var=221) load (__M_WDMA.9 __rt.1793 d0.729) <613>; (__tmp.733 var=222) __sshort___sshort___sint (__fch_d0.732) <614>; (__M_SDMB.738 var=8 _ZL10input_port.739 var=48 __vola.740 var=29) store (__tmp.733 __shv___ptr_input_port.1681 _ZL10input_port.713 __vola.731) <619>; (__fch_d1.741 var=227) load (__M_WDMA.9 __rt.1815 d1.730) <620>; (__tmp.742 var=228) __sshort___sshort___sint (__fch_d1.741) <621>; (__M_SDMB.750 var=8 _ZL10input_port.751 var=48 __vola.752 var=29) store (__tmp.742 __rt.1869 _ZL10input_port.739 __vola.740) <629>; (__link.905 var=251) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.903) <728>; (__rt.1869 var=361) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1681 __ct_2.2092) <1656>; (__rt.1891 var=361) __Pvoid__mi___Pvoid_int18_ (__rt.1869 __ct_2.2092) <1684>; call { (__ptr_corrupted_signal.890 var=60 stl=A off=0) assign (__ptr_corrupted_signal.58) <713>; (__ptr_reference_noise_signal.891 var=62 stl=A off=1) assign (__ptr_reference_noise_signal.60) <714>; (__fch__ZZ4mainvE4mode.893 var=242 stl=RA off=0) assign (__fch__ZZ4mainvE4mode.892) <716>; (__tmp.897 var=245 stl=A off=4) assign (__shv___ptr_input_port.1681) <720>; (__tmp.901 var=248 stl=A off=5) assign (__rt.1869) <724>; (__ptr_output_port.902 var=80 stl=__spill_WDMA off=0) assign (__ct_8388624.79) <725>; (__link.906 var=251 stl=LR off=0) assign (__link.905) <729>; (_ZL10input_port.907 var=48 _ZL11output_port.908 var=51 _ZL16corrupted_signal.909 var=37 _ZL22reference_noise_signal.910 var=39 __extDM.911 var=32 __extDM_SingleSignalPath.912 var=38 __extDM_int16_.913 var=49 __extDM_int32_.914 var=58 __extDM_int64_.915 var=55 __extDM_int8_.916 var=56 __extDM_void.917 var=53 __extPM.918 var=33 __extPM_FILE.919 var=57 __extPM_void.920 var=54 b0.921 var=35 b1.922 var=36 d0.923 var=46 d1.924 var=47 __vola.925 var=29) F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ (__link.906 __ptr_corrupted_signal.890 __ptr_reference_noise_signal.891 __fch__ZZ4mainvE4mode.893 __tmp.897 __tmp.901 __ptr_output_port.902 _ZL10input_port.751 _ZL11output_port.714 _ZL16corrupted_signal.715 _ZL22reference_noise_signal.716 __extDM.717 __extDM_SingleSignalPath.718 __extDM_int16_.719 __extDM_int32_.720 __extDM_int64_.721 __extDM_int8_.722 __extDM_void.723 __extPM.724 __extPM_FILE.725 __extPM_void.726 b0.727 b1.728 d0.729 d1.730 __vola.752) <730>; } #45 off=20 #53 off=21 (__fch__ZL11output_port.1048 var=261 _ZL11output_port.1049 var=51 __vola.1050 var=29) load (__M_SDMB.6 __ct_8388624.79 _ZL11output_port.908 __vola.925) <855>; (__link.1055 var=265) dmaddr__call_dmaddr_ (fprintf.1053) <860>; call { (fp3.1042 var=108 stl=A off=0) assign (__tmp.298) <849>; (__ptr___str2eb09b76.1043 var=82 stl=A off=1) assign (__ptr___str2eb09b76.82) <850>; (__fch__ZL11output_port.1052 var=262 stl=__spill_WDMA off=0) assign (__fch__ZL11output_port.1048) <857>; (__link.1056 var=265 stl=LR off=0) assign (__link.1055) <861>; (__tmp.1057 var=266 stl=RA off=0 _ZL10input_port.1060 var=48 _ZL11output_port.1061 var=51 _ZL16corrupted_signal.1062 var=37 _ZL22reference_noise_signal.1063 var=39 __extDM.1064 var=32 __extDM_SingleSignalPath.1065 var=38 __extDM_int16_.1066 var=49 __extDM_int32_.1067 var=58 __extDM_int64_.1068 var=55 __extDM_int8_.1069 var=56 __extDM_void.1070 var=53 __extPM.1071 var=33 __extPM_FILE.1072 var=57 __extPM_void.1073 var=54 b0.1074 var=35 b1.1075 var=36 d0.1076 var=46 d1.1077 var=47 __vola.1078 var=29) VA2Ffprintf (__link.1056 fp3.1042 __ptr___str2eb09b76.1043 __fch__ZL11output_port.1052 _ZL10input_port.907 _ZL11output_port.1049 _ZL16corrupted_signal.909 _ZL22reference_noise_signal.910 __extDM.911 __extDM_SingleSignalPath.912 __extDM_int16_.913 __extDM_int32_.914 __extDM_int64_.915 __extDM_int8_.916 __extDM_void.917 __extPM.918 __extPM_FILE.919 __extPM_void.920 b0.921 b1.922 d0.923 d1.924 __vola.1050) <862>; } #54 off=22 #59 off=23 (__link.1219 var=275) dmaddr__call_dmaddr_ (feof.318) <951>; call { (fp1.1216 var=106 stl=A off=0) assign (__tmp.244) <948>; (__link.1220 var=275 stl=LR off=0) assign (__link.1219) <952>; (__tmp.1221 var=276 stl=RA off=0 _ZL10input_port.1224 var=48 _ZL11output_port.1225 var=51 _ZL16corrupted_signal.1226 var=37 _ZL22reference_noise_signal.1227 var=39 __extDM.1228 var=32 __extDM_SingleSignalPath.1229 var=38 __extDM_int16_.1230 var=49 __extDM_int32_.1231 var=58 __extDM_int64_.1232 var=55 __extDM_int8_.1233 var=56 __extDM_void.1234 var=53 __extPM.1235 var=33 __extPM_FILE.1236 var=57 __extPM_void.1237 var=54 b0.1238 var=35 b1.1239 var=36 d0.1240 var=46 d1.1241 var=47 __vola.1242 var=29) Ffeof (__link.1220 fp1.1216 _ZL10input_port.1060 _ZL11output_port.1061 _ZL16corrupted_signal.1062 _ZL22reference_noise_signal.1063 __extDM.1064 __extDM_SingleSignalPath.1065 __extDM_int16_.1066 __extDM_int32_.1067 __extDM_int64_.1068 __extDM_int8_.1069 __extDM_void.1070 __extPM.1071 __extPM_FILE.1072 __extPM_void.1073 b0.1074 b1.1075 d0.1076 d1.1077 __vola.1078) <953>; (__tmp.1222 var=276) deassign (__tmp.1221) <954>; } #60 off=24 #697 off=25 (__tmp.2135 var=443) uint3__cmp_int72__int72_ (__tmp.1222 __ct_0.125) <2072>; (__tmp.2141 var=386) bool_nequal_uint3_ (__tmp.2135) <2124>; () void_jump_bool_int10_ (__tmp.2141 __trgt.2151) <2224>; (__either.2152 var=456) undefined () <2225>; if { { () if_expr (__either.2152) <1014>; } #63 { (__false.2153 var=455) const () <2226>; } #64 { #66 off=26 (__link.1306 var=284) dmaddr__call_dmaddr_ (feof.318) <1020>; call { (fp2.1303 var=107 stl=A off=0) assign (__tmp.271) <1017>; (__link.1307 var=284 stl=LR off=0) assign (__link.1306) <1021>; (__tmp.1308 var=285 stl=RA off=0 _ZL10input_port.1311 var=48 _ZL11output_port.1312 var=51 _ZL16corrupted_signal.1313 var=37 _ZL22reference_noise_signal.1314 var=39 __extDM.1315 var=32 __extDM_SingleSignalPath.1316 var=38 __extDM_int16_.1317 var=49 __extDM_int32_.1318 var=58 __extDM_int64_.1319 var=55 __extDM_int8_.1320 var=56 __extDM_void.1321 var=53 __extPM.1322 var=33 __extPM_FILE.1323 var=57 __extPM_void.1324 var=54 b0.1325 var=35 b1.1326 var=36 d0.1327 var=46 d1.1328 var=47 __vola.1329 var=29) Ffeof (__link.1307 fp2.1303 _ZL10input_port.1224 _ZL11output_port.1225 _ZL16corrupted_signal.1226 _ZL22reference_noise_signal.1227 __extDM.1228 __extDM_SingleSignalPath.1229 __extDM_int16_.1230 __extDM_int32_.1231 __extDM_int64_.1232 __extDM_int8_.1233 __extDM_void.1234 __extPM.1235 __extPM_FILE.1236 __extPM_void.1237 b0.1238 b1.1239 d0.1240 d1.1241 __vola.1242) <1022>; (__tmp.1309 var=285) deassign (__tmp.1308) <1023>; } #67 off=27 #689 off=28 (__tmp.2125 var=443) uint3__cmp_int72__int72_ (__tmp.1309 __ct_0.125) <2056>; (__tmp.2126 var=288) bool_equal_uint3_ (__tmp.2125) <2057>; () void_jump_bool_int10_ (__tmp.2126 __trgt.2154) <2228>; (__either.2155 var=456) undefined () <2229>; } #65 { (__vola.1334 var=29) merge (__vola.1242 __vola.1329) <1029>; (__extDM.1335 var=32) merge (__extDM.1228 __extDM.1315) <1030>; (__extPM.1336 var=33) merge (__extPM.1235 __extPM.1322) <1031>; (b0.1337 var=35) merge (b0.1238 b0.1325) <1032>; (b1.1338 var=36) merge (b1.1239 b1.1326) <1033>; (_ZL16corrupted_signal.1339 var=37) merge (_ZL16corrupted_signal.1226 _ZL16corrupted_signal.1313) <1034>; (__extDM_SingleSignalPath.1340 var=38) merge (__extDM_SingleSignalPath.1229 __extDM_SingleSignalPath.1316) <1035>; (_ZL22reference_noise_signal.1341 var=39) merge (_ZL22reference_noise_signal.1227 _ZL22reference_noise_signal.1314) <1036>; (d0.1342 var=46) merge (d0.1240 d0.1327) <1037>; (d1.1343 var=47) merge (d1.1241 d1.1328) <1038>; (_ZL10input_port.1344 var=48) merge (_ZL10input_port.1224 _ZL10input_port.1311) <1039>; (__extDM_int16_.1345 var=49) merge (__extDM_int16_.1230 __extDM_int16_.1317) <1040>; (_ZL11output_port.1346 var=51) merge (_ZL11output_port.1225 _ZL11output_port.1312) <1041>; (__extDM_void.1347 var=53) merge (__extDM_void.1234 __extDM_void.1321) <1042>; (__extPM_void.1348 var=54) merge (__extPM_void.1237 __extPM_void.1324) <1043>; (__extDM_int64_.1349 var=55) merge (__extDM_int64_.1232 __extDM_int64_.1319) <1044>; (__extDM_int8_.1350 var=56) merge (__extDM_int8_.1233 __extDM_int8_.1320) <1045>; (__extPM_FILE.1351 var=57) merge (__extPM_FILE.1236 __extPM_FILE.1323) <1046>; (__extDM_int32_.1352 var=58) merge (__extDM_int32_.1231 __extDM_int32_.1318) <1047>; (__tmp.1639 var=289) merge (__false.2153 __either.2155) <1331>; } #69 } #62 } #28 { () while_expr (__tmp.1639) <1049>; (__vola.1354 var=29 __vola.1355 var=29) exit (__vola.1334) <1050>; (__extDM.1360 var=32 __extDM.1361 var=32) exit (__extDM.1335) <1053>; (__extPM.1362 var=33 __extPM.1363 var=33) exit (__extPM.1336) <1054>; (b0.1366 var=35 b0.1367 var=35) exit (b0.1337) <1056>; (b1.1368 var=36 b1.1369 var=36) exit (b1.1338) <1057>; (_ZL16corrupted_signal.1370 var=37 _ZL16corrupted_signal.1371 var=37) exit (_ZL16corrupted_signal.1339) <1058>; (__extDM_SingleSignalPath.1372 var=38 __extDM_SingleSignalPath.1373 var=38) exit (__extDM_SingleSignalPath.1340) <1059>; (_ZL22reference_noise_signal.1374 var=39 _ZL22reference_noise_signal.1375 var=39) exit (_ZL22reference_noise_signal.1341) <1060>; (d0.1388 var=46 d0.1389 var=46) exit (d0.1342) <1067>; (d1.1390 var=47 d1.1391 var=47) exit (d1.1343) <1068>; (_ZL10input_port.1392 var=48 _ZL10input_port.1393 var=48) exit (_ZL10input_port.1344) <1069>; (__extDM_int16_.1394 var=49 __extDM_int16_.1395 var=49) exit (__extDM_int16_.1345) <1070>; (_ZL11output_port.1398 var=51 _ZL11output_port.1399 var=51) exit (_ZL11output_port.1346) <1072>; (__extDM_void.1402 var=53 __extDM_void.1403 var=53) exit (__extDM_void.1347) <1074>; (__extPM_void.1404 var=54 __extPM_void.1405 var=54) exit (__extPM_void.1348) <1075>; (__extDM_int64_.1406 var=55 __extDM_int64_.1407 var=55) exit (__extDM_int64_.1349) <1076>; (__extDM_int8_.1408 var=56 __extDM_int8_.1409 var=56) exit (__extDM_int8_.1350) <1077>; (__extPM_FILE.1410 var=57 __extPM_FILE.1411 var=57) exit (__extPM_FILE.1351) <1078>; (__extDM_int32_.1412 var=58 __extDM_int32_.1413 var=58) exit (__extDM_int32_.1352) <1079>; (__shv___ptr_input_port.1679 var=337 __shv___ptr_input_port.1680 var=337) exit (__rt.1891) <1369>; } #71 } #26 rng=[1,65535] } #25 { (__vola.1464 var=29) merge (__vola.431 __vola.1355) <1105>; (__extDM.1465 var=32) merge (__extDM.432 __extDM.1361) <1106>; (__extPM.1466 var=33) merge (__extPM.433 __extPM.1363) <1107>; (b0.1467 var=35) merge (b0.434 b0.1367) <1108>; (b1.1468 var=36) merge (b1.435 b1.1369) <1109>; (_ZL16corrupted_signal.1469 var=37) merge (_ZL16corrupted_signal.436 _ZL16corrupted_signal.1371) <1110>; (__extDM_SingleSignalPath.1470 var=38) merge (__extDM_SingleSignalPath.437 __extDM_SingleSignalPath.1373) <1111>; (_ZL22reference_noise_signal.1471 var=39) merge (_ZL22reference_noise_signal.438 _ZL22reference_noise_signal.1375) <1112>; (d0.1472 var=46) merge (d0.44 d0.1389) <1113>; (d1.1473 var=47) merge (d1.45 d1.1391) <1114>; (_ZL10input_port.1474 var=48) merge (_ZL10input_port.439 _ZL10input_port.1393) <1115>; (__extDM_int16_.1475 var=49) merge (__extDM_int16_.440 __extDM_int16_.1395) <1116>; (_ZL11output_port.1476 var=51) merge (_ZL11output_port.441 _ZL11output_port.1399) <1117>; (__extDM_void.1477 var=53) merge (__extDM_void.442 __extDM_void.1403) <1118>; (__extPM_void.1478 var=54) merge (__extPM_void.443 __extPM_void.1405) <1119>; (__extDM_int64_.1479 var=55) merge (__extDM_int64_.444 __extDM_int64_.1407) <1120>; (__extDM_int8_.1480 var=56) merge (__extDM_int8_.445 __extDM_int8_.1409) <1121>; (__extPM_FILE.1481 var=57) merge (__extPM_FILE.446 __extPM_FILE.1411) <1122>; (__extDM_int32_.1482 var=58) merge (__extDM_int32_.447 __extDM_int32_.1413) <1123>; } #73 } #23 #74 off=31 (fclose.1488 var=291) const () <1129>; (__link.1490 var=293) dmaddr__call_dmaddr_ (fclose.1488) <1131>; call { (fp1.1487 var=106 stl=A off=0) assign (__tmp.244) <1128>; (__link.1491 var=293 stl=LR off=0) assign (__link.1490) <1132>; (__tmp.1492 var=294 stl=RA off=0 _ZL10input_port.1495 var=48 _ZL11output_port.1496 var=51 _ZL16corrupted_signal.1497 var=37 _ZL22reference_noise_signal.1498 var=39 __extDM.1499 var=32 __extDM_SingleSignalPath.1500 var=38 __extDM_int16_.1501 var=49 __extDM_int32_.1502 var=58 __extDM_int64_.1503 var=55 __extDM_int8_.1504 var=56 __extDM_void.1505 var=53 __extPM.1506 var=33 __extPM_FILE.1507 var=57 __extPM_void.1508 var=54 b0.1509 var=35 b1.1510 var=36 d0.1511 var=46 d1.1512 var=47 __vola.1513 var=29) Ffclose (__link.1491 fp1.1487 _ZL10input_port.1474 _ZL11output_port.1476 _ZL16corrupted_signal.1469 _ZL22reference_noise_signal.1471 __extDM.1465 __extDM_SingleSignalPath.1470 __extDM_int16_.1475 __extDM_int32_.1482 __extDM_int64_.1479 __extDM_int8_.1480 __extDM_void.1477 __extPM.1466 __extPM_FILE.1481 __extPM_void.1478 b0.1467 b1.1468 d0.1472 d1.1473 __vola.1464) <1133>; } #75 off=32 #76 off=33 (__link.1517 var=297) dmaddr__call_dmaddr_ (fclose.1488) <1139>; call { (fp2.1514 var=107 stl=A off=0) assign (__tmp.271) <1136>; (__link.1518 var=297 stl=LR off=0) assign (__link.1517) <1140>; (__tmp.1519 var=298 stl=RA off=0 _ZL10input_port.1522 var=48 _ZL11output_port.1523 var=51 _ZL16corrupted_signal.1524 var=37 _ZL22reference_noise_signal.1525 var=39 __extDM.1526 var=32 __extDM_SingleSignalPath.1527 var=38 __extDM_int16_.1528 var=49 __extDM_int32_.1529 var=58 __extDM_int64_.1530 var=55 __extDM_int8_.1531 var=56 __extDM_void.1532 var=53 __extPM.1533 var=33 __extPM_FILE.1534 var=57 __extPM_void.1535 var=54 b0.1536 var=35 b1.1537 var=36 d0.1538 var=46 d1.1539 var=47 __vola.1540 var=29) Ffclose (__link.1518 fp2.1514 _ZL10input_port.1495 _ZL11output_port.1496 _ZL16corrupted_signal.1497 _ZL22reference_noise_signal.1498 __extDM.1499 __extDM_SingleSignalPath.1500 __extDM_int16_.1501 __extDM_int32_.1502 __extDM_int64_.1503 __extDM_int8_.1504 __extDM_void.1505 __extPM.1506 __extPM_FILE.1507 __extPM_void.1508 b0.1509 b1.1510 d0.1511 d1.1512 __vola.1513) <1141>; } #77 off=34 #78 off=35 (__link.1544 var=301) dmaddr__call_dmaddr_ (fclose.1488) <1147>; call { (fp3.1541 var=108 stl=A off=0) assign (__tmp.298) <1144>; (__link.1545 var=301 stl=LR off=0) assign (__link.1544) <1148>; (__tmp.1546 var=302 stl=RA off=0 _ZL10input_port.1549 var=48 _ZL11output_port.1550 var=51 _ZL16corrupted_signal.1551 var=37 _ZL22reference_noise_signal.1552 var=39 __extDM.1553 var=32 __extDM_SingleSignalPath.1554 var=38 __extDM_int16_.1555 var=49 __extDM_int32_.1556 var=58 __extDM_int64_.1557 var=55 __extDM_int8_.1558 var=56 __extDM_void.1559 var=53 __extPM.1560 var=33 __extPM_FILE.1561 var=57 __extPM_void.1562 var=54 b0.1563 var=35 b1.1564 var=36 d0.1565 var=46 d1.1566 var=47 __vola.1567 var=29) Ffclose (__link.1545 fp3.1541 _ZL10input_port.1522 _ZL11output_port.1523 _ZL16corrupted_signal.1524 _ZL22reference_noise_signal.1525 __extDM.1526 __extDM_SingleSignalPath.1527 __extDM_int16_.1528 __extDM_int32_.1529 __extDM_int64_.1530 __extDM_int8_.1531 __extDM_void.1532 __extPM.1533 __extPM_FILE.1534 __extPM_void.1535 b0.1536 b1.1537 d0.1538 d1.1539 __vola.1540) <1149>; } #79 off=36 #82 off=37 nxt=-2 (__R_SP.1574 var=26 __sp.1575 var=34) wr_res_reg (__rt.1847 __sp.95) <1158>; () void_ret_dmaddr_ (__la.87) <1159>; (__rt.1576 var=86 stl=RA off=0) assign (__ct_0.125) <1160>; () out (__rt.1576) <1161>; () sink (__vola.1567) <1162>; () sink (__extDM.1553) <1165>; () sink (__extPM.1560) <1166>; () sink (__sp.1575) <1167>; () sink (_ZL16corrupted_signal.1551) <1168>; () sink (__extDM_SingleSignalPath.1554) <1169>; () sink (_ZL22reference_noise_signal.1552) <1170>; () sink (_ZL10input_port.1549) <1177>; () sink (__extDM_int16_.1555) <1178>; () sink (_ZL11output_port.1550) <1180>; () sink (__extDM_void.1559) <1182>; () sink (__extPM_void.1562) <1183>; () sink (__extDM_int64_.1557) <1184>; () sink (__extDM_int8_.1558) <1185>; () sink (__extPM_FILE.1561) <1186>; () sink (__extDM_int32_.1556) <1187>; () sink (__ct_0.84) <1188>; (__rt.1847 var=361) __Pvoid__pl___Pvoid_int18_ (__rd___sp.96 __ct_88s0.2081) <1628>; (__ct_88s0.2081 var=403) const () <1971>; } #0 0 : 'main.c'; ---------- 0 : (0,28:0,0); 4 : (0,38:4,15); 5 : (0,50:72,16); 6 : (0,50:16,16); 7 : (0,51:68,17); 8 : (0,51:16,17); 9 : (0,52:79,18); 10 : (0,52:16,18); 11 : (0,56:4,20); 12 : (0,56:4,20); 14 : (0,56:4,20); 16 : (0,56:4,21); 17 : (0,56:4,22); 18 : (0,56:4,22); 19 : (0,56:4,22); 23 : (0,56:4,24); 25 : (0,56:4,25); 26 : (0,56:4,25); 28 : (0,56:37,25); 36 : (0,58:22,27); 37 : (0,58:12,27); 38 : (0,59:22,28); 39 : (0,59:12,28); 45 : (0,63:8,40); 53 : (0,66:23,43); 54 : (0,66:12,43); 59 : (0,56:18,54); 60 : (0,56:13,54); 62 : (0,56:23,54); 64 : (0,56:23,55); 65 : (0,56:23,56); 66 : (0,56:31,56); 67 : (0,56:26,56); 72 : (0,56:4,60); 74 : (0,69:11,63); 75 : (0,69:4,63); 76 : (0,70:11,64); 77 : (0,70:4,64); 78 : (0,71:11,65); 79 : (0,71:4,65); 82 : (0,72:0,66); 352 : (0,38:4,15); 474 : (0,63:8,40); 686 : (0,56:4,22); 689 : (0,56:23,56); 692 : (0,56:4,20); 697 : (0,56:23,54); ---------- 86 : (0,50:22,0); 88 : (0,50:72,0); 90 : (0,51:22,0); 92 : (0,52:22,0); 94 : (0,52:79,0); 114 : (0,28:4,0); 118 : (0,28:4,0); 120 : (0,33:11,0); 147 : (0,33:18,0); 149 : (0,33:18,0); 152 : (0,33:18,2); 153 : (0,33:24,0); 158 : (0,33:24,3); 164 : (0,33:28,4); 170 : (0,33:32,5); 176 : (0,33:36,6); 182 : (0,34:18,8); 188 : (0,34:24,9); 194 : (0,34:28,10); 200 : (0,34:32,11); 206 : (0,34:36,12); 207 : (0,39:8,0); 208 : (0,39:27,0); 209 : (0,40:8,0); 210 : (0,41:8,0); 211 : (0,42:8,0); 213 : (0,42:8,0); 216 : (0,43:8,0); 217 : (0,44:8,0); 219 : (0,44:8,0); 222 : (0,45:8,0); 223 : (0,46:8,0); 225 : (0,46:8,0); 226 : (0,47:8,0); 228 : (0,47:8,0); 231 : (0,38:4,15); 232 : (0,38:4,0); 233 : (0,38:4,15); 235 : (0,50:22,0); 236 : (0,50:72,0); 239 : (0,50:16,16); 240 : (0,50:16,0); 241 : (0,50:16,16); 245 : (0,51:22,0); 246 : (0,51:68,0); 249 : (0,51:16,17); 250 : (0,51:16,0); 251 : (0,51:16,17); 255 : (0,52:22,0); 256 : (0,52:79,0); 259 : (0,52:16,18); 260 : (0,52:16,0); 261 : (0,52:16,18); 264 : (0,56:4,0); 267 : (0,56:4,20); 268 : (0,56:4,0); 269 : (0,56:4,20); 330 : (0,56:4,20); 333 : (0,56:4,0); 336 : (0,56:4,22); 337 : (0,56:4,0); 338 : (0,56:4,22); 345 : (0,56:4,23); 346 : (0,56:4,23); 347 : (0,56:4,23); 348 : (0,56:4,23); 349 : (0,56:4,23); 350 : (0,56:4,23); 351 : (0,56:4,23); 352 : (0,56:4,23); 353 : (0,56:4,23); 354 : (0,56:4,23); 355 : (0,56:4,23); 356 : (0,56:4,23); 357 : (0,56:4,23); 358 : (0,56:4,23); 359 : (0,56:4,23); 360 : (0,56:4,23); 361 : (0,56:4,23); 418 : (0,56:4,24); 420 : (0,56:4,25); 423 : (0,56:4,25); 424 : (0,56:4,25); 426 : (0,56:4,25); 427 : (0,56:4,25); 428 : (0,56:4,25); 429 : (0,56:4,25); 430 : (0,56:4,25); 437 : (0,56:4,25); 438 : (0,56:4,25); 439 : (0,56:4,25); 440 : (0,56:4,25); 442 : (0,56:4,25); 444 : (0,56:4,25); 445 : (0,56:4,25); 446 : (0,56:4,25); 447 : (0,56:4,25); 448 : (0,56:4,25); 449 : (0,56:4,25); 593 : (0,58:19,0); 594 : (0,58:24,0); 595 : (0,58:22,0); 598 : (0,58:12,27); 599 : (0,58:12,0); 600 : (0,58:12,27); 603 : (0,59:19,0); 604 : (0,59:24,0); 605 : (0,59:22,0); 608 : (0,59:12,28); 609 : (0,59:12,0); 610 : (0,59:12,28); 613 : (0,60:38,29); 614 : (0,60:28,29); 619 : (0,60:22,29); 620 : (0,61:40,30); 621 : (0,61:30,30); 629 : (0,61:22,30); 713 : (0,64:12,0); 714 : (0,64:31,0); 715 : (0,64:56,40); 716 : (0,64:56,0); 720 : (0,64:73,0); 724 : (0,64:89,0); 725 : (0,64:94,0); 728 : (0,63:8,40); 729 : (0,63:8,0); 730 : (0,63:8,40); 849 : (0,66:20,0); 850 : (0,66:25,0); 855 : (0,66:44,43); 857 : (0,66:23,0); 860 : (0,66:12,43); 861 : (0,66:12,0); 862 : (0,66:12,43); 948 : (0,56:18,0); 951 : (0,56:13,54); 952 : (0,56:13,0); 953 : (0,56:13,54); 1014 : (0,56:23,54); 1017 : (0,56:31,0); 1020 : (0,56:26,56); 1021 : (0,56:26,0); 1022 : (0,56:26,56); 1029 : (0,56:23,57); 1030 : (0,56:23,57); 1031 : (0,56:23,57); 1032 : (0,56:23,57); 1033 : (0,56:23,57); 1034 : (0,56:23,57); 1035 : (0,56:23,57); 1036 : (0,56:23,57); 1037 : (0,56:23,57); 1038 : (0,56:23,57); 1039 : (0,56:23,57); 1040 : (0,56:23,57); 1041 : (0,56:23,57); 1042 : (0,56:23,57); 1043 : (0,56:23,57); 1044 : (0,56:23,57); 1045 : (0,56:23,57); 1046 : (0,56:23,57); 1047 : (0,56:23,57); 1049 : (0,56:4,58); 1050 : (0,56:4,58); 1053 : (0,56:4,58); 1054 : (0,56:4,58); 1056 : (0,56:4,58); 1057 : (0,56:4,58); 1058 : (0,56:4,58); 1059 : (0,56:4,58); 1060 : (0,56:4,58); 1067 : (0,56:4,58); 1068 : (0,56:4,58); 1069 : (0,56:4,58); 1070 : (0,56:4,58); 1072 : (0,56:4,58); 1074 : (0,56:4,58); 1075 : (0,56:4,58); 1076 : (0,56:4,58); 1077 : (0,56:4,58); 1078 : (0,56:4,58); 1079 : (0,56:4,58); 1105 : (0,56:4,62); 1106 : (0,56:4,62); 1107 : (0,56:4,62); 1108 : (0,56:4,62); 1109 : (0,56:4,62); 1110 : (0,56:4,62); 1111 : (0,56:4,62); 1112 : (0,56:4,62); 1113 : (0,56:4,62); 1114 : (0,56:4,62); 1115 : (0,56:4,62); 1116 : (0,56:4,62); 1117 : (0,56:4,62); 1118 : (0,56:4,62); 1119 : (0,56:4,62); 1120 : (0,56:4,62); 1121 : (0,56:4,62); 1122 : (0,56:4,62); 1123 : (0,56:4,62); 1128 : (0,69:11,0); 1131 : (0,69:4,63); 1132 : (0,69:4,0); 1133 : (0,69:4,63); 1136 : (0,70:11,0); 1139 : (0,70:4,64); 1140 : (0,70:4,0); 1141 : (0,70:4,64); 1144 : (0,71:11,0); 1147 : (0,71:4,65); 1148 : (0,71:4,0); 1149 : (0,71:4,65); 1158 : (0,72:0,66); 1159 : (0,72:0,66); 1160 : (0,72:0,0); 1331 : (0,56:23,57); 1472 : (0,28:4,0); 1500 : (0,33:11,0); 1528 : (0,34:11,0); 1556 : (0,54:8,0); 1584 : (0,54:12,0); 1628 : (0,72:0,0); 1656 : (0,64:89,0); 1712 : (0,33:24,0); 1740 : (0,33:28,0); 1768 : (0,33:32,0); 1796 : (0,33:36,0); 1824 : (0,34:24,0); 1852 : (0,34:28,0); 1880 : (0,34:32,0); 1908 : (0,34:36,0); 1969 : (0,28:4,0); 1971 : (0,28:4,0); 1973 : (0,33:11,0); 1975 : (0,34:11,0); 1981 : (0,54:8,0); 1987 : (0,54:12,0); 1993 : (0,64:89,0); 1997 : (0,33:24,0); 2003 : (0,33:28,0); 2009 : (0,33:32,0); 2015 : (0,33:36,0); 2021 : (0,34:24,0); 2027 : (0,34:28,0); 2033 : (0,34:32,0); 2039 : (0,34:36,0); 2048 : (0,56:4,22); 2056 : (0,56:23,56); 2057 : (0,56:23,56); 2064 : (0,56:4,20); 2072 : (0,56:23,54); 2123 : (0,56:4,20); 2124 : (0,56:23,54); 2172 : (0,56:4,22); 2173 : (0,56:4,23); 2221 : (0,56:4,20); 2224 : (0,56:23,54); 2228 : (0,56:4,58); 2232 : (0,56:4,24);