// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 09:15:24 2026 // Copyright 2014-2025 Synopsys, Inc. All rights reserved. // C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32 /*** !! int sig_calc_biquad(SingleSignalPath *, int) F_Z15sig_calc_biquadP16SingleSignalPathi : user_defined, called { fnm : "sig_calc_biquad" 'int sig_calc_biquad(SingleSignalPath *, int)'; arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i ); loc : ( LR[0] RA[0] A[0] RA[1] ); vac : ( srIM[0] ); frm : ( ); } **** ***/ [ 0 : _Z15sig_calc_biquadP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___1 11 : __M_WDMA typ=int32_ bnd=d stl=WDMA 26 : __R_SP typ=dmaddr_ bnd=d stl=SP 34 : __sp typ=dmaddr_ bnd=b stl=SP 36 : __extDM_SingleSignalPath_preemph_activated typ=int8_ bnd=b stl=DM 38 : __extDM_SingleSignalPath_b_preemph typ=int8_ bnd=b stl=DM 39 : __extDM_SingleSignalPath__xd typ=int8_ bnd=b stl=DM 40 : __extDM_SingleSignalPath__yd typ=int8_ bnd=b stl=DM 41 : __rd___sp typ=dmaddr_ bnd=m 42 : __ct_0 typ=uint1_ val=0f bnd=m 43 : __la typ=dmaddr_ bnd=p tref=dmaddr___ 44 : __rt typ=int32_ bnd=p tref=__sint__ 45 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__ 46 : x typ=int32_ bnd=p tref=__sint__ 50 : sum typ=int72_ bnd=m lscp=591 tref=accum_t__ 55 : __fch___extDM_SingleSignalPath_preemph_activated typ=int32_ bnd=m 56 : __ct_0 typ=int32_ val=0f bnd=m 58 : __tmp typ=bool bnd=m 65 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m 66 : __tmp typ=int72_ bnd=m 73 : __fch___extDM_SingleSignalPath__xd typ=int32_ bnd=m 80 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m 81 : __tmp typ=int72_ bnd=m 82 : __tmp typ=int72_ bnd=m 89 : __fch___extDM_SingleSignalPath__xd typ=int32_ bnd=m 96 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m 97 : __tmp typ=int72_ bnd=m 98 : __tmp typ=int72_ bnd=m 105 : __fch___extDM_SingleSignalPath__yd typ=int32_ bnd=m 112 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m 113 : __tmp typ=int72_ bnd=m 114 : __tmp typ=int72_ bnd=m 121 : __fch___extDM_SingleSignalPath__yd typ=int32_ bnd=m 128 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m 129 : __tmp typ=int72_ bnd=m 131 : __ct_1 typ=int32_ val=1f bnd=m 133 : __tmp typ=int72_ bnd=m 197 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__ 232 : __ct_0S0 typ=int18_ val=0S0 bnd=m 233 : __ct_8 typ=int18_ val=8f bnd=m 236 : __ct_12 typ=int18_ val=12f bnd=m 239 : __ct_0s0 typ=int18_ val=0s0 bnd=m 240 : __ct_24 typ=int18_ val=24f bnd=m 242 : __ct_20 typ=int18_ val=20f bnd=m 244 : __ct_4 typ=int18_ val=4f bnd=m 248 : __tmp typ=uint3_ bnd=m 253 : __ct_0 typ=uint2_ val=0f bnd=m 263 : __either typ=bool bnd=m 264 : __trgt typ=int10_ val=0j bnd=m 265 : __trgt typ=int10_ val=0j bnd=m ] F_Z15sig_calc_biquadP16SingleSignalPathi { #553 off=0 (__M_WDMA.9 var=11) st_def () <18>; (__R_SP.24 var=26) st_def () <48>; (__sp.32 var=34) source () <56>; (__extDM_SingleSignalPath_preemph_activated.34 var=36) source () <58>; (__extDM_SingleSignalPath_b_preemph.36 var=38) source () <60>; (__extDM_SingleSignalPath__xd.37 var=39) source () <61>; (__extDM_SingleSignalPath__yd.38 var=40) source () <62>; (__ct_0.40 var=42) const () <64>; (__la.42 var=43 stl=LR off=0) inp () <66>; (__la.43 var=43) deassign (__la.42) <67>; (signal.46 var=45 stl=A off=0) inp () <70>; (signal.47 var=45) deassign (signal.46) <71>; (x.49 var=46 stl=RA off=1) inp () <73>; (x.50 var=46) deassign (x.49) <74>; (__rd___sp.52 var=41) rd_res_reg (__R_SP.24 __sp.32) <76>; (__R_SP.56 var=26 __sp.57 var=34) wr_res_reg (__rt.297 __sp.32) <80>; (__fch___extDM_SingleSignalPath_preemph_activated.63 var=55) load (__M_WDMA.9 __rt.319 __extDM_SingleSignalPath_preemph_activated.34) <87>; (__ct_0.64 var=56) const () <88>; (__rt.297 var=197) __Pvoid__pl___Pvoid_int18_ (__rd___sp.52 __ct_0S0.640) <391>; (__rt.319 var=197) __Pvoid__pl___Pvoid_int18_ (signal.47 __ct_8.641) <419>; (__ct_0S0.640 var=232) const () <840>; (__ct_8.641 var=233) const () <842>; (__tmp.655 var=248) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_preemph_activated.63 __ct_0.64) <869>; (__tmp.656 var=58) bool_equal_uint3_ (__tmp.655) <870>; (__trgt.669 var=264) const () <927>; () void_jump_bool_int10_ (__tmp.656 __trgt.669) <928>; (__either.670 var=263) undefined () <929>; if { { () if_expr (__either.670) <109>; } #5 { } #6 off=2 { (__fch___extDM_SingleSignalPath_b_preemph.92 var=65) load (__M_WDMA.9 __rt.341 __extDM_SingleSignalPath_b_preemph.36) <117>; (__fch___extDM_SingleSignalPath__xd.100 var=73) load (__M_WDMA.9 __rt.385 __extDM_SingleSignalPath__xd.37) <125>; (__fch___extDM_SingleSignalPath_b_preemph.107 var=80) load (__M_WDMA.9 __rt.407 __extDM_SingleSignalPath_b_preemph.36) <132>; (__tmp.109 var=82) accum_t__pl_accum_t_accum_t (__tmp.244 __tmp.249) <134>; (__fch___extDM_SingleSignalPath__xd.116 var=89) load (__M_WDMA.9 __rt.429 __extDM_SingleSignalPath__xd.37) <141>; (__fch___extDM_SingleSignalPath_b_preemph.123 var=96) load (__M_WDMA.9 __rt.451 __extDM_SingleSignalPath_b_preemph.36) <148>; (__tmp.125 var=98) accum_t__pl_accum_t_accum_t (__tmp.109 __tmp.254) <150>; (__fch___extDM_SingleSignalPath__yd.132 var=105) load (__M_WDMA.9 __rt.473 __extDM_SingleSignalPath__yd.38) <157>; (__fch___extDM_SingleSignalPath_b_preemph.139 var=112) load (__M_WDMA.9 __rt.495 __extDM_SingleSignalPath_b_preemph.36) <164>; (__tmp.141 var=114) accum_t__pl_accum_t_accum_t (__tmp.125 __tmp.259) <166>; (__fch___extDM_SingleSignalPath__yd.148 var=121) load (__M_WDMA.9 __rt.517 __extDM_SingleSignalPath__yd.38) <173>; (__fch___extDM_SingleSignalPath_b_preemph.155 var=128) load (__M_WDMA.9 __rt.539 __extDM_SingleSignalPath_b_preemph.36) <180>; (sum.157 var=50) accum_t__pl_accum_t_accum_t (__tmp.141 __tmp.264) <182>; (__ct_1.159 var=131) const () <184>; (__rt.162 var=44) __sint_rnd_saturate_accum_t (__tmp.661) <187>; (__M_WDMA.176 var=11 __extDM_SingleSignalPath__xd.177 var=39) store (__fch___extDM_SingleSignalPath__xd.100 __rt.561 __extDM_SingleSignalPath__xd.37) <201>; (__M_WDMA.184 var=11 __extDM_SingleSignalPath__xd.185 var=39) store (x.50 __rt.583 __extDM_SingleSignalPath__xd.177) <208>; (__M_WDMA.199 var=11 __extDM_SingleSignalPath__yd.200 var=40) store (__fch___extDM_SingleSignalPath__yd.132 __rt.605 __extDM_SingleSignalPath__yd.38) <222>; (__M_WDMA.207 var=11 __extDM_SingleSignalPath__yd.208 var=40) store (__rt.162 __rt.627 __extDM_SingleSignalPath__yd.200) <229>; (__tmp.244 var=66) int72__multss_int32__int32__uint1_ (x.50 __fch___extDM_SingleSignalPath_b_preemph.92 __ct_0.40) <293>; (__tmp.249 var=81) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__xd.100 __fch___extDM_SingleSignalPath_b_preemph.107 __ct_0.40) <301>; (__tmp.254 var=97) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__xd.116 __fch___extDM_SingleSignalPath_b_preemph.123 __ct_0.40) <309>; (__tmp.259 var=113) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__yd.132 __fch___extDM_SingleSignalPath_b_preemph.139 __ct_0.40) <317>; (__tmp.264 var=129) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__yd.148 __fch___extDM_SingleSignalPath_b_preemph.155 __ct_0.40) <325>; (__rt.341 var=197) __Pvoid__pl___Pvoid_int18_ (signal.47 __ct_12.644) <447>; (__rt.385 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.341 __ct_24.648) <503>; (__rt.407 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.385 __ct_20.650) <531>; (__rt.429 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.407 __ct_24.648) <559>; (__rt.451 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.429 __ct_20.650) <587>; (__rt.473 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.451 __ct_24.648) <615>; (__rt.495 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.473 __ct_20.650) <643>; (__rt.517 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.495 __ct_24.648) <671>; (__rt.539 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.517 __ct_20.650) <699>; (__rt.561 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.539 __ct_12.644) <727>; (__rt.583 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.561 __ct_4.652) <755>; (__rt.605 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.583 __ct_12.644) <783>; (__rt.627 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.605 __ct_4.652) <811>; (__ct_12.644 var=236) const () <848>; (__ct_24.648 var=240) const () <856>; (__ct_20.650 var=242) const () <860>; (__ct_4.652 var=244) const () <864>; (__ct_0.660 var=253) const () <877>; (__tmp.661 var=133) int72__shift_int72__int72__uint2_ (sum.157 __ct_1.159 __ct_0.660) <878>; (__trgt.671 var=265) const () <930>; () void_jump_int10_ (__trgt.671) <931>; } #591 off=1 { (__extDM_SingleSignalPath__xd.209 var=39) merge (__extDM_SingleSignalPath__xd.37 __extDM_SingleSignalPath__xd.185) <230>; (__extDM_SingleSignalPath__yd.210 var=40) merge (__extDM_SingleSignalPath__yd.38 __extDM_SingleSignalPath__yd.208) <231>; (__rt.211 var=44) merge (x.50 __rt.162) <232>; } #8 } #4 #10 off=3 nxt=-2 (__rd___sp.214 var=41) rd_res_reg (__R_SP.24 __sp.57) <235>; (__R_SP.218 var=26 __sp.219 var=34) wr_res_reg (__rt.363 __sp.57) <239>; () void_ret_dmaddr_ (__la.43) <240>; (__rt.220 var=44 stl=RA off=0) assign (__rt.211) <241>; () out (__rt.220) <242>; () sink (__sp.219) <248>; () sink (__extDM_SingleSignalPath__xd.209) <253>; () sink (__extDM_SingleSignalPath__yd.210) <254>; () sink (__ct_0.40) <255>; (__rt.363 var=197) __Pvoid__pl___Pvoid_int18_ (__rd___sp.214 __ct_0s0.647) <475>; (__ct_0s0.647 var=239) const () <854>; } #0 0 : 'signal_processing\\signal_path.c'; ---------- 0 : (0,179:0,0); 4 : (0,180:4,1); 6 : (0,180:40,2); 10 : (0,194:4,16); 553 : (0,180:34,1); 591 : (0,193:15,11); ---------- 76 : (0,179:4,0); 80 : (0,179:4,0); 87 : (0,180:14,1); 88 : (0,180:37,0); 109 : (0,180:4,1); 117 : (0,184:39,6); 125 : (0,184:68,6); 132 : (0,184:90,6); 134 : (0,184:44,6); 141 : (0,185:30,6); 148 : (0,185:52,6); 150 : (0,184:95,6); 157 : (0,185:81,6); 164 : (0,185:103,6); 166 : (0,185:57,6); 173 : (0,186:30,6); 180 : (0,186:51,6); 182 : (0,185:108,6); 184 : (0,187:32,0); 187 : (0,187:12,7); 201 : (0,190:15,8); 208 : (0,191:15,9); 222 : (0,192:15,10); 229 : (0,193:15,11); 230 : (0,180:4,15); 231 : (0,180:4,15); 232 : (0,180:4,15); 235 : (0,194:4,0); 239 : (0,194:4,16); 240 : (0,194:4,16); 241 : (0,194:4,0); 293 : (0,184:8,6); 301 : (0,184:46,6); 309 : (0,185:8,6); 317 : (0,185:59,6); 325 : (0,186:8,6); 391 : (0,179:4,0); 419 : (0,180:14,1); 447 : (0,184:28,6); 475 : (0,194:4,0); 503 : (0,184:63,0); 531 : (0,184:90,0); 559 : (0,185:30,0); 587 : (0,185:52,0); 615 : (0,185:76,0); 643 : (0,185:103,0); 671 : (0,186:30,0); 699 : (0,186:51,0); 727 : (0,185:30,0); 755 : (0,184:63,0); 783 : (0,186:30,0); 811 : (0,185:76,0); 840 : (0,179:4,0); 842 : (0,180:14,0); 848 : (0,184:28,0); 854 : (0,194:4,0); 856 : (0,184:63,0); 860 : (0,184:90,0); 864 : (0,184:63,0); 869 : (0,180:34,1); 870 : (0,180:34,1); 877 : (0,187:29,0); 878 : (0,187:29,7); 928 : (0,180:4,1);