Calc-Funktion weiter, unnötige Funktionen auskommentiert (kompiliert)
This commit is contained in:
Patrick Hangl
736
simulation/Release/chesswork/signal_path-6dff42.sfg
Normal file
736
simulation/Release/chesswork/signal_path-6dff42.sfg
Normal file
@@ -0,0 +1,736 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)
|
||||
F_Z20scale_preemph_filterP16SingleSignalPathdddddi : user_defined, called {
|
||||
fnm : "scale_preemph_filter" 'void scale_preemph_filter(SingleSignalPath *, double, double, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! extern double ff_pow(double, double)
|
||||
Fff_pow : user_defined, called {
|
||||
fnm : "ff_pow" 'double ff_pow(double, double)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int float64_eq(float64, float64)
|
||||
F_Z10float64_eqyy : user_defined, called {
|
||||
fnm : "float64_eq" 'int float64_eq(float64, float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] AX[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 int32_to_float64(int)
|
||||
F_Z16int32_to_float64i : user_defined, called {
|
||||
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
|
||||
arg : ( dmaddr_:i int64_:r int32_:i );
|
||||
loc : ( LR[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_sub(float64, float64)
|
||||
F_Z11float64_subyy : user_defined, called {
|
||||
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! int float64_to_int32_round_to_zero(float64)
|
||||
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
|
||||
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_mul(float64, float64)
|
||||
F_Z11float64_mulyy : user_defined, called {
|
||||
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z20scale_preemph_filterP16SingleSignalPathdddddi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___fdouble___fdouble___fdouble___fdouble___fdouble___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_SingleSignalPath_preemph_activated typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath__preemph_scale_nbits typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_SingleSignalPath_b_preemph typ=int8_ bnd=b stl=DM
|
||||
40 : __rd___sp typ=dmaddr_ bnd=m
|
||||
41 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
42 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
44 : b0 typ=int64_ bnd=p tref=__fdouble__
|
||||
45 : b1 typ=int64_ bnd=p tref=__fdouble__
|
||||
46 : b2 typ=int64_ bnd=p tref=__fdouble__
|
||||
47 : a1 typ=int64_ bnd=p tref=__fdouble__
|
||||
48 : a2 typ=int64_ bnd=p tref=__fdouble__
|
||||
49 : scale_bits typ=int32_ bnd=p tref=__sint__
|
||||
53 : __tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
|
||||
54 : __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
|
||||
56 : scale typ=int32_ bnd=m lscp=247 tref=__sint__
|
||||
57 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
|
||||
60 : __ct_0 typ=uint40_ val=0f bnd=m
|
||||
65 : __tmp typ=bool bnd=m
|
||||
71 : __tmp typ=bool bnd=m
|
||||
77 : __tmp typ=bool bnd=m
|
||||
83 : __tmp typ=bool bnd=m
|
||||
84 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
89 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
98 : __ct_4611686018427387904 typ=int64_ val=4611686018427387904f bnd=m
|
||||
103 : __tmp typ=int64_ bnd=m
|
||||
105 : __tmp typ=int64_ bnd=m
|
||||
106 : __tmp typ=int64_ bnd=m
|
||||
107 : __tmp typ=int32_ bnd=m
|
||||
115 : __tmp typ=int64_ bnd=m
|
||||
116 : __tmp typ=int32_ bnd=m
|
||||
124 : __tmp typ=int64_ bnd=m
|
||||
125 : __tmp typ=int32_ bnd=m
|
||||
133 : __tmp typ=int64_ bnd=m
|
||||
134 : __tmp typ=int32_ bnd=m
|
||||
142 : __tmp typ=int64_ bnd=m
|
||||
143 : __tmp typ=int32_ bnd=m
|
||||
164 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
185 : __tmp typ=int32_ bnd=m
|
||||
202 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
203 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
206 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
207 : __ct_24 typ=int18_ val=24f bnd=m
|
||||
209 : __ct_20 typ=int18_ val=20f bnd=m
|
||||
210 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
214 : __tmp typ=bool bnd=m
|
||||
225 : __a0 typ=int64_ bnd=m tref=__atp0___48
|
||||
227 : ff_pow typ=dmaddr_ val=0r bnd=m
|
||||
228 : __link typ=dmaddr_ bnd=m
|
||||
253 : __a1 typ=int64_ bnd=m tref=__atp1___12
|
||||
254 : _Z10float64_eqyy typ=dmaddr_ val=0r bnd=m
|
||||
255 : __link typ=dmaddr_ bnd=m
|
||||
265 : __tmp typ=uint3_ bnd=m
|
||||
274 : _Z16int32_to_float64i typ=dmaddr_ val=0r bnd=m
|
||||
275 : __link typ=dmaddr_ bnd=m
|
||||
277 : __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi typ=int64_ bnd=m
|
||||
279 : __a1 typ=int64_ bnd=m tref=__atp1___9
|
||||
280 : _Z11float64_subyy typ=dmaddr_ val=0r bnd=m
|
||||
281 : __link typ=dmaddr_ bnd=m
|
||||
283 : __tmp typ=int64_ bnd=m
|
||||
285 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
|
||||
286 : __link typ=dmaddr_ bnd=m
|
||||
289 : __tmp typ=int64_ bnd=m
|
||||
292 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
|
||||
293 : __link typ=dmaddr_ bnd=m
|
||||
295 : __tmp typ=int64_ bnd=m
|
||||
297 : __tmp typ=int64_ bnd=m
|
||||
299 : __tmp typ=int64_ bnd=m
|
||||
301 : __tmp typ=int64_ bnd=m
|
||||
303 : __tmp typ=int64_ bnd=m
|
||||
311 : __true typ=bool val=1f bnd=m
|
||||
312 : __false typ=bool val=0f bnd=m
|
||||
313 : __either typ=bool bnd=m
|
||||
314 : __trgt typ=int10_ val=0j bnd=m
|
||||
315 : __trgt typ=int10_ val=0j bnd=m
|
||||
316 : __trgt typ=int10_ val=0j bnd=m
|
||||
317 : __trgt typ=int10_ val=0j bnd=m
|
||||
318 : __trgt typ=int10_ val=0j bnd=m
|
||||
319 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z20scale_preemph_filterP16SingleSignalPathdddddi {
|
||||
#482 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath_preemph_activated.34 var=36) source () <58>;
|
||||
(__extDM_SingleSignalPath__preemph_scale_nbits.36 var=38) source () <60>;
|
||||
(__extDM_SingleSignalPath_b_preemph.37 var=39) source () <61>;
|
||||
(__ct_0.39 var=41) const () <63>;
|
||||
(__la.41 var=42 stl=LR off=0) inp () <65>;
|
||||
(__la.42 var=42) deassign (__la.41) <66>;
|
||||
(signal.44 var=43 stl=A off=0) inp () <68>;
|
||||
(signal.45 var=43) deassign (signal.44) <69>;
|
||||
(b0.47 var=44 stl=AX off=0) inp () <71>;
|
||||
(b0.48 var=44) deassign (b0.47) <72>;
|
||||
(b1.50 var=45 stl=AX off=1) inp () <74>;
|
||||
(b1.51 var=45) deassign (b1.50) <75>;
|
||||
(b2.53 var=46 stl=BX off=0) inp () <77>;
|
||||
(b2.54 var=46) deassign (b2.53) <78>;
|
||||
(a1.56 var=47 stl=BX off=1) inp () <80>;
|
||||
(a1.57 var=47) deassign (a1.56) <81>;
|
||||
(a2.59 var=48 stl=__spill_LDMA off=0) inp () <83>;
|
||||
(a2.60 var=48) deassign (a2.59) <84>;
|
||||
(scale_bits.62 var=49 stl=RA off=0) inp () <86>;
|
||||
(scale_bits.63 var=49) deassign (scale_bits.62) <87>;
|
||||
(__rd___sp.65 var=40) rd_res_reg (__R_SP.24 __sp.32) <89>;
|
||||
(__R_SP.69 var=26 __sp.70 var=34) wr_res_reg (__rt.365 __sp.32) <93>;
|
||||
(__ct_4607182418800017408.75 var=57) const () <99>;
|
||||
(__rt.365 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.65 __ct_0S0.584) <447>;
|
||||
(__ct_0S0.584 var=202) const () <747>;
|
||||
(_Z10float64_eqyy.680 var=254) const () <927>;
|
||||
(__link.681 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <928>;
|
||||
call {
|
||||
(b0.682 var=44 stl=AX off=0) assign (b0.48) <929>;
|
||||
(__a1.683 var=253 stl=AX off=1) assign (__ct_4607182418800017408.75) <930>;
|
||||
(__link.684 var=255 stl=LR off=0) assign (__link.681) <931>;
|
||||
(__tmp.685 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.684 b0.682 __a1.683) <932>;
|
||||
(__tmp.686 var=185) deassign (__tmp.685) <933>;
|
||||
} #483 off=1
|
||||
#479 off=2
|
||||
(__ct_0.101 var=60) const () <126>;
|
||||
(__ct_0.217 var=84) const () <246>;
|
||||
(__rt.417 var=164) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_8.585) <520>;
|
||||
(__ct_8.585 var=203) const () <749>;
|
||||
(__tmp.730 var=265) uint3__cmp_int72__int72_ (__tmp.686 __ct_0.217) <992>;
|
||||
(__tmp.888 var=214) bool_equal_uint3_ (__tmp.730) <1262>;
|
||||
(__trgt.897 var=314) const () <1291>;
|
||||
() void_jump_bool_int10_ (__tmp.888 __trgt.897) <1292>;
|
||||
(__either.898 var=313) undefined () <1293>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.898) <125>;
|
||||
} #5
|
||||
{
|
||||
(__true.899 var=311) const () <1294>;
|
||||
} #7
|
||||
{
|
||||
#491 off=3
|
||||
(__link.691 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <941>;
|
||||
call {
|
||||
(b1.692 var=45 stl=AX off=0) assign (b1.51) <942>;
|
||||
(__a1.693 var=253 stl=AX off=1) assign (__ct_0.101) <943>;
|
||||
(__link.694 var=255 stl=LR off=0) assign (__link.691) <944>;
|
||||
(__tmp.695 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.694 b1.692 __a1.693) <945>;
|
||||
(__tmp.696 var=185) deassign (__tmp.695) <946>;
|
||||
} #492 off=4
|
||||
#488 off=5
|
||||
(__tmp.735 var=265) uint3__cmp_int72__int72_ (__tmp.696 __ct_0.217) <1000>;
|
||||
(__tmp.889 var=214) bool_equal_uint3_ (__tmp.735) <1263>;
|
||||
(__trgt.900 var=315) const () <1295>;
|
||||
() void_jump_bool_int10_ (__tmp.889 __trgt.900) <1296>;
|
||||
(__either.901 var=313) undefined () <1297>;
|
||||
} #383
|
||||
{
|
||||
(__tmp.890 var=65) merge (__true.899 __either.901) <1264>;
|
||||
} #8
|
||||
} #4
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.890) <155>;
|
||||
} #11
|
||||
{
|
||||
(__true.902 var=311) const () <1298>;
|
||||
} #13
|
||||
{
|
||||
#500 off=6
|
||||
(__link.701 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <954>;
|
||||
call {
|
||||
(b2.702 var=46 stl=AX off=0) assign (b2.54) <955>;
|
||||
(__a1.703 var=253 stl=AX off=1) assign (__ct_0.101) <956>;
|
||||
(__link.704 var=255 stl=LR off=0) assign (__link.701) <957>;
|
||||
(__tmp.705 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.704 b2.702 __a1.703) <958>;
|
||||
(__tmp.706 var=185) deassign (__tmp.705) <959>;
|
||||
} #501 off=7
|
||||
#497 off=8
|
||||
(__tmp.740 var=265) uint3__cmp_int72__int72_ (__tmp.706 __ct_0.217) <1008>;
|
||||
(__tmp.891 var=214) bool_equal_uint3_ (__tmp.740) <1265>;
|
||||
(__trgt.903 var=316) const () <1299>;
|
||||
() void_jump_bool_int10_ (__tmp.891 __trgt.903) <1300>;
|
||||
(__either.904 var=313) undefined () <1301>;
|
||||
} #388
|
||||
{
|
||||
(__tmp.892 var=71) merge (__true.902 __either.904) <1266>;
|
||||
} #14
|
||||
} #10
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.892) <185>;
|
||||
} #17
|
||||
{
|
||||
(__true.905 var=311) const () <1302>;
|
||||
} #19
|
||||
{
|
||||
#509 off=9
|
||||
(__link.711 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <967>;
|
||||
call {
|
||||
(a1.712 var=47 stl=AX off=0) assign (a1.57) <968>;
|
||||
(__a1.713 var=253 stl=AX off=1) assign (__ct_0.101) <969>;
|
||||
(__link.714 var=255 stl=LR off=0) assign (__link.711) <970>;
|
||||
(__tmp.715 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.714 a1.712 __a1.713) <971>;
|
||||
(__tmp.716 var=185) deassign (__tmp.715) <972>;
|
||||
} #510 off=10
|
||||
#506 off=11
|
||||
(__tmp.745 var=265) uint3__cmp_int72__int72_ (__tmp.716 __ct_0.217) <1016>;
|
||||
(__tmp.893 var=214) bool_equal_uint3_ (__tmp.745) <1267>;
|
||||
(__trgt.906 var=317) const () <1303>;
|
||||
() void_jump_bool_int10_ (__tmp.893 __trgt.906) <1304>;
|
||||
(__either.907 var=313) undefined () <1305>;
|
||||
} #393
|
||||
{
|
||||
(__tmp.894 var=77) merge (__true.905 __either.907) <1268>;
|
||||
} #20
|
||||
} #16
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.894) <215>;
|
||||
} #23
|
||||
{
|
||||
(__false.908 var=312) const () <1306>;
|
||||
} #25
|
||||
{
|
||||
#518 off=12
|
||||
(__link.721 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <980>;
|
||||
call {
|
||||
(a2.722 var=48 stl=AX off=0) assign (a2.60) <981>;
|
||||
(__a1.723 var=253 stl=AX off=1) assign (__ct_0.101) <982>;
|
||||
(__link.724 var=255 stl=LR off=0) assign (__link.721) <983>;
|
||||
(__tmp.725 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.724 a2.722 __a1.723) <984>;
|
||||
(__tmp.726 var=185) deassign (__tmp.725) <985>;
|
||||
} #519 off=13
|
||||
#515 off=14
|
||||
(__tmp.750 var=265) uint3__cmp_int72__int72_ (__tmp.726 __ct_0.217) <1024>;
|
||||
(__tmp.759 var=214) bool_nequal_uint3_ (__tmp.750) <1051>;
|
||||
(__trgt.909 var=318) const () <1307>;
|
||||
() void_jump_bool_int10_ (__tmp.759 __trgt.909) <1308>;
|
||||
(__either.910 var=313) undefined () <1309>;
|
||||
} #398
|
||||
{
|
||||
(__tmp.193 var=83) merge (__false.908 __either.910) <221>;
|
||||
} #26
|
||||
} #22
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.193) <245>;
|
||||
} #29
|
||||
{
|
||||
(__M_WDMA.222 var=11 __extDM_SingleSignalPath_preemph_activated.223 var=36) store (__ct_0.217 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <251>;
|
||||
} #30 off=46
|
||||
{
|
||||
#545 off=15
|
||||
(__ct_1.224 var=89) const () <252>;
|
||||
(__M_WDMA.229 var=11 __extDM_SingleSignalPath_preemph_activated.230 var=36) store (__ct_1.224 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <257>;
|
||||
(__M_WDMA.234 var=11 __extDM_SingleSignalPath__preemph_scale_nbits.235 var=38) store (scale_bits.63 __rt.461 __extDM_SingleSignalPath__preemph_scale_nbits.36) <261>;
|
||||
(__rt.461 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.417 __ct_24.589) <576>;
|
||||
(__rt.483 var=164) __Pvoid__mi___Pvoid_int18_ (__rt.461 __ct_20.591) <604>;
|
||||
(__ct_24.589 var=207) const () <757>;
|
||||
(__ct_20.591 var=209) const () <761>;
|
||||
(_Z16int32_to_float64i.761 var=274) const () <1054>;
|
||||
(__link.762 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1055>;
|
||||
call {
|
||||
(scale_bits.763 var=49 stl=RA off=0) assign (scale_bits.63) <1056>;
|
||||
(__link.764 var=275 stl=LR off=0) assign (__link.762) <1057>;
|
||||
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.765 var=277 stl=AX off=0) F_Z16int32_to_float64i (__link.764 scale_bits.763) <1058>;
|
||||
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.766 var=54) deassign (__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.765) <1059>;
|
||||
} #546 off=16
|
||||
#542 off=17
|
||||
(__ct_4611686018427387904.241 var=98) const () <267>;
|
||||
(ff_pow.625 var=227) const () <830>;
|
||||
(__link.626 var=228) dmaddr__call_dmaddr_ (ff_pow.625) <831>;
|
||||
call {
|
||||
(__a0.627 var=225 stl=AX off=1) assign (__ct_4611686018427387904.241) <832>;
|
||||
(__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.628 var=54 stl=BX off=0) assign (__tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.766) <833>;
|
||||
(__link.629 var=228 stl=LR off=0) assign (__link.626) <834>;
|
||||
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.630 var=53 stl=AX off=0) Fff_pow (__link.629 __a0.627 __tmpb2_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.628) <835>;
|
||||
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.631 var=53) deassign (__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.630) <836>;
|
||||
} #434 off=18
|
||||
#573 off=19
|
||||
(_Z11float64_subyy.770 var=280) const () <1066>;
|
||||
(__link.771 var=281) dmaddr__call_dmaddr_ (_Z11float64_subyy.770) <1067>;
|
||||
call {
|
||||
(__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.772 var=53 stl=AX off=1) assign (__tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.631) <1068>;
|
||||
(__a1.773 var=279 stl=BX off=0) assign (__ct_4607182418800017408.75) <1069>;
|
||||
(__link.774 var=281 stl=LR off=0) assign (__link.771) <1070>;
|
||||
(__tmp.775 var=283 stl=AX off=0) F_Z11float64_subyy (__link.774 __tmpb0_F_Z20scale_preemph_filterP16SingleSignalPathdddddi.772 __a1.773) <1071>;
|
||||
(__tmp.776 var=103) deassign (__tmp.775) <1072>;
|
||||
} #574 off=20
|
||||
#579 off=21
|
||||
(_Z30float64_to_int32_round_to_zeroy.779 var=285) const () <1078>;
|
||||
(__link.780 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1079>;
|
||||
call {
|
||||
(__tmp.781 var=103 stl=AX off=0) assign (__tmp.776) <1080>;
|
||||
(__link.782 var=286 stl=LR off=0) assign (__link.780) <1081>;
|
||||
(scale.783 var=56 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.782 __tmp.781) <1082>;
|
||||
(scale.784 var=56) deassign (scale.783) <1083>;
|
||||
} #580 off=22
|
||||
#585 off=23
|
||||
(__link.788 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1090>;
|
||||
call {
|
||||
(scale.789 var=56 stl=RA off=0) assign (scale.784) <1091>;
|
||||
(__link.790 var=275 stl=LR off=0) assign (__link.788) <1092>;
|
||||
(__tmp.791 var=289 stl=AX off=0) F_Z16int32_to_float64i (__link.790 scale.789) <1093>;
|
||||
(__tmp.792 var=105) deassign (__tmp.791) <1094>;
|
||||
} #586 off=24
|
||||
#591 off=25
|
||||
(_Z11float64_mulyy.796 var=292) const () <1101>;
|
||||
(__link.797 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1102>;
|
||||
call {
|
||||
(b0.798 var=44 stl=AX off=1) assign (b0.48) <1103>;
|
||||
(__tmp.799 var=105 stl=BX off=0) assign (__tmp.792) <1104>;
|
||||
(__link.800 var=293 stl=LR off=0) assign (__link.797) <1105>;
|
||||
(__tmp.801 var=295 stl=AX off=0) F_Z11float64_mulyy (__link.800 b0.798 __tmp.799) <1106>;
|
||||
(__tmp.802 var=106) deassign (__tmp.801) <1107>;
|
||||
} #592 off=26
|
||||
#597 off=27
|
||||
(__link.806 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1114>;
|
||||
call {
|
||||
(__tmp.807 var=106 stl=AX off=0) assign (__tmp.802) <1115>;
|
||||
(__link.808 var=286 stl=LR off=0) assign (__link.806) <1116>;
|
||||
(__tmp.809 var=107 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.808 __tmp.807) <1117>;
|
||||
(__tmp.810 var=107) deassign (__tmp.809) <1118>;
|
||||
} #598 off=28
|
||||
#603 off=29
|
||||
(__M_WDMA.257 var=11 __extDM_SingleSignalPath_b_preemph.258 var=39) store (__tmp.810 __rt.483 __extDM_SingleSignalPath_b_preemph.37) <283>;
|
||||
(__rt.505 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.483 __ct_4.592) <632>;
|
||||
(__ct_4.592 var=210) const () <763>;
|
||||
(__link.815 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1126>;
|
||||
call {
|
||||
(b1.816 var=45 stl=AX off=1) assign (b1.51) <1127>;
|
||||
(__tmp.817 var=105 stl=BX off=0) assign (__tmp.792) <1128>;
|
||||
(__link.818 var=293 stl=LR off=0) assign (__link.815) <1129>;
|
||||
(__tmp.819 var=297 stl=AX off=0) F_Z11float64_mulyy (__link.818 b1.816 __tmp.817) <1130>;
|
||||
(__tmp.820 var=115) deassign (__tmp.819) <1131>;
|
||||
} #604 off=30
|
||||
#609 off=31
|
||||
(__link.824 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1138>;
|
||||
call {
|
||||
(__tmp.825 var=115 stl=AX off=0) assign (__tmp.820) <1139>;
|
||||
(__link.826 var=286 stl=LR off=0) assign (__link.824) <1140>;
|
||||
(__tmp.827 var=116 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.826 __tmp.825) <1141>;
|
||||
(__tmp.828 var=116) deassign (__tmp.827) <1142>;
|
||||
} #610 off=32
|
||||
#615 off=33
|
||||
(__M_WDMA.268 var=11 __extDM_SingleSignalPath_b_preemph.269 var=39) store (__tmp.828 __rt.505 __extDM_SingleSignalPath_b_preemph.258) <293>;
|
||||
(__rt.527 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.505 __ct_4.592) <660>;
|
||||
(__link.833 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1150>;
|
||||
call {
|
||||
(b2.834 var=46 stl=AX off=1) assign (b2.54) <1151>;
|
||||
(__tmp.835 var=105 stl=BX off=0) assign (__tmp.792) <1152>;
|
||||
(__link.836 var=293 stl=LR off=0) assign (__link.833) <1153>;
|
||||
(__tmp.837 var=299 stl=AX off=0) F_Z11float64_mulyy (__link.836 b2.834 __tmp.835) <1154>;
|
||||
(__tmp.838 var=124) deassign (__tmp.837) <1155>;
|
||||
} #616 off=34
|
||||
#621 off=35
|
||||
(__link.842 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1162>;
|
||||
call {
|
||||
(__tmp.843 var=124 stl=AX off=0) assign (__tmp.838) <1163>;
|
||||
(__link.844 var=286 stl=LR off=0) assign (__link.842) <1164>;
|
||||
(__tmp.845 var=125 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.844 __tmp.843) <1165>;
|
||||
(__tmp.846 var=125) deassign (__tmp.845) <1166>;
|
||||
} #622 off=36
|
||||
#627 off=37
|
||||
(__M_WDMA.279 var=11 __extDM_SingleSignalPath_b_preemph.280 var=39) store (__tmp.846 __rt.527 __extDM_SingleSignalPath_b_preemph.269) <303>;
|
||||
(__rt.549 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.527 __ct_4.592) <688>;
|
||||
(__link.851 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1174>;
|
||||
call {
|
||||
(a1.852 var=47 stl=AX off=1) assign (a1.57) <1175>;
|
||||
(__tmp.853 var=105 stl=BX off=0) assign (__tmp.792) <1176>;
|
||||
(__link.854 var=293 stl=LR off=0) assign (__link.851) <1177>;
|
||||
(__tmp.855 var=301 stl=AX off=0) F_Z11float64_mulyy (__link.854 a1.852 __tmp.853) <1178>;
|
||||
(__tmp.856 var=133) deassign (__tmp.855) <1179>;
|
||||
} #628 off=38
|
||||
#633 off=39
|
||||
(__link.860 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1186>;
|
||||
call {
|
||||
(__tmp.861 var=133 stl=AX off=0) assign (__tmp.856) <1187>;
|
||||
(__link.862 var=286 stl=LR off=0) assign (__link.860) <1188>;
|
||||
(__tmp.863 var=134 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.862 __tmp.861) <1189>;
|
||||
(__tmp.864 var=134) deassign (__tmp.863) <1190>;
|
||||
} #634 off=40
|
||||
#639 off=41
|
||||
(__M_WDMA.290 var=11 __extDM_SingleSignalPath_b_preemph.291 var=39) store (__tmp.864 __rt.549 __extDM_SingleSignalPath_b_preemph.280) <313>;
|
||||
(__rt.571 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.549 __ct_4.592) <716>;
|
||||
(__link.869 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1198>;
|
||||
call {
|
||||
(a2.870 var=48 stl=AX off=1) assign (a2.60) <1199>;
|
||||
(__tmp.871 var=105 stl=BX off=0) assign (__tmp.792) <1200>;
|
||||
(__link.872 var=293 stl=LR off=0) assign (__link.869) <1201>;
|
||||
(__tmp.873 var=303 stl=AX off=0) F_Z11float64_mulyy (__link.872 a2.870 __tmp.871) <1202>;
|
||||
(__tmp.874 var=142) deassign (__tmp.873) <1203>;
|
||||
} #640 off=42
|
||||
#645 off=43
|
||||
(__link.878 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1210>;
|
||||
call {
|
||||
(__tmp.879 var=142 stl=AX off=0) assign (__tmp.874) <1211>;
|
||||
(__link.880 var=286 stl=LR off=0) assign (__link.878) <1212>;
|
||||
(__tmp.881 var=143 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.880 __tmp.879) <1213>;
|
||||
(__tmp.882 var=143) deassign (__tmp.881) <1214>;
|
||||
} #646 off=44
|
||||
#570 off=45
|
||||
(__M_WDMA.301 var=11 __extDM_SingleSignalPath_b_preemph.302 var=39) store (__tmp.882 __rt.571 __extDM_SingleSignalPath_b_preemph.291) <323>;
|
||||
(__trgt.911 var=319) const () <1310>;
|
||||
() void_jump_int10_ (__trgt.911) <1311>;
|
||||
} #247
|
||||
{
|
||||
(__extDM_SingleSignalPath_preemph_activated.303 var=36) merge (__extDM_SingleSignalPath_preemph_activated.223 __extDM_SingleSignalPath_preemph_activated.230) <324>;
|
||||
(__extDM_SingleSignalPath__preemph_scale_nbits.304 var=38) merge (__extDM_SingleSignalPath__preemph_scale_nbits.36 __extDM_SingleSignalPath__preemph_scale_nbits.235) <325>;
|
||||
(__extDM_SingleSignalPath_b_preemph.305 var=39) merge (__extDM_SingleSignalPath_b_preemph.37 __extDM_SingleSignalPath_b_preemph.302) <326>;
|
||||
} #32
|
||||
} #28
|
||||
#34 off=47 nxt=-2
|
||||
(__rd___sp.310 var=40) rd_res_reg (__R_SP.24 __sp.70) <331>;
|
||||
(__R_SP.314 var=26 __sp.315 var=34) wr_res_reg (__rt.439 __sp.70) <335>;
|
||||
() void_ret_dmaddr_ (__la.42) <336>;
|
||||
() sink (__sp.315) <342>;
|
||||
() sink (__extDM_SingleSignalPath_preemph_activated.303) <344>;
|
||||
() sink (__extDM_SingleSignalPath__preemph_scale_nbits.304) <346>;
|
||||
() sink (__extDM_SingleSignalPath_b_preemph.305) <347>;
|
||||
() sink (__ct_0.39) <348>;
|
||||
(__rt.439 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.310 __ct_0s0.588) <548>;
|
||||
(__ct_0s0.588 var=206) const () <755>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,182:0,0);
|
||||
4 : (0,184:17,1);
|
||||
7 : (0,184:17,3);
|
||||
10 : (0,184:29,5);
|
||||
13 : (0,184:29,7);
|
||||
16 : (0,184:41,9);
|
||||
19 : (0,184:41,11);
|
||||
22 : (0,184:53,13);
|
||||
25 : (0,184:53,15);
|
||||
28 : (0,184:4,17);
|
||||
30 : (0,184:66,18);
|
||||
34 : (0,198:0,42);
|
||||
247 : (0,196:25,38);
|
||||
383 : (0,184:23,2);
|
||||
388 : (0,184:35,6);
|
||||
393 : (0,184:47,10);
|
||||
398 : (0,184:59,14);
|
||||
434 : (0,190:20,30);
|
||||
479 : (0,184:11,1);
|
||||
482 : (0,184:11,1);
|
||||
483 : (0,184:11,1);
|
||||
488 : (0,184:23,2);
|
||||
491 : (0,184:23,2);
|
||||
492 : (0,184:23,2);
|
||||
497 : (0,184:35,6);
|
||||
500 : (0,184:35,6);
|
||||
501 : (0,184:35,6);
|
||||
506 : (0,184:47,10);
|
||||
509 : (0,184:47,10);
|
||||
510 : (0,184:47,10);
|
||||
515 : (0,184:59,14);
|
||||
518 : (0,184:59,14);
|
||||
519 : (0,184:59,14);
|
||||
542 : (0,190:20,30);
|
||||
545 : (0,190:25,27);
|
||||
546 : (0,190:25,27);
|
||||
570 : (0,196:25,38);
|
||||
573 : (0,190:39,33);
|
||||
574 : (0,190:39,33);
|
||||
579 : (0,190:39,33);
|
||||
580 : (0,190:39,33);
|
||||
585 : (0,192:34,34);
|
||||
586 : (0,192:34,34);
|
||||
591 : (0,192:34,34);
|
||||
592 : (0,192:34,34);
|
||||
597 : (0,192:29,34);
|
||||
598 : (0,192:29,34);
|
||||
603 : (0,193:34,35);
|
||||
604 : (0,193:34,35);
|
||||
609 : (0,193:29,35);
|
||||
610 : (0,193:29,35);
|
||||
615 : (0,194:34,36);
|
||||
616 : (0,194:34,36);
|
||||
621 : (0,194:29,36);
|
||||
622 : (0,194:29,36);
|
||||
627 : (0,195:34,37);
|
||||
628 : (0,195:34,37);
|
||||
633 : (0,195:29,37);
|
||||
634 : (0,195:29,37);
|
||||
639 : (0,196:34,38);
|
||||
640 : (0,196:34,38);
|
||||
645 : (0,196:29,38);
|
||||
646 : (0,196:29,38);
|
||||
----------
|
||||
89 : (0,182:5,0);
|
||||
93 : (0,182:5,0);
|
||||
99 : (0,184:14,0);
|
||||
125 : (0,184:17,1);
|
||||
126 : (0,184:26,0);
|
||||
155 : (0,184:29,5);
|
||||
185 : (0,184:41,9);
|
||||
215 : (0,184:53,13);
|
||||
221 : (0,184:53,16);
|
||||
245 : (0,184:4,17);
|
||||
246 : (0,185:36,0);
|
||||
251 : (0,185:14,18);
|
||||
252 : (0,188:36,0);
|
||||
257 : (0,188:14,21);
|
||||
261 : (0,189:14,22);
|
||||
267 : (0,190:20,0);
|
||||
283 : (0,192:25,34);
|
||||
293 : (0,193:25,35);
|
||||
303 : (0,194:25,36);
|
||||
313 : (0,195:25,37);
|
||||
323 : (0,196:25,38);
|
||||
324 : (0,184:4,41);
|
||||
325 : (0,184:4,41);
|
||||
326 : (0,184:4,41);
|
||||
331 : (0,198:0,0);
|
||||
335 : (0,198:0,42);
|
||||
336 : (0,198:0,42);
|
||||
447 : (0,182:5,0);
|
||||
520 : (0,185:14,18);
|
||||
548 : (0,198:0,0);
|
||||
576 : (0,189:14,0);
|
||||
604 : (0,192:14,0);
|
||||
632 : (0,193:25,0);
|
||||
660 : (0,194:25,0);
|
||||
688 : (0,195:25,0);
|
||||
716 : (0,196:25,0);
|
||||
747 : (0,182:5,0);
|
||||
749 : (0,185:14,0);
|
||||
755 : (0,198:0,0);
|
||||
757 : (0,189:14,0);
|
||||
761 : (0,192:14,0);
|
||||
763 : (0,193:25,0);
|
||||
830 : (0,190:20,0);
|
||||
831 : (0,190:20,30);
|
||||
832 : (0,190:20,30);
|
||||
833 : (0,190:20,30);
|
||||
834 : (0,190:20,30);
|
||||
835 : (0,190:20,30);
|
||||
836 : (0,190:20,30);
|
||||
927 : (0,184:11,0);
|
||||
928 : (0,184:11,1);
|
||||
929 : (0,184:11,1);
|
||||
930 : (0,184:11,1);
|
||||
931 : (0,184:11,1);
|
||||
932 : (0,184:11,1);
|
||||
933 : (0,184:11,1);
|
||||
941 : (0,184:23,2);
|
||||
942 : (0,184:23,2);
|
||||
943 : (0,184:23,2);
|
||||
944 : (0,184:23,2);
|
||||
945 : (0,184:23,2);
|
||||
946 : (0,184:23,2);
|
||||
954 : (0,184:35,6);
|
||||
955 : (0,184:35,6);
|
||||
956 : (0,184:35,6);
|
||||
957 : (0,184:35,6);
|
||||
958 : (0,184:35,6);
|
||||
959 : (0,184:35,6);
|
||||
967 : (0,184:47,10);
|
||||
968 : (0,184:47,10);
|
||||
969 : (0,184:47,10);
|
||||
970 : (0,184:47,10);
|
||||
971 : (0,184:47,10);
|
||||
972 : (0,184:47,10);
|
||||
980 : (0,184:59,14);
|
||||
981 : (0,184:59,14);
|
||||
982 : (0,184:59,14);
|
||||
983 : (0,184:59,14);
|
||||
984 : (0,184:59,14);
|
||||
985 : (0,184:59,14);
|
||||
992 : (0,184:11,1);
|
||||
1000 : (0,184:23,2);
|
||||
1008 : (0,184:35,6);
|
||||
1016 : (0,184:47,10);
|
||||
1024 : (0,184:59,14);
|
||||
1051 : (0,184:59,14);
|
||||
1054 : (0,190:25,0);
|
||||
1055 : (0,190:25,27);
|
||||
1056 : (0,190:25,27);
|
||||
1057 : (0,190:25,27);
|
||||
1058 : (0,190:25,27);
|
||||
1059 : (0,190:25,27);
|
||||
1066 : (0,190:39,0);
|
||||
1067 : (0,190:39,33);
|
||||
1068 : (0,190:39,33);
|
||||
1069 : (0,190:39,33);
|
||||
1070 : (0,190:39,33);
|
||||
1071 : (0,190:39,33);
|
||||
1072 : (0,190:39,33);
|
||||
1078 : (0,190:39,0);
|
||||
1079 : (0,190:39,33);
|
||||
1080 : (0,190:39,33);
|
||||
1081 : (0,190:39,33);
|
||||
1082 : (0,190:39,33);
|
||||
1083 : (0,190:39,33);
|
||||
1090 : (0,192:34,34);
|
||||
1091 : (0,192:34,34);
|
||||
1092 : (0,192:34,34);
|
||||
1093 : (0,192:34,34);
|
||||
1094 : (0,192:34,34);
|
||||
1101 : (0,192:34,0);
|
||||
1102 : (0,192:34,34);
|
||||
1103 : (0,192:34,34);
|
||||
1104 : (0,192:34,34);
|
||||
1105 : (0,192:34,34);
|
||||
1106 : (0,192:34,34);
|
||||
1107 : (0,192:34,34);
|
||||
1114 : (0,192:29,34);
|
||||
1115 : (0,192:29,34);
|
||||
1116 : (0,192:29,34);
|
||||
1117 : (0,192:29,34);
|
||||
1118 : (0,192:29,34);
|
||||
1126 : (0,193:34,35);
|
||||
1127 : (0,193:34,35);
|
||||
1128 : (0,193:34,35);
|
||||
1129 : (0,193:34,35);
|
||||
1130 : (0,193:34,35);
|
||||
1131 : (0,193:34,35);
|
||||
1138 : (0,193:29,35);
|
||||
1139 : (0,193:29,35);
|
||||
1140 : (0,193:29,35);
|
||||
1141 : (0,193:29,35);
|
||||
1142 : (0,193:29,35);
|
||||
1150 : (0,194:34,36);
|
||||
1151 : (0,194:34,36);
|
||||
1152 : (0,194:34,36);
|
||||
1153 : (0,194:34,36);
|
||||
1154 : (0,194:34,36);
|
||||
1155 : (0,194:34,36);
|
||||
1162 : (0,194:29,36);
|
||||
1163 : (0,194:29,36);
|
||||
1164 : (0,194:29,36);
|
||||
1165 : (0,194:29,36);
|
||||
1166 : (0,194:29,36);
|
||||
1174 : (0,195:34,37);
|
||||
1175 : (0,195:34,37);
|
||||
1176 : (0,195:34,37);
|
||||
1177 : (0,195:34,37);
|
||||
1178 : (0,195:34,37);
|
||||
1179 : (0,195:34,37);
|
||||
1186 : (0,195:29,37);
|
||||
1187 : (0,195:29,37);
|
||||
1188 : (0,195:29,37);
|
||||
1189 : (0,195:29,37);
|
||||
1190 : (0,195:29,37);
|
||||
1198 : (0,196:34,38);
|
||||
1199 : (0,196:34,38);
|
||||
1200 : (0,196:34,38);
|
||||
1201 : (0,196:34,38);
|
||||
1202 : (0,196:34,38);
|
||||
1203 : (0,196:34,38);
|
||||
1210 : (0,196:29,38);
|
||||
1211 : (0,196:29,38);
|
||||
1212 : (0,196:29,38);
|
||||
1213 : (0,196:29,38);
|
||||
1214 : (0,196:29,38);
|
||||
1262 : (0,184:11,1);
|
||||
1263 : (0,184:23,2);
|
||||
1264 : (0,184:17,4);
|
||||
1265 : (0,184:35,6);
|
||||
1266 : (0,184:29,8);
|
||||
1267 : (0,184:47,10);
|
||||
1268 : (0,184:41,12);
|
||||
1292 : (0,184:17,1);
|
||||
1296 : (0,184:29,5);
|
||||
1300 : (0,184:41,9);
|
||||
1304 : (0,184:53,13);
|
||||
1308 : (0,184:4,17);
|
||||
|
||||
Reference in New Issue
Block a user