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Calc-Funktion weiter, unnötige Funktionen auskommentiert (kompiliert)

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This commit is contained in:
Patrick Hangl
2026-02-02 16:12:41 +01:00
parent fa787bec48
commit f6fa0ed021
85 changed files with 16931 additions and 12836 deletions
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301
simulation/Release/chesswork/main-9f2435.sfg
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Jan 28 15:15:00 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 15:52:57 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -14,9 +14,9 @@ F_main : user_defined, called {
frm : ( l=88 b=8 );
}
****
!! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
!! void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "initialize_signal" 'void initialize_signal(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
@@ -45,9 +45,9 @@ Ffscanf : user_defined, called, varargs {
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
!! void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
!! void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ : user_defined, called {
fnm : "calculate_output" 'void calculate_output(SingleSignalPath *, SingleSignalPath *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );
@@ -135,20 +135,19 @@ Ffclose : user_defined, called {
103 : fp1 typ=dmaddr_ bnd=m tref=__PFILE__
104 : fp2 typ=dmaddr_ bnd=m tref=__PFILE__
105 : fp3 typ=dmaddr_ bnd=m tref=__PFILE__
110 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m
110 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
112 : __ct_0 typ=int32_ val=0f bnd=m
115 : __ct_0 typ=uint40_ val=0f bnd=m
160 : __ct_2 typ=int32_ val=2f bnd=m
161 : __ct typ=int32_ bnd=m
163 : __ct typ=int32_ bnd=m
164 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m
165 : __ct typ=int64_ bnd=m
167 : __ct typ=int64_ bnd=m
168 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m
169 : __ct typ=int64_ bnd=m
170 : __ct_64 typ=int32_ val=64f bnd=m
171 : __ct typ=int32_ bnd=m
172 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
172 : _Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
174 : __link typ=dmaddr_ bnd=m
175 : fopen typ=dmaddr_ val=0r bnd=m
177 : __link typ=dmaddr_ bnd=m
@@ -175,7 +174,7 @@ Ffclose : user_defined, called {
225 : __tmp typ=int16_ bnd=m
241 : __tmp typ=dmaddr_ bnd=m
244 : __tmp typ=dmaddr_ bnd=m
245 : _Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=dmaddr_ val=0r bnd=m
245 : _Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ typ=dmaddr_ val=0r bnd=m
247 : __link typ=dmaddr_ bnd=m
257 : __fch__ZL11output_port typ=int16_ bnd=m
258 : __fch__ZL11output_port typ=int32_ bnd=m
@@ -224,7 +223,7 @@ Ffclose : user_defined, called {
457 : __trgt typ=int10_ val=0j bnd=m
]
F_main {
#368 off=0
#366 off=0
(__M_SDMB.6 var=8) st_def () <12>;
(__M_WDMA.9 var=11) st_def () <18>;
(__R_SP.24 var=26) st_def () <48>;
@@ -256,46 +255,45 @@ F_main {
(__rd___sp.87 var=58) rd_res_reg (__R_SP.24 __sp.32) <111>;
(__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.1692 __sp.32) <115>;
(__rd___sp.93 var=58) rd_res_reg (__R_SP.24 __sp.92) <117>;
(__ct_4604930618986332160.120 var=110) const () <144>;
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_4604930618986332160.120 __rt.1714 b0.33) <149>;
(__ct_4607182418800017408.120 var=110) const () <144>;
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_4607182418800017408.120 __rt.1714 b0.33) <149>;
(__ct_0.127 var=115) const () <150>;
(__M_LDMA.132 var=14 b0.133 var=35) store (__ct_0.127 __rt.1878 b0.126) <155>;
(__M_LDMA.139 var=14 b0.140 var=35) store (__ct_0.127 __rt.1900 b0.133) <161>;
(__M_LDMA.146 var=14 b0.147 var=35) store (__ct_0.127 __rt.1922 b0.140) <167>;
(__M_LDMA.153 var=14 b0.154 var=35) store (__ct_0.127 __rt.1944 b0.147) <173>;
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_4604930618986332160.120 __rt.1736 b1.34) <179>;
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_4607182418800017408.120 __rt.1736 b1.34) <179>;
(__M_LDMA.167 var=14 b1.168 var=36) store (__ct_0.127 __rt.1966 b1.161) <185>;
(__M_LDMA.174 var=14 b1.175 var=36) store (__ct_0.127 __rt.1988 b1.168) <191>;
(__M_LDMA.181 var=14 b1.182 var=36) store (__ct_0.127 __rt.2010 b1.175) <197>;
(__M_LDMA.188 var=14 b1.189 var=36) store (__ct_0.127 __rt.2032 b1.182) <203>;
(__ct_2.194 var=160) const () <208>;
(__ct_4606281698874543309.200 var=164) const () <214>;
(__ct_4576918229304087675.206 var=168) const () <220>;
(__ct_64.209 var=170) const () <223>;
(_Z4initP16SingleSignalPathS0_PdS1_iidddi.212 var=172) const () <226>;
(__link.214 var=174) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.212) <228>;
(__rt.1692 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_m88S0.2045) <1439>;
(__rt.1714 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_0t0.2047) <1467>;
(__rt.1736 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_40t0.2048) <1495>;
(__rt.1878 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_8t0.2059) <1679>;
(__rt.1900 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_16t0.2062) <1707>;
(__rt.1922 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_24t0.2065) <1735>;
(__rt.1944 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_32t0.2068) <1763>;
(__rt.1966 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_48t0.2071) <1791>;
(__rt.1988 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_56t0.2074) <1819>;
(__rt.2010 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_64t0.2077) <1847>;
(__rt.2032 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_72t0.2080) <1875>;
(__ct_m88S0.2045 var=398) const () <1935>;
(__ct_0t0.2047 var=400) const () <1939>;
(__ct_40t0.2048 var=401) const () <1941>;
(__ct_8t0.2059 var=412) const () <1963>;
(__ct_16t0.2062 var=415) const () <1969>;
(__ct_24t0.2065 var=418) const () <1975>;
(__ct_32t0.2068 var=421) const () <1981>;
(__ct_48t0.2071 var=424) const () <1987>;
(__ct_56t0.2074 var=427) const () <1993>;
(__ct_64t0.2077 var=430) const () <1999>;
(__ct_72t0.2080 var=433) const () <2005>;
(_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi.212 var=172) const () <226>;
(__link.214 var=174) dmaddr__call_dmaddr_ (_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi.212) <228>;
(__rt.1692 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_m88S0.2045) <1436>;
(__rt.1714 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_0t0.2047) <1464>;
(__rt.1736 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_40t0.2048) <1492>;
(__rt.1878 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_8t0.2059) <1676>;
(__rt.1900 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_16t0.2062) <1704>;
(__rt.1922 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_24t0.2065) <1732>;
(__rt.1944 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_32t0.2068) <1760>;
(__rt.1966 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_48t0.2071) <1788>;
(__rt.1988 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_56t0.2074) <1816>;
(__rt.2010 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_64t0.2077) <1844>;
(__rt.2032 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_72t0.2080) <1872>;
(__ct_m88S0.2045 var=398) const () <1931>;
(__ct_0t0.2047 var=400) const () <1935>;
(__ct_40t0.2048 var=401) const () <1937>;
(__ct_8t0.2059 var=412) const () <1959>;
(__ct_16t0.2062 var=415) const () <1965>;
(__ct_24t0.2065 var=418) const () <1971>;
(__ct_32t0.2068 var=421) const () <1977>;
(__ct_48t0.2071 var=424) const () <1983>;
(__ct_56t0.2074 var=427) const () <1989>;
(__ct_64t0.2077 var=430) const () <1995>;
(__ct_72t0.2080 var=433) const () <2001>;
call {
(__ptr_c_sensor_signal_t.190 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <204>;
(__ptr_acc_sensor_signal_t.191 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <205>;
@@ -303,12 +301,12 @@ F_main {
(__ptr_b1.193 var=91 stl=A off=3) assign (__rt.1736) <207>;
(__ct.196 var=161 stl=RA off=0) assign (__ct_2.194) <210>;
(__ct.199 var=163 stl=RA off=1) assign (__ct_2.194) <213>;
(__ct.202 var=165 stl=AX off=0) assign (__ct_4606281698874543309.200) <216>;
(__ct.205 var=167 stl=AX off=1) assign (__ct_4606281698874543309.200) <219>;
(__ct.202 var=165 stl=AX off=0) assign (__ct_4607182418800017408.120) <216>;
(__ct.205 var=167 stl=AX off=1) assign (__ct_4607182418800017408.120) <219>;
(__ct.208 var=169 stl=BX off=0) assign (__ct_4576918229304087675.206) <222>;
(__ct.211 var=171 stl=RB off=0) assign (__ct_64.209) <225>;
(__link.215 var=174 stl=LR off=0) assign (__link.214) <229>;
(_ZL10input_port.216 var=48 _ZL11output_port.217 var=50 _ZL17c_sensor_signal_t.218 var=37 _ZL19acc_sensor_signal_t.219 var=39 __extDM.220 var=32 __extDM_SingleSignalPath.221 var=38 __extDM_int16_.222 var=49 __extDM_int32_.223 var=57 __extDM_int64_.224 var=54 __extDM_int8_.225 var=55 __extDM_void.226 var=52 __extPM.227 var=33 __extPM_FILE.228 var=56 __extPM_void.229 var=53 b0.230 var=35 b1.231 var=36 __vola.232 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.215 __ptr_c_sensor_signal_t.190 __ptr_acc_sensor_signal_t.191 __ptr_b0.192 __ptr_b1.193 __ct.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 _ZL10input_port.46 _ZL11output_port.48 _ZL17c_sensor_signal_t.35 _ZL19acc_sensor_signal_t.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.55 __extDM_int64_.52 __extDM_int8_.53 __extDM_void.50 __extPM.31 __extPM_FILE.54 __extPM_void.51 b0.154 b1.189 __vola.27) <230>;
(_ZL10input_port.216 var=48 _ZL11output_port.217 var=50 _ZL17c_sensor_signal_t.218 var=37 _ZL19acc_sensor_signal_t.219 var=39 __extDM.220 var=32 __extDM_SingleSignalPath.221 var=38 __extDM_int16_.222 var=49 __extDM_int32_.223 var=57 __extDM_int64_.224 var=54 __extDM_int8_.225 var=55 __extDM_void.226 var=52 __extPM.227 var=33 __extPM_FILE.228 var=56 __extPM_void.229 var=53 b0.230 var=35 b1.231 var=36 __vola.232 var=29) F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi (__link.215 __ptr_c_sensor_signal_t.190 __ptr_acc_sensor_signal_t.191 __ptr_b0.192 __ptr_b1.193 __ct.196 __ct.199 __ct.202 __ct.205 __ct.208 __ct.211 _ZL10input_port.46 _ZL11output_port.48 _ZL17c_sensor_signal_t.35 _ZL19acc_sensor_signal_t.37 __extDM.30 __extDM_SingleSignalPath.36 __extDM_int16_.47 __extDM_int32_.55 __extDM_int64_.52 __extDM_int8_.53 __extDM_void.50 __extPM.31 __extPM_FILE.54 __extPM_void.51 b0.154 b1.189 __vola.27) <230>;
} #4 off=1
#5 off=2
(__ptr___str45bf45e5.61 var=64) const () <85>;
@@ -352,19 +350,19 @@ F_main {
(__tmp.319 var=190 stl=RA off=0 _ZL10input_port.322 var=48 _ZL11output_port.323 var=50 _ZL17c_sensor_signal_t.324 var=37 _ZL19acc_sensor_signal_t.325 var=39 __extDM.326 var=32 __extDM_SingleSignalPath.327 var=38 __extDM_int16_.328 var=49 __extDM_int32_.329 var=57 __extDM_int64_.330 var=54 __extDM_int8_.331 var=55 __extDM_void.332 var=52 __extPM.333 var=33 __extPM_FILE.334 var=56 __extPM_void.335 var=53 b0.336 var=35 b1.337 var=36 __vola.338 var=29) Ffeof (__link.318 fp1.314 _ZL10input_port.297 _ZL11output_port.298 _ZL17c_sensor_signal_t.299 _ZL19acc_sensor_signal_t.300 __extDM.301 __extDM_SingleSignalPath.302 __extDM_int16_.303 __extDM_int32_.304 __extDM_int64_.305 __extDM_int8_.306 __extDM_void.307 __extPM.308 __extPM_FILE.309 __extPM_void.310 b0.311 b1.312 __vola.313) <266>;
(__tmp.320 var=190) deassign (__tmp.319) <267>;
} #12 off=9
#717 off=10
#715 off=10
(__ct_0.122 var=112) const () <146>;
(__tmp.2095 var=439) uint3__cmp_int72__int72_ (__tmp.320 __ct_0.122) <2030>;
(__tmp.2105 var=382) bool_nequal_uint3_ (__tmp.2095) <2088>;
(__trgt.2114 var=453) const () <2183>;
() void_jump_bool_int10_ (__tmp.2105 __trgt.2114) <2184>;
(__either.2115 var=452) undefined () <2185>;
(__tmp.2095 var=439) uint3__cmp_int72__int72_ (__tmp.320 __ct_0.122) <2026>;
(__tmp.2105 var=382) bool_nequal_uint3_ (__tmp.2095) <2083>;
(__trgt.2114 var=453) const () <2176>;
() void_jump_bool_int10_ (__tmp.2105 __trgt.2114) <2177>;
(__either.2115 var=452) undefined () <2178>;
if {
{
() if_expr (__either.2115) <325>;
} #15
{
(__true.2121 var=450) const () <2193>;
(__true.2121 var=450) const () <2186>;
} #16
{
#18 off=11
@@ -375,12 +373,12 @@ F_main {
(__tmp.402 var=199 stl=RA off=0 _ZL10input_port.405 var=48 _ZL11output_port.406 var=50 _ZL17c_sensor_signal_t.407 var=37 _ZL19acc_sensor_signal_t.408 var=39 __extDM.409 var=32 __extDM_SingleSignalPath.410 var=38 __extDM_int16_.411 var=49 __extDM_int32_.412 var=57 __extDM_int64_.413 var=54 __extDM_int8_.414 var=55 __extDM_void.415 var=52 __extPM.416 var=33 __extPM_FILE.417 var=56 __extPM_void.418 var=53 b0.419 var=35 b1.420 var=36 __vola.421 var=29) Ffeof (__link.401 fp2.397 _ZL10input_port.322 _ZL11output_port.323 _ZL17c_sensor_signal_t.324 _ZL19acc_sensor_signal_t.325 __extDM.326 __extDM_SingleSignalPath.327 __extDM_int16_.328 __extDM_int32_.329 __extDM_int64_.330 __extDM_int8_.331 __extDM_void.332 __extPM.333 __extPM_FILE.334 __extPM_void.335 b0.336 b1.337 __vola.338) <333>;
(__tmp.403 var=199) deassign (__tmp.402) <334>;
} #19 off=12
#711 off=13
(__tmp.2085 var=439) uint3__cmp_int72__int72_ (__tmp.403 __ct_0.122) <2014>;
(__tmp.2110 var=202) bool_nequal_uint3_ (__tmp.2085) <2136>;
(__trgt.2122 var=456) const () <2194>;
() void_jump_bool_int10_ (__tmp.2110 __trgt.2122) <2195>;
(__either.2123 var=452) undefined () <2196>;
#709 off=13
(__tmp.2085 var=439) uint3__cmp_int72__int72_ (__tmp.403 __ct_0.122) <2010>;
(__tmp.2110 var=202) bool_nequal_uint3_ (__tmp.2085) <2130>;
(__trgt.2122 var=456) const () <2187>;
() void_jump_bool_int10_ (__tmp.2110 __trgt.2122) <2188>;
(__either.2123 var=452) undefined () <2189>;
} #17
{
(__vola.426 var=29) merge (__vola.338 __vola.421) <340>;
@@ -400,35 +398,35 @@ F_main {
(__extDM_int8_.440 var=55) merge (__extDM_int8_.331 __extDM_int8_.414) <354>;
(__extPM_FILE.441 var=56) merge (__extPM_FILE.334 __extPM_FILE.417) <355>;
(__extDM_int32_.442 var=57) merge (__extDM_int32_.329 __extDM_int32_.412) <356>;
(__tmp.2111 var=203) merge (__true.2121 __either.2123) <2137>;
(__tmp.2111 var=203) merge (__true.2121 __either.2123) <2131>;
} #21
} #14
if {
{
() if_expr (__tmp.2111) <411>;
() chess_frequent_else () <412>;
() chess_rear_then () <2197>;
() chess_rear_then () <2190>;
} #24
{
(__trgt.2124 var=457) const () <2198>;
() void_jump_int10_ (__trgt.2124) <2199>;
(__trgt.2124 var=457) const () <2191>;
() void_jump_int10_ (__trgt.2124) <2192>;
} #72 off=30
{
#760 off=14
#758 off=14
(__ptr___str41232700.71 var=74) const () <95>;
(__ct_8388608.73 var=76) const () <97>;
(__ct_8388624.76 var=78) const () <100>;
(__ptr___str2eb09b76.79 var=80) const () <103>;
(fscanf.665 var=210) const () <583>;
(_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884 var=245) const () <709>;
(_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884 var=245) const () <709>;
(fprintf.1030 var=259) const () <837>;
(__rt.1758 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_80t0.2051) <1523>;
(__rt.1780 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_84t0.2054) <1551>;
(__ct_80t0.2051 var=404) const () <1947>;
(__ct_84t0.2054 var=407) const () <1953>;
(__ct_2.2057 var=410) const () <1959>;
(__trgt.2116 var=454) const () <2186>;
(__trgt.2119 var=455) const () <2190>;
(__rt.1758 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_80t0.2051) <1520>;
(__rt.1780 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_84t0.2054) <1548>;
(__ct_80t0.2051 var=404) const () <1943>;
(__ct_84t0.2054 var=407) const () <1949>;
(__ct_2.2057 var=410) const () <1955>;
(__trgt.2116 var=454) const () <2179>;
(__trgt.2119 var=455) const () <2183>;
do {
{
(__vola.497 var=29) entry (__vola.1325 __vola.426) <413>;
@@ -450,7 +448,7 @@ F_main {
(__extDM_int8_.523 var=55) entry (__extDM_int8_.1377 __extDM_int8_.440) <439>;
(__extPM_FILE.524 var=56) entry (__extPM_FILE.1379 __extPM_FILE.441) <440>;
(__extDM_int32_.525 var=57) entry (__extDM_int32_.1381 __extDM_int32_.442) <441>;
(__shv___ptr_input_port.1646 var=333) entry (__shv___ptr_input_port.1644 __ct_8388608.73) <1338>;
(__shv___ptr_input_port.1646 var=333) entry (__shv___ptr_input_port.1644 __ct_8388608.73) <1336>;
} #27
{
#36 off=15
@@ -471,16 +469,16 @@ F_main {
(__link.696 var=216 stl=LR off=0) assign (__link.695) <596>;
(__tmp.697 var=217 stl=RA off=0 _ZL10input_port.700 var=48 _ZL11output_port.701 var=50 _ZL17c_sensor_signal_t.702 var=37 _ZL19acc_sensor_signal_t.703 var=39 __extDM.704 var=32 __extDM_SingleSignalPath.705 var=38 __extDM_int16_.706 var=49 __extDM_int32_.707 var=57 __extDM_int64_.708 var=54 __extDM_int8_.709 var=55 __extDM_void.710 var=52 __extPM.711 var=33 __extPM_FILE.712 var=56 __extPM_void.713 var=53 b0.714 var=35 b1.715 var=36 d0.716 var=46 d1.717 var=47 __vola.718 var=29) VA1Ffscanf (__link.696 fp2.690 __ptr___str41232700.691 __ptr_d1.692 _ZL10input_port.672 _ZL11output_port.673 _ZL17c_sensor_signal_t.674 _ZL19acc_sensor_signal_t.675 __extDM.676 __extDM_SingleSignalPath.677 __extDM_int16_.678 __extDM_int32_.679 __extDM_int64_.680 __extDM_int8_.681 __extDM_void.682 __extPM.683 __extPM_FILE.684 __extPM_void.685 b0.686 b1.687 d0.688 d1.515 __vola.689) <597>;
} #39 off=18
#490 off=19
#488 off=19
(__fch_d0.719 var=218) load (__M_WDMA.9 __rt.1758 d0.716) <600>;
(__tmp.720 var=219) __sshort___sshort___sint (__fch_d0.719) <601>;
(__M_SDMB.725 var=8 _ZL10input_port.726 var=48 __vola.727 var=29) store (__tmp.720 __shv___ptr_input_port.1646 _ZL10input_port.700 __vola.718) <606>;
(__fch_d1.728 var=224) load (__M_WDMA.9 __rt.1780 d1.717) <607>;
(__tmp.729 var=225) __sshort___sshort___sint (__fch_d1.728) <608>;
(__M_SDMB.737 var=8 _ZL10input_port.738 var=48 __vola.739 var=29) store (__tmp.729 __rt.1834 _ZL10input_port.726 __vola.727) <616>;
(__link.886 var=247) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884) <711>;
(__rt.1834 var=357) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1646 __ct_2.2057) <1623>;
(__rt.1856 var=357) __Pvoid__mi___Pvoid_int18_ (__rt.1834 __ct_2.2057) <1651>;
(__link.886 var=247) dmaddr__call_dmaddr_ (_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_.884) <711>;
(__rt.1834 var=357) __Pvoid__pl___Pvoid_int18_ (__shv___ptr_input_port.1646 __ct_2.2057) <1620>;
(__rt.1856 var=357) __Pvoid__mi___Pvoid_int18_ (__rt.1834 __ct_2.2057) <1648>;
call {
(__ptr_c_sensor_signal_t.873 var=59 stl=A off=0) assign (__ptr_c_sensor_signal_t.57) <698>;
(__ptr_acc_sensor_signal_t.874 var=61 stl=A off=1) assign (__ptr_acc_sensor_signal_t.59) <699>;
@@ -488,7 +486,7 @@ F_main {
(__tmp.882 var=244 stl=A off=5) assign (__rt.1834) <707>;
(__ptr_output_port.883 var=77 stl=__spill_WDMA off=0) assign (__ct_8388624.76) <708>;
(__link.887 var=247 stl=LR off=0) assign (__link.886) <712>;
(_ZL10input_port.888 var=48 _ZL11output_port.889 var=50 _ZL17c_sensor_signal_t.890 var=37 _ZL19acc_sensor_signal_t.891 var=39 __extDM.892 var=32 __extDM_SingleSignalPath.893 var=38 __extDM_int16_.894 var=49 __extDM_int32_.895 var=57 __extDM_int64_.896 var=54 __extDM_int8_.897 var=55 __extDM_void.898 var=52 __extPM.899 var=33 __extPM_FILE.900 var=56 __extPM_void.901 var=53 b0.902 var=35 b1.903 var=36 d0.904 var=46 d1.905 var=47 __vola.906 var=29) F_Z4calcP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ (__link.887 __ptr_c_sensor_signal_t.873 __ptr_acc_sensor_signal_t.874 __tmp.878 __tmp.882 __ptr_output_port.883 _ZL10input_port.738 _ZL11output_port.701 _ZL17c_sensor_signal_t.702 _ZL19acc_sensor_signal_t.703 __extDM.704 __extDM_SingleSignalPath.705 __extDM_int16_.706 __extDM_int32_.707 __extDM_int64_.708 __extDM_int8_.709 __extDM_void.710 __extPM.711 __extPM_FILE.712 __extPM_void.713 b0.714 b1.715 d0.716 d1.717 __vola.739) <713>;
(_ZL10input_port.888 var=48 _ZL11output_port.889 var=50 _ZL17c_sensor_signal_t.890 var=37 _ZL19acc_sensor_signal_t.891 var=39 __extDM.892 var=32 __extDM_SingleSignalPath.893 var=38 __extDM_int16_.894 var=49 __extDM_int32_.895 var=57 __extDM_int64_.896 var=54 __extDM_int8_.897 var=55 __extDM_void.898 var=52 __extPM.899 var=33 __extPM_FILE.900 var=56 __extPM_void.901 var=53 b0.902 var=35 b1.903 var=36 d0.904 var=46 d1.905 var=47 __vola.906 var=29) F_Z16calculate_outputP16SingleSignalPathS0_PU17chess_storage_DMBVsS2_S2_ (__link.887 __ptr_c_sensor_signal_t.873 __ptr_acc_sensor_signal_t.874 __tmp.878 __tmp.882 __ptr_output_port.883 _ZL10input_port.738 _ZL11output_port.701 _ZL17c_sensor_signal_t.702 _ZL19acc_sensor_signal_t.703 __extDM.704 __extDM_SingleSignalPath.705 __extDM_int16_.706 __extDM_int32_.707 __extDM_int64_.708 __extDM_int8_.709 __extDM_void.710 __extPM.711 __extPM_FILE.712 __extPM_void.713 b0.714 b1.715 d0.716 d1.717 __vola.739) <713>;
} #45 off=20
#53 off=21
(__fch__ZL11output_port.1025 var=257 _ZL11output_port.1026 var=50 __vola.1027 var=29) load (__M_SDMB.6 __ct_8388624.76 _ZL11output_port.889 __vola.906) <834>;
@@ -508,17 +506,17 @@ F_main {
(__tmp.1194 var=272 stl=RA off=0 _ZL10input_port.1197 var=48 _ZL11output_port.1198 var=50 _ZL17c_sensor_signal_t.1199 var=37 _ZL19acc_sensor_signal_t.1200 var=39 __extDM.1201 var=32 __extDM_SingleSignalPath.1202 var=38 __extDM_int16_.1203 var=49 __extDM_int32_.1204 var=57 __extDM_int64_.1205 var=54 __extDM_int8_.1206 var=55 __extDM_void.1207 var=52 __extPM.1208 var=33 __extPM_FILE.1209 var=56 __extPM_void.1210 var=53 b0.1211 var=35 b1.1212 var=36 d0.1213 var=46 d1.1214 var=47 __vola.1215 var=29) Ffeof (__link.1193 fp1.1189 _ZL10input_port.1037 _ZL11output_port.1038 _ZL17c_sensor_signal_t.1039 _ZL19acc_sensor_signal_t.1040 __extDM.1041 __extDM_SingleSignalPath.1042 __extDM_int16_.1043 __extDM_int32_.1044 __extDM_int64_.1045 __extDM_int8_.1046 __extDM_void.1047 __extPM.1048 __extPM_FILE.1049 __extPM_void.1050 b0.1051 b1.1052 d0.1053 d1.1054 __vola.1055) <930>;
(__tmp.1195 var=272) deassign (__tmp.1194) <931>;
} #60 off=24
#722 off=25
(__tmp.2100 var=439) uint3__cmp_int72__int72_ (__tmp.1195 __ct_0.122) <2038>;
(__tmp.2106 var=382) bool_nequal_uint3_ (__tmp.2100) <2089>;
() void_jump_bool_int10_ (__tmp.2106 __trgt.2116) <2187>;
(__either.2117 var=452) undefined () <2188>;
#720 off=25
(__tmp.2100 var=439) uint3__cmp_int72__int72_ (__tmp.1195 __ct_0.122) <2034>;
(__tmp.2106 var=382) bool_nequal_uint3_ (__tmp.2100) <2084>;
() void_jump_bool_int10_ (__tmp.2106 __trgt.2116) <2180>;
(__either.2117 var=452) undefined () <2181>;
if {
{
() if_expr (__either.2117) <989>;
} #63
{
(__false.2118 var=451) const () <2189>;
(__false.2118 var=451) const () <2182>;
} #64
{
#66 off=26
@@ -529,11 +527,11 @@ F_main {
(__tmp.1279 var=281 stl=RA off=0 _ZL10input_port.1282 var=48 _ZL11output_port.1283 var=50 _ZL17c_sensor_signal_t.1284 var=37 _ZL19acc_sensor_signal_t.1285 var=39 __extDM.1286 var=32 __extDM_SingleSignalPath.1287 var=38 __extDM_int16_.1288 var=49 __extDM_int32_.1289 var=57 __extDM_int64_.1290 var=54 __extDM_int8_.1291 var=55 __extDM_void.1292 var=52 __extPM.1293 var=33 __extPM_FILE.1294 var=56 __extPM_void.1295 var=53 b0.1296 var=35 b1.1297 var=36 d0.1298 var=46 d1.1299 var=47 __vola.1300 var=29) Ffeof (__link.1278 fp2.1274 _ZL10input_port.1197 _ZL11output_port.1198 _ZL17c_sensor_signal_t.1199 _ZL19acc_sensor_signal_t.1200 __extDM.1201 __extDM_SingleSignalPath.1202 __extDM_int16_.1203 __extDM_int32_.1204 __extDM_int64_.1205 __extDM_int8_.1206 __extDM_void.1207 __extPM.1208 __extPM_FILE.1209 __extPM_void.1210 b0.1211 b1.1212 d0.1213 d1.1214 __vola.1215) <997>;
(__tmp.1280 var=281) deassign (__tmp.1279) <998>;
} #67 off=27
#714 off=28
(__tmp.2090 var=439) uint3__cmp_int72__int72_ (__tmp.1280 __ct_0.122) <2022>;
(__tmp.2091 var=284) bool_equal_uint3_ (__tmp.2090) <2023>;
() void_jump_bool_int10_ (__tmp.2091 __trgt.2119) <2191>;
(__either.2120 var=452) undefined () <2192>;
#712 off=28
(__tmp.2090 var=439) uint3__cmp_int72__int72_ (__tmp.1280 __ct_0.122) <2018>;
(__tmp.2091 var=284) bool_equal_uint3_ (__tmp.2090) <2019>;
() void_jump_bool_int10_ (__tmp.2091 __trgt.2119) <2184>;
(__either.2120 var=452) undefined () <2185>;
} #65
{
(__vola.1305 var=29) merge (__vola.1215 __vola.1300) <1004>;
@@ -555,7 +553,7 @@ F_main {
(__extDM_int8_.1321 var=55) merge (__extDM_int8_.1206 __extDM_int8_.1291) <1020>;
(__extPM_FILE.1322 var=56) merge (__extPM_FILE.1209 __extPM_FILE.1294) <1021>;
(__extDM_int32_.1323 var=57) merge (__extDM_int32_.1204 __extDM_int32_.1289) <1022>;
(__tmp.1604 var=285) merge (__false.2118 __either.2120) <1299>;
(__tmp.1604 var=285) merge (__false.2118 __either.2120) <1297>;
} #69
} #62
} #28
@@ -580,7 +578,7 @@ F_main {
(__extDM_int8_.1377 var=55 __extDM_int8_.1378 var=55) exit (__extDM_int8_.1321) <1051>;
(__extPM_FILE.1379 var=56 __extPM_FILE.1380 var=56) exit (__extPM_FILE.1322) <1052>;
(__extDM_int32_.1381 var=57 __extDM_int32_.1382 var=57) exit (__extDM_int32_.1323) <1053>;
(__shv___ptr_input_port.1644 var=333 __shv___ptr_input_port.1645 var=333) exit (__rt.1856) <1337>;
(__shv___ptr_input_port.1644 var=333 __shv___ptr_input_port.1645 var=333) exit (__rt.1856) <1335>;
} #71
} #26 rng=[1,65535]
} #25
@@ -650,8 +648,8 @@ F_main {
() sink (__extPM_FILE.1528) <1158>;
() sink (__extDM_int32_.1523) <1159>;
() sink (__ct_0.81) <1160>;
(__rt.1812 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_88s0.2046) <1595>;
(__ct_88s0.2046 var=399) const () <1937>;
(__rt.1812 var=357) __Pvoid__pl___Pvoid_int18_ (__rd___sp.93 __ct_88s0.2046) <1592>;
(__ct_88s0.2046 var=399) const () <1933>;
} #0
0 : 'main.c';
----------
@@ -696,12 +694,12 @@ F_main {
78 : (0,70:11,64);
79 : (0,70:4,64);
82 : (0,71:0,65);
368 : (0,37:4,14);
490 : (0,62:8,39);
711 : (0,55:4,21);
714 : (0,55:23,55);
717 : (0,55:4,19);
722 : (0,55:23,53);
366 : (0,37:4,14);
488 : (0,62:8,39);
709 : (0,55:4,21);
712 : (0,55:23,55);
715 : (0,55:4,19);
720 : (0,55:23,53);
----------
85 : (0,49:22,0);
87 : (0,49:71,0);
@@ -714,16 +712,16 @@ F_main {
144 : (0,31:18,0);
146 : (0,31:18,0);
149 : (0,31:18,1);
150 : (0,31:24,0);
155 : (0,31:24,2);
161 : (0,31:28,3);
167 : (0,31:32,4);
173 : (0,31:36,5);
150 : (0,31:22,0);
155 : (0,31:22,2);
161 : (0,31:26,3);
167 : (0,31:30,4);
173 : (0,31:34,5);
179 : (0,32:18,7);
185 : (0,32:24,8);
191 : (0,32:28,9);
197 : (0,32:32,10);
203 : (0,32:36,11);
185 : (0,32:22,8);
191 : (0,32:26,9);
197 : (0,32:30,10);
203 : (0,32:34,11);
204 : (0,38:8,0);
205 : (0,38:28,0);
206 : (0,39:8,0);
@@ -731,9 +729,8 @@ F_main {
208 : (0,41:8,0);
210 : (0,41:8,0);
213 : (0,42:8,0);
214 : (0,43:8,0);
216 : (0,43:8,0);
219 : (0,44:8,0);
216 : (0,38:8,0);
219 : (0,38:8,0);
220 : (0,45:8,0);
222 : (0,45:8,0);
223 : (0,46:8,0);
@@ -917,48 +914,48 @@ F_main {
1131 : (0,71:0,65);
1132 : (0,71:0,65);
1133 : (0,71:0,0);
1299 : (0,55:23,56);
1439 : (0,28:4,0);
1467 : (0,31:11,0);
1495 : (0,32:11,0);
1523 : (0,53:8,0);
1551 : (0,53:12,0);
1595 : (0,71:0,0);
1623 : (0,63:81,0);
1679 : (0,31:24,0);
1707 : (0,31:28,0);
1735 : (0,31:32,0);
1763 : (0,31:36,0);
1791 : (0,32:24,0);
1819 : (0,32:28,0);
1847 : (0,32:32,0);
1875 : (0,32:36,0);
1935 : (0,28:4,0);
1937 : (0,28:4,0);
1939 : (0,31:11,0);
1941 : (0,32:11,0);
1947 : (0,53:8,0);
1953 : (0,53:12,0);
1959 : (0,63:81,0);
1963 : (0,31:24,0);
1969 : (0,31:28,0);
1975 : (0,31:32,0);
1981 : (0,31:36,0);
1987 : (0,32:24,0);
1993 : (0,32:28,0);
1999 : (0,32:32,0);
2005 : (0,32:36,0);
2014 : (0,55:4,21);
2022 : (0,55:23,55);
2023 : (0,55:23,55);
2030 : (0,55:4,19);
2038 : (0,55:23,53);
2088 : (0,55:4,19);
2089 : (0,55:23,53);
2136 : (0,55:4,21);
2137 : (0,55:4,22);
2184 : (0,55:4,19);
2187 : (0,55:23,53);
2191 : (0,55:4,57);
2195 : (0,55:4,23);
1297 : (0,55:23,56);
1436 : (0,28:4,0);
1464 : (0,31:11,0);
1492 : (0,32:11,0);
1520 : (0,53:8,0);
1548 : (0,53:12,0);
1592 : (0,71:0,0);
1620 : (0,63:81,0);
1676 : (0,31:22,0);
1704 : (0,31:26,0);
1732 : (0,31:30,0);
1760 : (0,31:34,0);
1788 : (0,32:22,0);
1816 : (0,32:26,0);
1844 : (0,32:30,0);
1872 : (0,32:34,0);
1931 : (0,28:4,0);
1933 : (0,28:4,0);
1935 : (0,31:11,0);
1937 : (0,32:11,0);
1943 : (0,53:8,0);
1949 : (0,53:12,0);
1955 : (0,63:81,0);
1959 : (0,31:22,0);
1965 : (0,31:26,0);
1971 : (0,31:30,0);
1977 : (0,31:34,0);
1983 : (0,32:22,0);
1989 : (0,32:26,0);
1995 : (0,32:30,0);
2001 : (0,32:34,0);
2010 : (0,55:4,21);
2018 : (0,55:23,55);
2019 : (0,55:23,55);
2026 : (0,55:4,19);
2034 : (0,55:23,53);
2083 : (0,55:4,19);
2084 : (0,55:23,53);
2130 : (0,55:4,21);
2131 : (0,55:4,22);
2177 : (0,55:4,19);
2180 : (0,55:23,53);
2184 : (0,55:4,57);
2188 : (0,55:4,23);