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Calc-Funktion kommentiert - kompiliert

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This commit is contained in:
Patrick Hangl
2026-01-27 11:17:03 +01:00
parent 5e701bd41d
commit 9b09cb21fa
140 changed files with 2420830 additions and 12680 deletions
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9
testcode/Release/chesswork/main-29daee.# Normal file
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466ba9a29dd6732e5048de41303e492793f3e524
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
ff952af49aad4daf3a74d0cfe5bef6d8b03d5219
da39a3ee5e6b4b0d3255bfef95601890afd80709
505a4156ed69046b2107b4419f21b75ff788e214
42
0
0

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testcode/Release/chesswork/main-29daee.o Normal file
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testcode/Release/chesswork/main-29daee.sfg Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
/***
!! int max_man(int, int)
F_Z7max_manii : user_defined, called {
fnm : "max_man" 'int max_man(int, int)';
arg : ( dmaddr_:i int32_:r int32_:i int32_:i );
loc : ( LR[0] RA[0] RA[1] RB[0] );
vac : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : _Z7max_manii typ=uint20_ bnd=e stl=PM tref=__sint_____sint___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : __rd___sp typ=dmaddr_ bnd=m
36 : __ct_0 typ=uint1_ val=0f bnd=m
37 : __la typ=dmaddr_ bnd=p tref=dmaddr___
39 : a typ=int32_ bnd=p tref=__sint__
40 : b typ=int32_ bnd=p tref=__sint__
45 : __tmp typ=int32_ bnd=m
60 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
81 : __ct_0S0 typ=int18_ val=0S0 bnd=m
82 : __ct_0s0 typ=int18_ val=0s0 bnd=m
]
F_Z7max_manii {
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__ct_0.34 var=36) const () <58>;
(__la.36 var=37 stl=LR off=0) inp () <60>;
(__la.37 var=37) deassign (__la.36) <61>;
(a.40 var=39 stl=RA off=1) inp () <64>;
(a.41 var=39) deassign (a.40) <65>;
(b.43 var=40 stl=RB off=0) inp () <67>;
(b.44 var=40) deassign (b.43) <68>;
(__rd___sp.46 var=35) rd_res_reg (__R_SP.24 __sp.32) <70>;
(__R_SP.50 var=26 __sp.51 var=34) wr_res_reg (__rt.104 __sp.32) <74>;
(__rd___sp.64 var=35) rd_res_reg (__R_SP.24 __sp.51) <89>;
(__R_SP.68 var=26 __sp.69 var=34) wr_res_reg (__rt.126 __sp.51) <93>;
() void_ret_dmaddr_ (__la.37) <94>;
(__tmp.70 var=45 stl=RA off=0) assign (__tmp.89) <95>;
() out (__tmp.70) <96>;
() sink (__sp.69) <102>;
() sink (__ct_0.34) <103>;
(__tmp.89 var=45) __sint_max___sint___sint (a.41 b.44) <133>;
(__rt.104 var=60) __Pvoid__pl___Pvoid_int18_ (__rd___sp.46 __ct_0S0.139) <158>;
(__rt.126 var=60) __Pvoid__pl___Pvoid_int18_ (__rd___sp.64 __ct_0s0.140) <186>;
(__ct_0S0.139 var=81) const () <209>;
(__ct_0s0.140 var=82) const () <211>;
} #10 off=0 nxt=-2
0 : 'main.c';
----------
10 : (0,42:4,5);
----------
70 : (0,41:4,0);
74 : (0,41:4,0);
89 : (0,42:4,0);
93 : (0,42:4,5);
94 : (0,42:4,5);
95 : (0,42:19,0);
133 : (0,42:19,4);
158 : (0,41:4,0);
186 : (0,42:4,0);
209 : (0,41:4,0);
211 : (0,42:4,0);

8
testcode/Release/chesswork/main-520f39.# Normal file
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466ba9a29dd6732e5048de41303e492793f3e524
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
e32147d9fa09f1a752037c468afacdc816731c60
da39a3ee5e6b4b0d3255bfef95601890afd80709
0a44fb3f94f4fc66f57821f8d42e54fbcdcb520e
27
0

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testcode/Release/chesswork/main-520f39.o Normal file
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195
testcode/Release/chesswork/main-520f39.sfg Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Tue Jan 20 12:04:50 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
/***
!! volatile int *cyclic_add_man(volatile int *, int, volatile int *, int)
F_Z14cyclic_add_manPViiS0_i : user_defined, called {
fnm : "cyclic_add_man" 'volatile int *cyclic_add_man(volatile int *, int, volatile int *, int)';
arg : ( dmaddr_:i dmaddr_:r dmaddr_:i int32_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] A[1] RA[0] A[2] RA[1] );
vac : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : _Z14cyclic_add_manPViiS0_i typ=uint20_ bnd=e stl=PM tref=__P__sint_____P__sint___sint___P__sint___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __rd___sp typ=dmaddr_ bnd=m
37 : __ct_0 typ=uint1_ val=0f bnd=m
38 : __la typ=dmaddr_ bnd=p tref=dmaddr___
40 : ptr typ=dmaddr_ bnd=p tref=__P__sint__
41 : i_pp typ=int32_ bnd=p tref=__sint__
42 : ptr_start typ=dmaddr_ bnd=p tref=__P__sint__
43 : buffer_len typ=int32_ bnd=p tref=__sint__
47 : p_ptr typ=dmaddr_ bnd=m tref=__P__sint__
50 : __ct_0 typ=int32_ val=0f bnd=m
52 : __tmp typ=int32_ bnd=m
53 : __tmp typ=bool bnd=m
78 : __cv typ=uint16_ bnd=m
83 : __ct_2 typ=int32_ val=2f bnd=m
86 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
109 : __tmp typ=bool bnd=m
114 : __ct_0S0 typ=int18_ val=0S0 bnd=m
115 : __ct_4 typ=int18_ val=4f bnd=m
118 : __ct_0s0 typ=int18_ val=0s0 bnd=m
122 : __tmp typ=uint3_ bnd=m
127 : __ct_2 typ=uint2_ val=2f bnd=m
137 : __tmp typ=uint3_ bnd=m
141 : __tmp typ=int18_ bnd=m
150 : __either typ=bool bnd=m
151 : __trgt typ=int10_ val=0j bnd=m
152 : __trgt typ=int10_ val=0j bnd=m
153 : __trgt typ=int10_ val=0j bnd=m
154 : __trgt typ=int10_ val=0j bnd=m
155 : __trgt typ=uint16_ val=0j bnd=m
156 : __vcnt typ=uint16_ bnd=m
]
F_Z14cyclic_add_manPViiS0_i {
#206 off=0
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__ct_0.35 var=37) const () <59>;
(__la.37 var=38 stl=LR off=0) inp () <61>;
(__la.38 var=38) deassign (__la.37) <62>;
(ptr.41 var=40 stl=A off=1) inp () <65>;
(ptr.42 var=40) deassign (ptr.41) <66>;
(i_pp.44 var=41 stl=RA off=0) inp () <68>;
(i_pp.45 var=41) deassign (i_pp.44) <69>;
(ptr_start.47 var=42 stl=A off=2) inp () <71>;
(ptr_start.48 var=42) deassign (ptr_start.47) <72>;
(buffer_len.50 var=43 stl=RA off=1) inp () <74>;
(buffer_len.51 var=43) deassign (buffer_len.50) <75>;
(__rd___sp.53 var=36) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.213 __sp.32) <81>;
(__ct_0.64 var=50) const () <88>;
(__tmp.66 var=52) __sint_abs___sint (i_pp.45) <90>;
(__rt.213 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.297) <264>;
(__ct_0S0.297 var=114) const () <381>;
(__tmp.304 var=122) uint3__cmp_int72__int72_ (__tmp.66 __ct_0.64) <394>;
(__tmp.329 var=53) bool_nplus_uint3_ (__tmp.304) <450>;
(__trgt.336 var=153) const () <468>;
() void_jump_bool_int10_ (__tmp.329 __trgt.336) <469>;
(__either.337 var=150) undefined () <470>;
if {
{
() if_expr (__either.337) <108>;
() chess_frequent_else () <109>;
() chess_rear_then () <471>;
} #5
{
(__trgt.338 var=154) const () <472>;
() void_jump_int10_ (__trgt.338) <473>;
} #18 off=7
{
#154 off=1
(__cv.196 var=78) uint16__uint16____sint (__tmp.66) <234>;
(__ct_2.199 var=83) const () <238>;
(__rt.257 var=86) __Pvoid__pl___Pvoid_int18_ (ptr_start.48 __tmp.310) <320>;
(__ct_4.298 var=115) const () <383>;
(__ct_2.309 var=127) const () <402>;
(__tmp.310 var=141) int72__shift_int72__int72__uint2_ (buffer_len.51 __ct_2.199 __ct_2.309) <403>;
(__trgt.333 var=151) const () <463>;
(__trgt.335 var=152) const () <466>;
(__trgt.339 var=155) const () <474>;
() void_doloop_uint16__uint16_ (__cv.196 __trgt.339) <475>;
(__vcnt.340 var=156) undefined () <476>;
for {
{
(p_ptr.92 var=47) entry (p_ptr.146 ptr.42) <118>;
} #8
{
#223 off=2
(__rt.235 var=86) __Pvoid__pl___Pvoid_int18_ (p_ptr.92 __ct_4.298) <292>;
(__tmp.319 var=137) uint3__cmp_int72__int72_ (__rt.235 __rt.257) <418>;
(__tmp.330 var=109) bool_neg_uint3_ (__tmp.319) <451>;
() void_jump_bool_int10_ (__tmp.330 __trgt.333) <464>;
(__either.334 var=150) undefined () <465>;
if {
{
() if_expr (__either.334) <150>;
} #12
{
} #14 off=4
{
() void_jump_int10_ (__trgt.335) <467>;
} #13 off=3
{
(p_ptr.124 var=47) merge (__rt.235 ptr_start.48) <151>;
} #15
} #11
} #9
{
() for_count (__vcnt.340) <157>;
(p_ptr.146 var=47 p_ptr.147 var=47) exit (p_ptr.124) <166>;
} #17
} #7 rng=[1,65535]
} #6
{
(p_ptr.162 var=47) merge (ptr.42 p_ptr.147) <174>;
} #19
} #4
#21 off=8 nxt=-2
(__rd___sp.165 var=36) rd_res_reg (__R_SP.24 __sp.58) <177>;
(__R_SP.169 var=26 __sp.170 var=34) wr_res_reg (__rt.284 __sp.58) <181>;
() void_ret_dmaddr_ (__la.38) <182>;
(p_ptr.171 var=47 stl=A off=0) assign (p_ptr.162) <183>;
() out (p_ptr.171) <184>;
() sink (__sp.170) <190>;
() sink (__ct_0.35) <192>;
(__rt.284 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.165 __ct_0s0.301) <356>;
(__ct_0s0.301 var=118) const () <389>;
} #0
0 : 'main.c';
----------
0 : (0,27:0,0);
4 : (0,29:8,3);
6 : (0,29:8,4);
7 : (0,29:8,4);
9 : (0,29:42,4);
11 : (0,31:16,7);
13 : (0,31:52,8);
14 : (0,31:16,11);
18 : (0,29:8,18);
21 : (0,35:8,21);
206 : (0,29:8,3);
223 : (0,31:26,7);
----------
77 : (0,27:14,0);
81 : (0,27:14,0);
88 : (0,29:19,0);
90 : (0,29:8,3);
108 : (0,29:8,3);
118 : (0,29:8,4);
150 : (0,31:16,7);
151 : (0,31:16,13);
157 : (0,29:8,16);
166 : (0,29:8,16);
174 : (0,29:8,20);
177 : (0,35:8,0);
181 : (0,35:8,21);
182 : (0,35:8,21);
183 : (0,35:15,0);
238 : (0,31:41,0);
264 : (0,27:14,0);
292 : (0,30:22,5);
320 : (0,31:39,7);
356 : (0,35:8,0);
381 : (0,27:14,0);
383 : (0,30:22,0);
389 : (0,35:8,0);
394 : (0,29:8,3);
402 : (0,31:41,0);
403 : (0,31:41,7);
418 : (0,31:26,7);
450 : (0,29:8,3);
451 : (0,31:26,7);
464 : (0,31:16,7);
469 : (0,29:8,3);
475 : (0,29:8,16);

6
testcode/Release/chesswork/main-9f2435.#
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@@ -1,8 +1,8 @@
466ba9a29dd6732e5048de41303e492793f3e524
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
1c8bbe93adae4ad958181e7bbdf3e50dc29b30bf
0bc9b730bee8cc49bb784bfd437498d97d237a7b
da39a3ee5e6b4b0d3255bfef95601890afd80709
caeed1d8261c9d5b0f3a72abdea803be6cd42cdc
42
c1a761eae81ed68af1d89a135a516a64d0e8a00c
44
0

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testcode/Release/chesswork/main-9f2435.o
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testcode/Release/chesswork/main-9f2435.sfg
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@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -14,6 +14,14 @@ F_main : user_defined, called {
frm : ( );
}
****
!! int max_man(int, int)
F_Z7max_manii : user_defined, called {
fnm : "max_man" 'int max_man(int, int)';
arg : ( dmaddr_:i int32_:r int32_:i int32_:i );
loc : ( LR[0] RA[0] RA[1] RB[0] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
***/
[
@@ -22,139 +30,382 @@ F_main : user_defined, called {
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
29 : __vola typ=uint20_ bnd=b stl=PM
32 : __extDM typ=int8_ bnd=b stl=DM
33 : __extPM typ=uint20_ bnd=b stl=PM
34 : __sp typ=dmaddr_ bnd=b stl=SP
35 : _ZL6sample typ=int8_ bnd=i sz=2 algn=2 stl=DMB tref=int16_t_DMB
37 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
38 : _ZL7pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
40 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
41 : __rd___sp typ=dmaddr_ bnd=m
43 : __ptr_sample typ=dmaddr_ val=0a bnd=m adro=35
45 : __ct_8388608 typ=dmaddr_ val=8388608f bnd=m
47 : __ptr_pointer typ=dmaddr_ val=0a bnd=m adro=38
49 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m
50 : __ct_0 typ=uint1_ val=0f bnd=m
51 : __la typ=dmaddr_ bnd=p tref=dmaddr___
52 : __rt typ=int32_ bnd=p tref=__sint__
56 : __ct_123 typ=int8_ val=123f bnd=m
58 : __ct_100 typ=int8_ val=100f bnd=m
60 : __ct_0 typ=int32_ val=0f bnd=m
63 : __ct_101 typ=int8_ val=101f bnd=m
68 : __ct_102 typ=int8_ val=102f bnd=m
73 : __ct_103 typ=int8_ val=103f bnd=m
81 : __ct_200 typ=uint8_ val=200f bnd=m
86 : __ct_201 typ=uint8_ val=201f bnd=m
91 : __ct_202 typ=uint8_ val=202f bnd=m
96 : __ct_203 typ=uint8_ val=203f bnd=m
118 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
146 : __ct_0S0 typ=int18_ val=0S0 bnd=m
147 : __ct_0s0 typ=int18_ val=0s0 bnd=m
148 : __ct_2 typ=int18_ val=2f bnd=m
150 : __ct_6 typ=int18_ val=6f bnd=m
35 : _ZL7pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
36 : __extDM___PDMint16_ typ=int8_ bnd=b stl=DM
37 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
38 : __extDM_int16_ typ=int8_ bnd=b stl=DM
39 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
40 : i typ=int8_ bnd=e sz=4 algn=4 stl=DMA tref=__sint_DMA
41 : __extDM_int32_ typ=int8_ bnd=b stl=DM
42 : result_1 typ=int8_ bnd=e sz=4 algn=4 stl=DMA tref=__sint_DMA
43 : int1 typ=int8_ bnd=e sz=4 algn=4 stl=DMA tref=__sint_DMA
44 : int2 typ=int8_ bnd=e sz=4 algn=4 stl=DMA tref=__sint_DMA
45 : result_2 typ=int8_ bnd=e sz=4 algn=4 stl=DMA tref=__sint_DMA
46 : __extDM_void typ=int8_ bnd=b stl=DM
47 : __extPM_void typ=uint20_ bnd=b stl=PM
48 : __rd___sp typ=dmaddr_ bnd=m
50 : __ptr_pointer typ=dmaddr_ val=0a bnd=m adro=35
52 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m
54 : __ct_8388608 typ=dmaddr_ val=8388608f bnd=m
56 : __ptr_i typ=dmaddr_ val=0a bnd=m adro=40
58 : __ptr_result_1 typ=dmaddr_ val=0a bnd=m adro=42
60 : __ptr_int1 typ=dmaddr_ val=0a bnd=m adro=43
62 : __ptr_int2 typ=dmaddr_ val=0a bnd=m adro=44
64 : __ptr_result_2 typ=dmaddr_ val=0a bnd=m adro=45
65 : __ct_0 typ=uint1_ val=0f bnd=m
66 : __la typ=dmaddr_ bnd=p tref=dmaddr___
67 : __rt typ=int32_ bnd=p tref=__sint__
71 : __ct_0 typ=int32_ val=0f bnd=m
74 : __ct_100 typ=int8_ val=100f bnd=m
79 : __ct_101 typ=int8_ val=101f bnd=m
84 : __ct_102 typ=int8_ val=102f bnd=m
89 : __ct_103 typ=int8_ val=103f bnd=m
94 : __ct_200 typ=uint8_ val=200f bnd=m
99 : __ct_201 typ=uint8_ val=201f bnd=m
104 : __ct_202 typ=uint8_ val=202f bnd=m
109 : __ct_203 typ=uint8_ val=203f bnd=m
114 : __fch_i typ=int32_ bnd=m
115 : __ct_10 typ=int32_ val=10f bnd=m
117 : __tmp typ=bool bnd=m
118 : __fch_int1 typ=int32_ bnd=m
119 : __fch_int2 typ=int32_ bnd=m
120 : __tmp typ=int32_ bnd=m
121 : __fch_int1 typ=int32_ bnd=m
122 : __fch_int2 typ=int32_ bnd=m
123 : _Z7max_manii typ=dmaddr_ val=0r bnd=m
125 : __link typ=dmaddr_ bnd=m
126 : __tmp typ=int32_ bnd=m
127 : __fch_i typ=int32_ bnd=m
128 : __ct_1 typ=int32_ val=1f bnd=m
130 : __tmp typ=int32_ bnd=m
134 : __tmp typ=bool bnd=m
153 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
180 : __ct_0S0 typ=int18_ val=0S0 bnd=m
181 : __ct_0s0 typ=int18_ val=0s0 bnd=m
182 : __ct_2 typ=int18_ val=2f bnd=m
186 : __tmp typ=uint3_ bnd=m
197 : __either typ=bool bnd=m
198 : __trgt typ=int10_ val=0j bnd=m
199 : __trgt typ=int10_ val=0j bnd=m
200 : __trgt typ=int10_ val=0j bnd=m
]
F_main {
#404 off=0
(__M_WDMA.9 var=11) st_def () <18>;
(__R_SP.24 var=26) st_def () <48>;
(__vola.27 var=29) source () <51>;
(__extDM.30 var=32) source () <54>;
(__extPM.31 var=33) source () <55>;
(__sp.32 var=34) source () <56>;
(_ZL6sample.33 var=35) source () <57>;
(_ZL10input_port.35 var=37) source () <59>;
(_ZL7pointer.36 var=38) source () <60>;
(_ZL11output_port.38 var=40) source () <62>;
(__ptr_sample.40 var=43) const () <64>;
(__ct_8388608.42 var=45) const () <66>;
(__ptr_pointer.45 var=47) const () <69>;
(__ct_8388624.47 var=49) const () <71>;
(__ct_0.50 var=50) const () <74>;
(__la.52 var=51 stl=LR off=0) inp () <76>;
(__la.53 var=51) deassign (__la.52) <77>;
(__rd___sp.56 var=41) rd_res_reg (__R_SP.24 __sp.32) <80>;
(__R_SP.60 var=26 __sp.61 var=34) wr_res_reg (__rt.189 __sp.32) <84>;
(__ct_123.62 var=56) const () <86>;
(__M_SDMB.64 var=8 _ZL6sample.65 var=35 __vola.66 var=29) store (__ct_123.62 __ptr_sample.40 _ZL6sample.33 __vola.27) <88>;
(__ct_100.67 var=58) const () <89>;
(__ct_0.69 var=60) const () <91>;
(__M_SDMB.72 var=8 _ZL10input_port.73 var=37 __vola.74 var=29) store (__ct_100.67 __ct_8388608.42 _ZL10input_port.35 __vola.66) <94>;
(__ct_101.75 var=63) const () <95>;
(__M_SDMB.80 var=8 _ZL10input_port.81 var=37 __vola.82 var=29) store (__ct_101.75 __rt.233 _ZL10input_port.73 __vola.74) <100>;
(__ct_102.83 var=68) const () <101>;
(__M_SDMB.88 var=8 _ZL10input_port.89 var=37 __vola.90 var=29) store (__ct_102.83 __rt.255 _ZL10input_port.81 __vola.82) <106>;
(__ct_103.91 var=73) const () <107>;
(__M_SDMB.96 var=8 _ZL10input_port.97 var=37 __vola.98 var=29) store (__ct_103.91 __rt.277 _ZL10input_port.89 __vola.90) <112>;
(__M_WDMA.102 var=11 _ZL7pointer.103 var=38) store (__rt.299 __ptr_pointer.45 _ZL7pointer.36) <116>;
(__ct_200.104 var=81) const () <117>;
(__M_SDMB.109 var=8 _ZL11output_port.110 var=40 __vola.111 var=29) store (__ct_200.104 __ct_8388624.47 _ZL11output_port.38 __vola.98) <122>;
(__ct_201.112 var=86) const () <123>;
(__M_SDMB.117 var=8 _ZL11output_port.118 var=40 __vola.119 var=29) store (__ct_201.112 __rt.321 _ZL11output_port.110 __vola.111) <128>;
(__ct_202.120 var=91) const () <129>;
(__M_SDMB.125 var=8 _ZL11output_port.126 var=40 __vola.127 var=29) store (__ct_202.120 __rt.343 _ZL11output_port.118 __vola.119) <134>;
(__ct_203.128 var=96) const () <135>;
(__M_SDMB.133 var=8 _ZL11output_port.134 var=40 __vola.135 var=29) store (__ct_203.128 __rt.365 _ZL11output_port.126 __vola.127) <140>;
(__rd___sp.138 var=41) rd_res_reg (__R_SP.24 __sp.61) <143>;
(__R_SP.142 var=26 __sp.143 var=34) wr_res_reg (__rt.211 __sp.61) <147>;
() void_ret_dmaddr_ (__la.53) <148>;
(__rt.144 var=52 stl=RA off=0) assign (__ct_0.69) <149>;
() out (__rt.144) <150>;
() sink (__vola.135) <151>;
() sink (__sp.143) <156>;
() sink (_ZL6sample.65) <157>;
() sink (_ZL10input_port.97) <159>;
() sink (_ZL7pointer.103) <160>;
() sink (_ZL11output_port.134) <162>;
() sink (__ct_0.50) <163>;
(__rt.189 var=118) __Pvoid__pl___Pvoid_int18_ (__rd___sp.56 __ct_0S0.378) <277>;
(__rt.211 var=118) __Pvoid__pl___Pvoid_int18_ (__rd___sp.138 __ct_0s0.379) <305>;
(__rt.233 var=118) __Pvoid__pl___Pvoid_int18_ (__ct_8388608.42 __ct_2.380) <333>;
(__rt.255 var=118) __Pvoid__pl___Pvoid_int18_ (__rt.233 __ct_2.380) <361>;
(__rt.277 var=118) __Pvoid__pl___Pvoid_int18_ (__rt.255 __ct_2.380) <389>;
(__rt.299 var=118) __Pvoid__mi___Pvoid_int18_ (__rt.277 __ct_6.382) <417>;
(__rt.321 var=118) __Pvoid__pl___Pvoid_int18_ (__ct_8388624.47 __ct_2.380) <445>;
(__rt.343 var=118) __Pvoid__pl___Pvoid_int18_ (__rt.321 __ct_2.380) <473>;
(__rt.365 var=118) __Pvoid__pl___Pvoid_int18_ (__rt.343 __ct_2.380) <501>;
(__ct_0S0.378 var=146) const () <539>;
(__ct_0s0.379 var=147) const () <541>;
(__ct_2.380 var=148) const () <543>;
(__ct_6.382 var=150) const () <547>;
} #5 off=0 nxt=-2
(_ZL7pointer.33 var=35) source () <57>;
(__extDM___PDMint16_.34 var=36) source () <58>;
(_ZL11output_port.35 var=37) source () <59>;
(__extDM_int16_.36 var=38) source () <60>;
(_ZL10input_port.37 var=39) source () <61>;
(i.38 var=40) source () <62>;
(__extDM_int32_.39 var=41) source () <63>;
(result_1.40 var=42) source () <64>;
(int1.41 var=43) source () <65>;
(int2.42 var=44) source () <66>;
(result_2.43 var=45) source () <67>;
(__extDM_void.44 var=46) source () <68>;
(__extPM_void.45 var=47) source () <69>;
(__ptr_pointer.47 var=50) const () <71>;
(__ct_8388624.49 var=52) const () <73>;
(__ct_8388608.52 var=54) const () <76>;
(__ptr_i.55 var=56) const () <79>;
(__ct_0.65 var=65) const () <89>;
(__la.67 var=66 stl=LR off=0) inp () <91>;
(__la.68 var=66) deassign (__la.67) <92>;
(__rd___sp.71 var=48) rd_res_reg (__R_SP.24 __sp.32) <95>;
(__R_SP.75 var=26 __sp.76 var=34) wr_res_reg (__rt.388 __sp.32) <99>;
(__M_WDMA.80 var=11 _ZL7pointer.81 var=35) store (__ct_8388624.49 __ptr_pointer.47 _ZL7pointer.33) <104>;
(__ct_100.82 var=74) const () <105>;
(__M_SDMB.87 var=8 _ZL10input_port.88 var=39 __vola.89 var=29) store (__ct_100.82 __ct_8388608.52 _ZL10input_port.37 __vola.27) <110>;
(__ct_101.90 var=79) const () <111>;
(__M_SDMB.95 var=8 _ZL10input_port.96 var=39 __vola.97 var=29) store (__ct_101.90 __rt.498 _ZL10input_port.88 __vola.89) <116>;
(__ct_102.98 var=84) const () <117>;
(__M_SDMB.103 var=8 _ZL10input_port.104 var=39 __vola.105 var=29) store (__ct_102.98 __rt.520 _ZL10input_port.96 __vola.97) <122>;
(__ct_103.106 var=89) const () <123>;
(__M_SDMB.111 var=8 _ZL10input_port.112 var=39 __vola.113 var=29) store (__ct_103.106 __rt.542 _ZL10input_port.104 __vola.105) <128>;
(__ct_200.114 var=94) const () <129>;
(__M_SDMB.119 var=8 _ZL11output_port.120 var=37 __vola.121 var=29) store (__ct_200.114 __ct_8388624.49 _ZL11output_port.35 __vola.113) <134>;
(__ct_201.122 var=99) const () <135>;
(__M_SDMB.127 var=8 _ZL11output_port.128 var=37 __vola.129 var=29) store (__ct_201.122 __rt.432 _ZL11output_port.120 __vola.121) <140>;
(__ct_202.130 var=104) const () <141>;
(__M_SDMB.135 var=8 _ZL11output_port.136 var=37 __vola.137 var=29) store (__ct_202.130 __rt.454 _ZL11output_port.128 __vola.129) <146>;
(__ct_203.138 var=109) const () <147>;
(__M_SDMB.143 var=8 _ZL11output_port.144 var=37 __vola.145 var=29) store (__ct_203.138 __rt.476 _ZL11output_port.136 __vola.137) <152>;
(__fch_i.146 var=114) load (__M_WDMA.9 __ptr_i.55 i.38) <153>;
(__ct_10.147 var=115) const () <154>;
(__rt.388 var=153) __Pvoid__pl___Pvoid_int18_ (__rd___sp.71 __ct_0S0.555) <456>;
(__rt.432 var=153) __Pvoid__pl___Pvoid_int18_ (__ct_8388624.49 __ct_2.557) <512>;
(__rt.454 var=153) __Pvoid__pl___Pvoid_int18_ (__rt.432 __ct_2.557) <540>;
(__rt.476 var=153) __Pvoid__pl___Pvoid_int18_ (__rt.454 __ct_2.557) <568>;
(__rt.498 var=153) __Pvoid__pl___Pvoid_int18_ (__ct_8388608.52 __ct_2.557) <596>;
(__rt.520 var=153) __Pvoid__pl___Pvoid_int18_ (__rt.498 __ct_2.557) <624>;
(__rt.542 var=153) __Pvoid__pl___Pvoid_int18_ (__rt.520 __ct_2.557) <652>;
(__ct_0S0.555 var=180) const () <695>;
(__ct_2.557 var=182) const () <699>;
(__tmp.560 var=186) uint3__cmp_int72__int72_ (__fch_i.146 __ct_10.147) <704>;
(__tmp.573 var=117) bool_nneg_uint3_ (__tmp.560) <774>;
(__trgt.578 var=199) const () <806>;
() void_jump_bool_int10_ (__tmp.573 __trgt.578) <807>;
(__either.579 var=197) undefined () <808>;
if {
{
() if_expr (__either.579) <186>;
() chess_frequent_else () <187>;
() chess_rear_then () <809>;
} #5
{
(__trgt.580 var=200) const () <810>;
() void_jump_int10_ (__trgt.580) <811>;
} #14 off=6
{
#447 off=1
(__ptr_result_1.57 var=58) const () <81>;
(__ptr_int1.59 var=60) const () <83>;
(__ptr_int2.61 var=62) const () <85>;
(__ptr_result_2.63 var=64) const () <87>;
(_Z7max_manii.217 var=123) const () <225>;
(__ct_1.243 var=128) const () <234>;
(__trgt.576 var=198) const () <803>;
do {
{
(__vola.179 var=29) entry (__vola.252 __vola.145) <188>;
(__extDM.182 var=32) entry (__extDM.258 __extDM.30) <191>;
(__extPM.183 var=33) entry (__extPM.260 __extPM.31) <192>;
(_ZL7pointer.185 var=35) entry (_ZL7pointer.264 _ZL7pointer.81) <194>;
(__extDM___PDMint16_.186 var=36) entry (__extDM___PDMint16_.266 __extDM___PDMint16_.34) <195>;
(_ZL11output_port.187 var=37) entry (_ZL11output_port.268 _ZL11output_port.144) <196>;
(__extDM_int16_.188 var=38) entry (__extDM_int16_.270 __extDM_int16_.36) <197>;
(_ZL10input_port.189 var=39) entry (_ZL10input_port.272 _ZL10input_port.112) <198>;
(i.190 var=40) entry (i.274 i.38) <199>;
(__extDM_int32_.191 var=41) entry (__extDM_int32_.276 __extDM_int32_.39) <200>;
(result_1.192 var=42) entry (result_1.278 result_1.40) <201>;
(int1.193 var=43) entry (int1.280 int1.41) <202>;
(int2.194 var=44) entry (int2.282 int2.42) <203>;
(result_2.195 var=45) entry (result_2.284 result_2.43) <204>;
(__extDM_void.196 var=46) entry (__extDM_void.286 __extDM_void.44) <205>;
(__extPM_void.197 var=47) entry (__extPM_void.288 __extPM_void.45) <206>;
} #8
{
#10 off=2
(__fch_int1.208 var=118) load (__M_WDMA.9 __ptr_int1.59 int1.193) <217>;
(__fch_int2.209 var=119) load (__M_WDMA.9 __ptr_int2.61 int2.194) <218>;
(__tmp.210 var=120) __sint_max___sint___sint (__fch_int1.208 __fch_int2.209) <219>;
(__M_WDMA.211 var=11 result_1.212 var=42) store (__tmp.210 __ptr_result_1.57 result_1.192) <220>;
(__link.219 var=125) dmaddr__call_dmaddr_ (_Z7max_manii.217) <227>;
call {
(__fch_int1.214 var=121 stl=RA off=1) assign (__fch_int1.208) <222>;
(__fch_int2.216 var=122 stl=RB off=0) assign (__fch_int2.209) <224>;
(__link.220 var=125 stl=LR off=0) assign (__link.219) <228>;
(__tmp.221 var=126 stl=RA off=0 _ZL10input_port.224 var=39 _ZL11output_port.225 var=37 _ZL7pointer.226 var=35 __extDM.227 var=32 __extDM___PDMint16_.228 var=36 __extDM_int16_.229 var=38 __extDM_int32_.230 var=41 __extDM_void.231 var=46 __extPM.232 var=33 __extPM_void.233 var=47 i.234 var=40 int1.235 var=43 int2.236 var=44 result_1.237 var=42 result_2.238 var=45 __vola.239 var=29) F_Z7max_manii (__link.220 __fch_int1.214 __fch_int2.216 _ZL10input_port.189 _ZL11output_port.187 _ZL7pointer.185 __extDM.182 __extDM___PDMint16_.186 __extDM_int16_.188 __extDM_int32_.191 __extDM_void.196 __extPM.183 __extPM_void.197 i.190 int1.193 int2.194 result_1.212 result_2.195 __vola.179) <229>;
(__tmp.222 var=126) deassign (__tmp.221) <230>;
} #11 off=3
#412 off=4
(__M_WDMA.240 var=11 result_2.241 var=45) store (__tmp.222 __ptr_result_2.63 result_2.238) <232>;
(__fch_i.242 var=127) load (__M_WDMA.9 __ptr_i.55 i.234) <233>;
(__tmp.245 var=130) __sint__pl___sint___sint (__fch_i.242 __ct_1.243) <236>;
(__M_WDMA.246 var=11 i.247 var=40) store (__tmp.245 __ptr_i.55 i.234) <237>;
(__tmp.565 var=186) uint3__cmp_int72__int72_ (__tmp.245 __ct_10.147) <712>;
(__tmp.566 var=134) bool_neg_uint3_ (__tmp.565) <713>;
() void_jump_bool_int10_ (__tmp.566 __trgt.576) <804>;
(__either.577 var=197) undefined () <805>;
} #9
{
() while_expr (__either.577) <242>;
(__vola.252 var=29 __vola.253 var=29) exit (__vola.239) <243>;
(__extDM.258 var=32 __extDM.259 var=32) exit (__extDM.227) <246>;
(__extPM.260 var=33 __extPM.261 var=33) exit (__extPM.232) <247>;
(_ZL7pointer.264 var=35 _ZL7pointer.265 var=35) exit (_ZL7pointer.226) <249>;
(__extDM___PDMint16_.266 var=36 __extDM___PDMint16_.267 var=36) exit (__extDM___PDMint16_.228) <250>;
(_ZL11output_port.268 var=37 _ZL11output_port.269 var=37) exit (_ZL11output_port.225) <251>;
(__extDM_int16_.270 var=38 __extDM_int16_.271 var=38) exit (__extDM_int16_.229) <252>;
(_ZL10input_port.272 var=39 _ZL10input_port.273 var=39) exit (_ZL10input_port.224) <253>;
(i.274 var=40 i.275 var=40) exit (i.247) <254>;
(__extDM_int32_.276 var=41 __extDM_int32_.277 var=41) exit (__extDM_int32_.230) <255>;
(result_1.278 var=42 result_1.279 var=42) exit (result_1.237) <256>;
(int1.280 var=43 int1.281 var=43) exit (int1.235) <257>;
(int2.282 var=44 int2.283 var=44) exit (int2.236) <258>;
(result_2.284 var=45 result_2.285 var=45) exit (result_2.241) <259>;
(__extDM_void.286 var=46 __extDM_void.287 var=46) exit (__extDM_void.231) <260>;
(__extPM_void.288 var=47 __extPM_void.289 var=47) exit (__extPM_void.233) <261>;
} #13
} #7 rng=[1,65535]
} #6
{
(__vola.310 var=29) merge (__vola.145 __vola.253) <272>;
(__extDM.311 var=32) merge (__extDM.30 __extDM.259) <273>;
(__extPM.312 var=33) merge (__extPM.31 __extPM.261) <274>;
(_ZL7pointer.313 var=35) merge (_ZL7pointer.81 _ZL7pointer.265) <275>;
(__extDM___PDMint16_.314 var=36) merge (__extDM___PDMint16_.34 __extDM___PDMint16_.267) <276>;
(_ZL11output_port.315 var=37) merge (_ZL11output_port.144 _ZL11output_port.269) <277>;
(__extDM_int16_.316 var=38) merge (__extDM_int16_.36 __extDM_int16_.271) <278>;
(_ZL10input_port.317 var=39) merge (_ZL10input_port.112 _ZL10input_port.273) <279>;
(i.318 var=40) merge (i.38 i.275) <280>;
(__extDM_int32_.319 var=41) merge (__extDM_int32_.39 __extDM_int32_.277) <281>;
(result_1.320 var=42) merge (result_1.40 result_1.279) <282>;
(int1.321 var=43) merge (int1.41 int1.281) <283>;
(int2.322 var=44) merge (int2.42 int2.283) <284>;
(result_2.323 var=45) merge (result_2.43 result_2.285) <285>;
(__extDM_void.324 var=46) merge (__extDM_void.44 __extDM_void.287) <286>;
(__extPM_void.325 var=47) merge (__extPM_void.45 __extPM_void.289) <287>;
} #15
} #4
#18 off=7 nxt=-2
(__ct_0.77 var=71) const () <101>;
(__rd___sp.328 var=48) rd_res_reg (__R_SP.24 __sp.76) <290>;
(__R_SP.332 var=26 __sp.333 var=34) wr_res_reg (__rt.410 __sp.76) <294>;
() void_ret_dmaddr_ (__la.68) <295>;
(__rt.334 var=67 stl=RA off=0) assign (__ct_0.77) <296>;
() out (__rt.334) <297>;
() sink (__vola.310) <298>;
() sink (__extDM.311) <301>;
() sink (__extPM.312) <302>;
() sink (__sp.333) <303>;
() sink (_ZL7pointer.313) <304>;
() sink (__extDM___PDMint16_.314) <305>;
() sink (_ZL11output_port.315) <306>;
() sink (__extDM_int16_.316) <307>;
() sink (_ZL10input_port.317) <308>;
() sink (i.318) <309>;
() sink (__extDM_int32_.319) <310>;
() sink (result_1.320) <311>;
() sink (int1.321) <312>;
() sink (int2.322) <313>;
() sink (result_2.323) <314>;
() sink (__extDM_void.324) <315>;
() sink (__extPM_void.325) <316>;
() sink (__ct_0.65) <317>;
(__rt.410 var=153) __Pvoid__pl___Pvoid_int18_ (__rd___sp.328 __ct_0s0.556) <484>;
(__ct_0s0.556 var=181) const () <697>;
} #0
0 : 'main.c';
----------
5 : (0,42:0,11);
0 : (0,44:0,0);
4 : (0,56:4,10);
6 : (0,56:4,11);
7 : (0,56:4,11);
9 : (0,56:17,11);
10 : (0,58:32,12);
11 : (0,58:19,12);
14 : (0,56:4,17);
18 : (0,66:0,20);
404 : (0,56:4,10);
412 : (0,56:12,15);
----------
66 : (0,31:4,0);
71 : (0,36:4,0);
80 : (0,27:4,0);
84 : (0,27:4,0);
86 : (0,29:11,0);
88 : (0,29:4,1);
89 : (0,31:18,0);
91 : (0,31:15,0);
94 : (0,31:14,2);
95 : (0,32:18,0);
100 : (0,32:14,3);
101 : (0,33:18,0);
106 : (0,33:14,4);
107 : (0,34:18,0);
112 : (0,34:14,5);
116 : (0,35:4,6);
117 : (0,36:19,0);
122 : (0,36:15,7);
123 : (0,37:19,0);
128 : (0,37:15,8);
129 : (0,38:19,0);
134 : (0,38:15,9);
135 : (0,39:19,0);
140 : (0,39:15,10);
143 : (0,42:0,0);
147 : (0,42:0,11);
148 : (0,42:0,11);
149 : (0,42:0,0);
277 : (0,27:4,0);
305 : (0,42:0,0);
333 : (0,32:14,0);
361 : (0,33:14,0);
389 : (0,34:14,0);
445 : (0,37:15,0);
473 : (0,38:15,0);
501 : (0,39:15,0);
539 : (0,27:4,0);
541 : (0,42:0,0);
543 : (0,32:14,0);
73 : (0,45:15,0);
76 : (0,47:4,0);
95 : (0,44:4,0);
99 : (0,44:4,0);
101 : (0,45:27,0);
104 : (0,45:4,1);
105 : (0,47:18,0);
110 : (0,47:14,2);
111 : (0,48:18,0);
116 : (0,48:14,3);
117 : (0,49:18,0);
122 : (0,49:14,4);
123 : (0,50:18,0);
128 : (0,50:14,5);
129 : (0,51:19,0);
134 : (0,51:15,6);
135 : (0,52:19,0);
140 : (0,52:15,7);
141 : (0,53:19,0);
146 : (0,53:15,8);
147 : (0,54:19,0);
152 : (0,54:15,9);
153 : (0,56:4,10);
154 : (0,56:4,0);
186 : (0,56:4,10);
188 : (0,56:4,11);
191 : (0,56:4,11);
192 : (0,56:4,11);
194 : (0,56:4,11);
195 : (0,56:4,11);
196 : (0,56:4,11);
197 : (0,56:4,11);
198 : (0,56:4,11);
199 : (0,56:4,11);
200 : (0,56:4,11);
201 : (0,56:4,11);
202 : (0,56:4,11);
203 : (0,56:4,11);
204 : (0,56:4,11);
205 : (0,56:4,11);
206 : (0,56:4,11);
217 : (0,57:22,11);
218 : (0,57:27,11);
219 : (0,57:18,11);
220 : (0,57:7,11);
222 : (0,58:27,0);
224 : (0,58:32,0);
227 : (0,58:19,12);
228 : (0,58:19,0);
229 : (0,58:19,12);
232 : (0,58:8,12);
233 : (0,59:10,13);
234 : (0,59:12,0);
236 : (0,59:11,13);
237 : (0,59:8,13);
242 : (0,56:4,15);
243 : (0,56:4,15);
246 : (0,56:4,15);
247 : (0,56:4,15);
249 : (0,56:4,15);
250 : (0,56:4,15);
251 : (0,56:4,15);
252 : (0,56:4,15);
253 : (0,56:4,15);
254 : (0,56:4,15);
255 : (0,56:4,15);
256 : (0,56:4,15);
257 : (0,56:4,15);
258 : (0,56:4,15);
259 : (0,56:4,15);
260 : (0,56:4,15);
261 : (0,56:4,15);
272 : (0,56:4,19);
273 : (0,56:4,19);
274 : (0,56:4,19);
275 : (0,56:4,19);
276 : (0,56:4,19);
277 : (0,56:4,19);
278 : (0,56:4,19);
279 : (0,56:4,19);
280 : (0,56:4,19);
281 : (0,56:4,19);
282 : (0,56:4,19);
283 : (0,56:4,19);
284 : (0,56:4,19);
285 : (0,56:4,19);
286 : (0,56:4,19);
287 : (0,56:4,19);
290 : (0,66:0,0);
294 : (0,66:0,20);
295 : (0,66:0,20);
296 : (0,66:0,0);
456 : (0,44:4,0);
484 : (0,66:0,0);
512 : (0,52:15,0);
540 : (0,53:15,0);
568 : (0,54:15,0);
596 : (0,48:14,0);
624 : (0,49:14,0);
652 : (0,50:14,0);
695 : (0,44:4,0);
697 : (0,66:0,0);
699 : (0,52:15,0);
704 : (0,56:4,10);
712 : (0,56:12,15);
713 : (0,56:12,15);
774 : (0,56:4,10);
804 : (0,56:4,15);
807 : (0,56:4,10);

12
testcode/Release/chesswork/main-c9e472.# Normal file
View File

@@ -0,0 +1,12 @@
466ba9a29dd6732e5048de41303e492793f3e524
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
44e466225afc14310af4127296f3e930522b437a
da39a3ee5e6b4b0d3255bfef95601890afd80709
c1d69c128ff9a82b968712738ba20371e0c02a50
26
0
0
0
5
5

BIN
testcode/Release/chesswork/main-c9e472.o Normal file
View File

Binary file not shown.

195
testcode/Release/chesswork/main-c9e472.sfg Normal file
View File

@@ -0,0 +1,195 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
/***
!! int *cyclic_add_man(int *, int, int *, int)
F_Z14cyclic_add_manPiiS_i : user_defined, called {
fnm : "cyclic_add_man" 'int *cyclic_add_man(int *, int, int *, int)';
arg : ( dmaddr_:i dmaddr_:r dmaddr_:i int32_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] A[1] RA[0] A[2] RA[1] );
vac : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : _Z14cyclic_add_manPiiS_i typ=uint20_ bnd=e stl=PM tref=__P__sint_____P__sint___sint___P__sint___sint__
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
34 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __rd___sp typ=dmaddr_ bnd=m
37 : __ct_0 typ=uint1_ val=0f bnd=m
38 : __la typ=dmaddr_ bnd=p tref=dmaddr___
40 : pointer typ=dmaddr_ bnd=p tref=__P__sint__
41 : increment typ=int32_ bnd=p tref=__sint__
42 : pointer_start typ=dmaddr_ bnd=p tref=__P__sint__
43 : buffer_length typ=int32_ bnd=p tref=__sint__
47 : new_pointer typ=dmaddr_ bnd=m tref=__P__sint__
50 : __ct_0 typ=int32_ val=0f bnd=m
52 : __tmp typ=int32_ bnd=m
53 : __tmp typ=bool bnd=m
78 : __cv typ=uint16_ bnd=m
83 : __ct_2 typ=int32_ val=2f bnd=m
86 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
109 : __tmp typ=bool bnd=m
114 : __ct_0S0 typ=int18_ val=0S0 bnd=m
115 : __ct_4 typ=int18_ val=4f bnd=m
118 : __ct_0s0 typ=int18_ val=0s0 bnd=m
122 : __tmp typ=uint3_ bnd=m
127 : __ct_2 typ=uint2_ val=2f bnd=m
137 : __tmp typ=uint3_ bnd=m
141 : __tmp typ=int18_ bnd=m
150 : __either typ=bool bnd=m
151 : __trgt typ=int10_ val=0j bnd=m
152 : __trgt typ=int10_ val=0j bnd=m
153 : __trgt typ=int10_ val=0j bnd=m
154 : __trgt typ=int10_ val=0j bnd=m
155 : __trgt typ=uint16_ val=0j bnd=m
156 : __vcnt typ=uint16_ bnd=m
]
F_Z14cyclic_add_manPiiS_i {
#206 off=0
(__R_SP.24 var=26) st_def () <48>;
(__sp.32 var=34) source () <56>;
(__ct_0.35 var=37) const () <59>;
(__la.37 var=38 stl=LR off=0) inp () <61>;
(__la.38 var=38) deassign (__la.37) <62>;
(pointer.41 var=40 stl=A off=1) inp () <65>;
(pointer.42 var=40) deassign (pointer.41) <66>;
(increment.44 var=41 stl=RA off=0) inp () <68>;
(increment.45 var=41) deassign (increment.44) <69>;
(pointer_start.47 var=42 stl=A off=2) inp () <71>;
(pointer_start.48 var=42) deassign (pointer_start.47) <72>;
(buffer_length.50 var=43 stl=RA off=1) inp () <74>;
(buffer_length.51 var=43) deassign (buffer_length.50) <75>;
(__rd___sp.53 var=36) rd_res_reg (__R_SP.24 __sp.32) <77>;
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.213 __sp.32) <81>;
(__ct_0.64 var=50) const () <88>;
(__tmp.66 var=52) __sint_abs___sint (increment.45) <90>;
(__rt.213 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.297) <264>;
(__ct_0S0.297 var=114) const () <381>;
(__tmp.304 var=122) uint3__cmp_int72__int72_ (__tmp.66 __ct_0.64) <394>;
(__tmp.329 var=53) bool_nplus_uint3_ (__tmp.304) <450>;
(__trgt.336 var=153) const () <468>;
() void_jump_bool_int10_ (__tmp.329 __trgt.336) <469>;
(__either.337 var=150) undefined () <470>;
if {
{
() if_expr (__either.337) <108>;
() chess_frequent_else () <109>;
() chess_rear_then () <471>;
} #5
{
(__trgt.338 var=154) const () <472>;
() void_jump_int10_ (__trgt.338) <473>;
} #18 off=7
{
#154 off=1
(__cv.196 var=78) uint16__uint16____sint (__tmp.66) <234>;
(__ct_2.199 var=83) const () <238>;
(__rt.257 var=86) __Pvoid__pl___Pvoid_int18_ (pointer_start.48 __tmp.310) <320>;
(__ct_4.298 var=115) const () <383>;
(__ct_2.309 var=127) const () <402>;
(__tmp.310 var=141) int72__shift_int72__int72__uint2_ (buffer_length.51 __ct_2.199 __ct_2.309) <403>;
(__trgt.333 var=151) const () <463>;
(__trgt.335 var=152) const () <466>;
(__trgt.339 var=155) const () <474>;
() void_doloop_uint16__uint16_ (__cv.196 __trgt.339) <475>;
(__vcnt.340 var=156) undefined () <476>;
for {
{
(new_pointer.92 var=47) entry (new_pointer.146 pointer.42) <118>;
} #8
{
#223 off=2
(__rt.235 var=86) __Pvoid__pl___Pvoid_int18_ (new_pointer.92 __ct_4.298) <292>;
(__tmp.319 var=137) uint3__cmp_int72__int72_ (__rt.235 __rt.257) <418>;
(__tmp.330 var=109) bool_neg_uint3_ (__tmp.319) <451>;
() void_jump_bool_int10_ (__tmp.330 __trgt.333) <464>;
(__either.334 var=150) undefined () <465>;
if {
{
() if_expr (__either.334) <150>;
} #12
{
} #14 off=4
{
() void_jump_int10_ (__trgt.335) <467>;
} #13 off=3
{
(new_pointer.124 var=47) merge (__rt.235 pointer_start.48) <151>;
} #15
} #11
} #9
{
() for_count (__vcnt.340) <157>;
(new_pointer.146 var=47 new_pointer.147 var=47) exit (new_pointer.124) <166>;
} #17
} #7 rng=[1,65535]
} #6
{
(new_pointer.162 var=47) merge (pointer.42 new_pointer.147) <174>;
} #19
} #4
#21 off=8 nxt=-2
(__rd___sp.165 var=36) rd_res_reg (__R_SP.24 __sp.58) <177>;
(__R_SP.169 var=26 __sp.170 var=34) wr_res_reg (__rt.284 __sp.58) <181>;
() void_ret_dmaddr_ (__la.38) <182>;
(new_pointer.171 var=47 stl=A off=0) assign (new_pointer.162) <183>;
() out (new_pointer.171) <184>;
() sink (__sp.170) <190>;
() sink (__ct_0.35) <192>;
(__rt.284 var=86) __Pvoid__pl___Pvoid_int18_ (__rd___sp.165 __ct_0s0.301) <356>;
(__ct_0s0.301 var=118) const () <389>;
} #0
0 : 'main.c';
----------
0 : (0,31:0,0);
4 : (0,33:8,3);
6 : (0,33:8,4);
7 : (0,33:8,4);
9 : (0,33:47,4);
11 : (0,35:16,7);
13 : (0,35:65,8);
14 : (0,35:16,11);
18 : (0,33:8,18);
21 : (0,39:8,21);
206 : (0,33:8,3);
223 : (0,35:32,7);
----------
77 : (0,31:5,0);
81 : (0,31:5,0);
88 : (0,33:19,0);
90 : (0,33:8,3);
108 : (0,33:8,3);
118 : (0,33:8,4);
150 : (0,35:16,7);
151 : (0,35:16,13);
157 : (0,33:8,16);
166 : (0,33:8,16);
174 : (0,33:8,20);
177 : (0,39:8,0);
181 : (0,39:8,21);
182 : (0,39:8,21);
183 : (0,39:15,0);
238 : (0,35:51,0);
264 : (0,31:5,0);
292 : (0,34:28,5);
320 : (0,35:49,7);
356 : (0,39:8,0);
381 : (0,31:5,0);
383 : (0,34:28,0);
389 : (0,39:8,0);
394 : (0,33:8,3);
402 : (0,35:51,0);
403 : (0,35:51,7);
418 : (0,35:32,7);
450 : (0,33:8,3);
451 : (0,35:32,7);
464 : (0,35:16,7);
469 : (0,33:8,3);
475 : (0,33:8,16);

2
testcode/Release/chesswork/main.ctt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32

5
testcode/Release/chesswork/main.dti
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -114,4 +114,7 @@
__PDMAvoid__ : _basic() __PDMAvoid;
__PDMIOvoid__ : _basic() __PDMIOvoid;
__PPMvoid__ : _basic() __PPMvoid;
__P__sint__ : _pointer() $__Pvoid__ $__sint_DMA;
__P__sint_____P__sint___sint___P__sint___sint__ : _function() $__P__sint__ $__P__sint__ $__sint__ $__P__sint__ $__sint__;
__sint_____sint___sint__ : _function() $__sint__ $__sint__ $__sint__;
__sint____ : _function() $__sint__;

21
testcode/Release/chesswork/main.fnm
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -8,9 +8,22 @@
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\testcode\\main.c"
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\testcode"
"main-9f2435.sfg"
: _main
: "main" global "main.c" 27 Ofile
"main-c9e472.sfg"
: _Z14cyclic_add_manPiiS_i
: "cyclic_add_man" global "main.c" 31 Ofile
(
)
"main-29daee.sfg"
: _Z7max_manii
: "max_man" global "main.c" 41 Ofile
(
)
"main-9f2435.sfg"
: _main
: "main" global "main.c" 44 Ofile
(
_Z7max_manii
)

12
testcode/Release/chesswork/main.gvt
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -12,11 +12,11 @@
8 : _ZL10input_port typ=int8_ val=8388608f bnd=f sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
9 : _ZL11output_port typ=int8_ val=8388624f bnd=f sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
10 : _ZL7pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
11 : _ZL15input_pointer_0 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
12 : _ZL15input_pointer_1 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
13 : _ZL14output_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
14 : _ZL14sample_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
15 : _ZL6sample typ=int8_ bnd=f sz=2 algn=2 stl=DMB tref=int16_t_DMB
11 : i typ=int8_ bnd=g sz=4 algn=4 stl=DMA tref=__sint_DMA
12 : int1 typ=int8_ bnd=g sz=4 algn=4 stl=DMA tref=__sint_DMA
13 : int2 typ=int8_ bnd=g sz=4 algn=4 stl=DMA tref=__sint_DMA
14 : result_1 typ=int8_ bnd=g sz=4 algn=4 stl=DMA tref=__sint_DMA
15 : result_2 typ=int8_ bnd=g sz=4 algn=4 stl=DMA tref=__sint_DMA
]
__main_sttc {
} #0

2
testcode/Release/chesswork/main.gvt.#
View File

@@ -1,7 +1,7 @@
b94f5e81f66808a8f4f9315bd020e05811fb8d4a
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
42695db990e5aaff0b9f36d25938c80e96ce47cc
0f92cd59bc109e3611ddf820c585207cf1996dd2
18875b4f2fe511420bc211eff19c3a32e9473865
da39a3ee5e6b4b0d3255bfef95601890afd80709
da39a3ee5e6b4b0d3255bfef95601890afd80709
0

BIN
testcode/Release/chesswork/main.gvt.o
View File

Binary file not shown.

9
testcode/Release/chesswork/main.ini
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -7,8 +7,5 @@ _ZL12css_cmd_flag/7 $ css_cmd_flag
_ZL10input_port/8 $ input_port
_ZL11output_port/9 $ output_port
_ZL7pointer/10 $ pointer
_ZL15input_pointer_0/11 $ input_pointer_0
_ZL15input_pointer_1/12 $ input_pointer_1
_ZL14output_pointer/13 $ output_pointer
_ZL14sample_pointer/14 $ sample_pointer
_ZL6sample/15 $ sample
int1/12 : #05 #00 #00 #00
int2/13 : #0a #00 #00 #00

22
testcode/Release/chesswork/main.lib
View File

@@ -1,5 +1,5 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
@@ -11,6 +11,26 @@ prop gp_offset_type = ( __sint );
prop static_variable_registers = ( IMSK irq_stat );
// int *cyclic_add_man(int *, int, int *, int)
F_Z14cyclic_add_manPiiS_i : user_defined, called {
fnm : "cyclic_add_man" 'int *cyclic_add_man(int *, int, int *, int)';
arg : ( dmaddr_:i dmaddr_:r dmaddr_:i int32_:i dmaddr_:i int32_:i );
loc : ( LR[0] A[0] A[1] RA[0] A[2] RA[1] );
vac : ( srIM[0] );
frm : ( );
llv : 0 1 0 0 0 ;
}
// int max_man(int, int)
F_Z7max_manii : user_defined, called {
fnm : "max_man" 'int max_man(int, int)';
arg : ( dmaddr_:i int32_:r int32_:i int32_:i );
loc : ( LR[0] RA[0] RA[1] RB[0] );
vac : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// int main()
F_main : user_defined, called {
fnm : "main" 'int main()';

2
testcode/Release/chesswork/main.objlist
View File

@@ -1,2 +1,4 @@
"main-c9e472.o" 5
"main-29daee.o" 0
"main-9f2435.o" 0
"main.gvt.o" 0

10
testcode/Release/chesswork/main.tof
View File

@@ -1,10 +1,16 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 11:30:40 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 22 11:13:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
// per defined called function, table of invoked intrinsic functions (excluding built-in operators):
// int main()
// int *cyclic_add_man(int *, int, int *, int)
int abs(int)
// int max_man(int, int)
// int main()
int max(int, int)