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This commit is contained in:
Patrick Hangl
2026-03-19 16:29:46 +01:00
parent f6fa0ed021
commit 91e62d48e8
76 changed files with 14848 additions and 2074659 deletions
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422
simulation/Release/chesswork/signal_path-43153a.sfg
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@@ -1,7 +1,7 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb 2 16:08:05 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Mar 19 15:18:08 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=16 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
/***
@@ -86,10 +86,10 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
37 : pointer_sample_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
38 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
39 : sample_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
39 : sample_line typ=int8_ bnd=e sz=64 algn=4 stl=DMB tref=__A16DMB__sint_DMB
40 : pointer_coefficient_line typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
41 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
42 : coefficient_line typ=int8_ bnd=e sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
42 : coefficient_line typ=int8_ bnd=e sz=64 algn=8 stl=DMA tref=__A16__sint_DMA
43 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
44 : __extDM_int64_ typ=int8_ bnd=b stl=DM
45 : __extDM_void typ=int8_ bnd=b stl=DM
@@ -122,6 +122,7 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
78 : __ct_0 typ=int32_ val=0f bnd=m
81 : __fch___extDM_int64_ typ=int64_ bnd=m
85 : __fch___extDM_int64_ typ=int64_ bnd=m
86 : __ct_16 typ=int32_ val=16f bnd=m
89 : __fch___extDM_int64_ typ=int64_ bnd=m
93 : __fch___extDM_int64_ typ=int64_ bnd=m
97 : __fch___extDM_int64_ typ=int64_ bnd=m
@@ -149,7 +150,6 @@ F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
146 : __ct_4746794007244308480 typ=int64_ val=4746794007244308480f bnd=m
148 : __tmp typ=int64_ bnd=m
149 : __tmp typ=int32_ bnd=m
150 : __ct_64 typ=int32_ val=64f bnd=m
151 : __ct typ=int32_ bnd=m
152 : _Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii typ=dmaddr_ val=0r bnd=m
154 : __link typ=dmaddr_ bnd=m
@@ -242,13 +242,13 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
(__ct_31.128 var=98) const () <152>;
(_Z20scale_preemph_filterP16SingleSignalPathdddddi.131 var=100) const () <155>;
(__link.133 var=102) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <157>;
(__rt.679 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.94 __ct_0S0.934) <617>;
(__rt.767 var=217) __Pvoid__pl___Pvoid_int18_ (b_c.71 __ct_8.937) <729>;
(__rt.789 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.767 __ct_8.937) <757>;
(__rt.811 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.789 __ct_8.937) <785>;
(__rt.833 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.811 __ct_8.937) <813>;
(__ct_0S0.934 var=248) const () <965>;
(__ct_8.937 var=251) const () <971>;
(__rt.679 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.94 __ct_0S0.934) <615>;
(__rt.767 var=217) __Pvoid__pl___Pvoid_int18_ (b_c.71 __ct_8.937) <727>;
(__rt.789 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.767 __ct_8.937) <755>;
(__rt.811 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.789 __ct_8.937) <783>;
(__rt.833 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.811 __ct_8.937) <811>;
(__ct_0S0.934 var=248) const () <963>;
(__ct_8.937 var=251) const () <969>;
call {
(c_sensor_signal_t.102 var=63 stl=A off=0) assign (c_sensor_signal_t.65) <126>;
(__fch___extDM_int64_.107 var=81 stl=AX off=0) assign (__fch___extDM_int64_.106) <131>;
@@ -286,10 +286,10 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
(__fch___extDM_int64_.226 var=127) load (__M_LDMA.12 __rt.899 __extDM_int64_.196) <198>;
(__fch___extDM_int64_.231 var=131) load (__M_LDMA.12 __rt.921 __extDM_int64_.196) <203>;
(__link.238 var=136) dmaddr__call_dmaddr_ (_Z20scale_preemph_filterP16SingleSignalPathdddddi.131) <210>;
(__rt.855 var=217) __Pvoid__pl___Pvoid_int18_ (b_acc.74 __ct_8.937) <841>;
(__rt.877 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.855 __ct_8.937) <869>;
(__rt.899 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.877 __ct_8.937) <897>;
(__rt.921 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.899 __ct_8.937) <925>;
(__rt.855 var=217) __Pvoid__pl___Pvoid_int18_ (b_acc.74 __ct_8.937) <839>;
(__rt.877 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.855 __ct_8.937) <867>;
(__rt.899 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.877 __ct_8.937) <895>;
(__rt.921 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.899 __ct_8.937) <923>;
call {
(acc_sensor_signal_t.207 var=64 stl=A off=0) assign (acc_sensor_signal_t.68) <179>;
(__fch___extDM_int64_.212 var=115 stl=AX off=0) assign (__fch___extDM_int64_.211) <184>;
@@ -320,37 +320,37 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
} #14 off=11
#474 off=12
(__ct_4746794007244308480.312 var=146) const () <232>;
(_Z11float64_mulyy.954 var=268) const () <1022>;
(__link.955 var=269) dmaddr__call_dmaddr_ (_Z11float64_mulyy.954) <1023>;
(_Z11float64_mulyy.954 var=268) const () <1020>;
(__link.955 var=269) dmaddr__call_dmaddr_ (_Z11float64_mulyy.954) <1021>;
call {
(lms_mu.956 var=71 stl=AX off=1) assign (lms_mu.89) <1024>;
(__a1.957 var=267 stl=BX off=0) assign (__ct_4746794007244308480.312) <1025>;
(__link.958 var=269 stl=LR off=0) assign (__link.955) <1026>;
(__tmp.959 var=271 stl=AX off=0) F_Z11float64_mulyy (__link.958 lms_mu.956 __a1.957) <1027>;
(__tmp.960 var=148) deassign (__tmp.959) <1028>;
(lms_mu.956 var=71 stl=AX off=1) assign (lms_mu.89) <1022>;
(__a1.957 var=267 stl=BX off=0) assign (__ct_4746794007244308480.312) <1023>;
(__link.958 var=269 stl=LR off=0) assign (__link.955) <1024>;
(__tmp.959 var=271 stl=AX off=0) F_Z11float64_mulyy (__link.958 lms_mu.956 __a1.957) <1025>;
(__tmp.960 var=148) deassign (__tmp.959) <1026>;
} #475 off=13
#480 off=14
(_Z30float64_to_int32_round_to_zeroy.963 var=273) const () <1034>;
(__link.964 var=274) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.963) <1035>;
(_Z30float64_to_int32_round_to_zeroy.963 var=273) const () <1032>;
(__link.964 var=274) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.963) <1033>;
call {
(__tmp.965 var=148 stl=AX off=0) assign (__tmp.960) <1036>;
(__link.966 var=274 stl=LR off=0) assign (__link.964) <1037>;
(__tmp.967 var=149 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.966 __tmp.965) <1038>;
(__tmp.968 var=149) deassign (__tmp.967) <1039>;
(__tmp.965 var=148 stl=AX off=0) assign (__tmp.960) <1034>;
(__link.966 var=274 stl=LR off=0) assign (__link.964) <1035>;
(__tmp.967 var=149 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.966 __tmp.965) <1036>;
(__tmp.968 var=149) deassign (__tmp.967) <1037>;
} #481 off=15
#471 off=16
(__ptr_mu.49 var=52) const () <73>;
(__ptr_pointer_sample_line.51 var=54) const () <75>;
(__ptr_sample_line.53 var=56) const () <77>;
(__ct_16.113 var=86) const () <137>;
(__M_WDMA.316 var=11 _ZL2mu.317 var=35) store (__tmp.968 __ptr_mu.49 _ZL2mu.294) <236>;
(__ct_64.321 var=150) const () <240>;
(_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324 var=152) const () <243>;
(__link.326 var=154) dmaddr__call_dmaddr_ (_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324) <245>;
call {
(__ptr_pointer_sample_line.318 var=53 stl=A off=4) assign (__ptr_pointer_sample_line.51) <237>;
(__ptr_sample_line.319 var=55 stl=A off=5) assign (__ptr_sample_line.53) <238>;
(number_coefficients.320 var=72 stl=RA off=1) assign (number_coefficients.92) <239>;
(__ct.323 var=151 stl=RB off=0) assign (__ct_64.321) <242>;
(__ct.323 var=151 stl=RB off=0) assign (__ct_16.113) <242>;
(__link.327 var=154 stl=LR off=0) assign (__link.326) <246>;
(__tmp.328 var=155 stl=RA off=0 _ZL2mu.331 var=35 __extDM.332 var=32 __extDM_BufferPtr.333 var=41 __extDM_BufferPtrDMB.334 var=38 __extDM_SingleSignalPath.335 var=43 __extDM___PDMint32_.336 var=48 __extDM_int32_.337 var=36 __extDM_int64_.338 var=44 __extDM_void.339 var=45 __extPM.340 var=33 __extPM_void.341 var=46 coefficient_line.342 var=42 pointer_coefficient_line.343 var=40 pointer_coefficient_line_ptr_start.344 var=49 pointer_sample_line.345 var=37 pointer_sample_line_ptr_start.346 var=47 sample_line.347 var=39 __vola.348 var=29) F_Z21initialize_buffer_dmbPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii (__link.327 __ptr_pointer_sample_line.318 __ptr_sample_line.319 number_coefficients.320 __ct.323 _ZL2mu.317 __extDM.295 __extDM_BufferPtr.296 __extDM_BufferPtrDMB.297 __extDM_SingleSignalPath.298 __extDM___PDMint32_.299 __extDM_int32_.300 __extDM_int64_.301 __extDM_void.302 __extPM.303 __extPM_void.304 coefficient_line.305 pointer_coefficient_line.306 pointer_coefficient_line_ptr_start.307 pointer_sample_line.308 pointer_sample_line_ptr_start.309 sample_line.310 __vola.311) <247>;
} #16 off=17
@@ -363,52 +363,52 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
(__ptr_pointer_coefficient_line.349 var=57 stl=A off=0) assign (__ptr_pointer_coefficient_line.55) <250>;
(__ptr_coefficient_line.350 var=59 stl=A off=1) assign (__ptr_coefficient_line.57) <251>;
(number_coefficients.351 var=72 stl=RA off=1) assign (number_coefficients.92) <252>;
(__ct.354 var=157 stl=RB off=0) assign (__ct_64.321) <255>;
(__ct.354 var=157 stl=RB off=0) assign (__ct_16.113) <255>;
(__link.358 var=160 stl=LR off=0) assign (__link.357) <259>;
(__tmp.359 var=161 stl=RA off=0 _ZL2mu.362 var=35 __extDM.363 var=32 __extDM_BufferPtr.364 var=41 __extDM_BufferPtrDMB.365 var=38 __extDM_SingleSignalPath.366 var=43 __extDM___PDMint32_.367 var=48 __extDM_int32_.368 var=36 __extDM_int64_.369 var=44 __extDM_void.370 var=45 __extPM.371 var=33 __extPM_void.372 var=46 coefficient_line.373 var=42 pointer_coefficient_line.374 var=40 pointer_coefficient_line_ptr_start.375 var=49 pointer_sample_line.376 var=37 pointer_sample_line_ptr_start.377 var=47 sample_line.378 var=39 __vola.379 var=29) F_Z17initialize_bufferP9BufferPtrPiii (__link.358 __ptr_pointer_coefficient_line.349 __ptr_coefficient_line.350 number_coefficients.351 __ct.354 _ZL2mu.331 __extDM.332 __extDM_BufferPtr.333 __extDM_BufferPtrDMB.334 __extDM_SingleSignalPath.335 __extDM___PDMint32_.336 __extDM_int32_.337 __extDM_int64_.338 __extDM_void.339 __extPM.340 __extPM_void.341 coefficient_line.342 pointer_coefficient_line.343 pointer_coefficient_line_ptr_start.344 pointer_sample_line.345 pointer_sample_line_ptr_start.346 sample_line.347 __vola.348) <260>;
} #18 off=19
#466 off=20
(__ct_0.103 var=78) const () <127>;
(__tmp.947 var=262) uint3__cmp_int72__int72_ (number_coefficients.92 __ct_0.103) <989>;
(__tmp.975 var=164) bool_nplus_uint3_ (__tmp.947) <1098>;
(__trgt.978 var=286) const () <1126>;
() void_jump_bool_int10_ (__tmp.975 __trgt.978) <1127>;
(__either.979 var=285) undefined () <1128>;
(__tmp.947 var=262) uint3__cmp_int72__int72_ (number_coefficients.92 __ct_0.103) <987>;
(__tmp.975 var=164) bool_nplus_uint3_ (__tmp.947) <1096>;
(__trgt.978 var=286) const () <1124>;
() void_jump_bool_int10_ (__tmp.975 __trgt.978) <1125>;
(__either.979 var=285) undefined () <1126>;
if {
{
() if_expr (__either.979) <306>;
() chess_frequent_else () <307>;
() chess_rear_then () <1129>;
() chess_rear_then () <1127>;
} #21
{
(__trgt.980 var=287) const () <1130>;
() void_jump_int10_ (__trgt.980) <1131>;
(__trgt.980 var=287) const () <1128>;
() void_jump_int10_ (__trgt.980) <1129>;
} #27 off=24
{
#34 off=21
(__fch_pointer_sample_line_ptr_start.467 var=170) load (__M_WDMB.10 __ptr_pointer_sample_line__a4.664 pointer_sample_line_ptr_start.377) <352>;
(__fch_pointer_coefficient_line_ptr_start.482 var=180) load (__M_WDMA.9 __ptr_pointer_coefficient_line__a4.665 pointer_coefficient_line_ptr_start.375) <363>;
(__cv.649 var=205) uint16__uint16____sint (number_coefficients.92) <558>;
(__ptr_pointer_sample_line__a4.664 var=213) const () <574>;
(__ptr_pointer_coefficient_line__a4.665 var=214) const () <576>;
(__ct_4.936 var=250) const () <969>;
(__trgt.981 var=288) const () <1132>;
() void_doloop_uint16__uint16_ (__cv.649 __trgt.981) <1133>;
(__vcnt.982 var=289) undefined () <1134>;
(__cv.649 var=205) uint16__uint16____sint (number_coefficients.92) <556>;
(__ptr_pointer_sample_line__a4.664 var=213) const () <572>;
(__ptr_pointer_coefficient_line__a4.665 var=214) const () <574>;
(__ct_4.936 var=250) const () <967>;
(__trgt.981 var=288) const () <1130>;
() void_doloop_uint16__uint16_ (__cv.649 __trgt.981) <1131>;
(__vcnt.982 var=289) undefined () <1132>;
for {
{
(_ZL2mu.429 var=35) entry (_ZL2mu.508 _ZL2mu.362) <314>;
(__extDM_int32_.430 var=36) entry (__extDM_int32_.510 __extDM_int32_.368) <315>;
(sample_line.433 var=39) entry (sample_line.516 sample_line.378) <318>;
(coefficient_line.436 var=42) entry (coefficient_line.522 coefficient_line.373) <321>;
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_pointer_sample_line_ptr_start.467) <545>;
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_pointer_coefficient_line_ptr_start.482) <549>;
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_pointer_sample_line_ptr_start.467) <543>;
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_pointer_coefficient_line_ptr_start.482) <547>;
} #24
{
(__M_WDMB.472 var=12 _ZL2mu.473 var=35 __extDM_int32_.474 var=36 coefficient_line.475 var=42 sample_line.476 var=39) store (__ct_0.103 __iv1_i.635 _ZL2mu.429 __extDM_int32_.430 coefficient_line.436 sample_line.433) <357>;
(__M_WDMA.487 var=11 _ZL2mu.488 var=35 __extDM_int32_.489 var=36 coefficient_line.490 var=42 sample_line.491 var=39) store (__ct_0.103 __iv2_i.640 _ZL2mu.473 __extDM_int32_.474 coefficient_line.475 sample_line.476) <368>;
(__rt.723 var=217) __Pvoid__pl___Pvoid_int18_ (__iv1_i.635 __ct_4.936) <673>;
(__rt.745 var=217) __Pvoid__pl___Pvoid_int18_ (__iv2_i.640 __ct_4.936) <701>;
(__rt.723 var=217) __Pvoid__pl___Pvoid_int18_ (__iv1_i.635 __ct_4.936) <671>;
(__rt.745 var=217) __Pvoid__pl___Pvoid_int18_ (__iv2_i.640 __ct_4.936) <699>;
} #256 off=22
{
() for_count (__vcnt.982) <373>;
@@ -416,8 +416,8 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
(__extDM_int32_.510 var=36 __extDM_int32_.511 var=36) exit (__extDM_int32_.489) <381>;
(sample_line.516 var=39 sample_line.517 var=39) exit (sample_line.491) <384>;
(coefficient_line.522 var=42 coefficient_line.523 var=42) exit (coefficient_line.490) <387>;
(__iv1_i.636 var=201 __iv1_i.637 var=201) exit (__rt.723) <546>;
(__iv2_i.641 var=202 __iv2_i.642 var=202) exit (__rt.745) <550>;
(__iv1_i.636 var=201 __iv1_i.637 var=201) exit (__rt.723) <544>;
(__iv2_i.641 var=202 __iv2_i.642 var=202) exit (__rt.745) <548>;
} #26
} #23 rng=[1,65535]
} #22
@@ -452,166 +452,166 @@ F_Z17initialize_signalP16SingleSignalPathS0_PdS1_iidddi {
() sink (__extDM___PDMint32_.367) <444>;
() sink (pointer_coefficient_line_ptr_start.375) <445>;
() sink (__ct_0.59) <446>;
(__rt.701 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.580 __ct_0s0.935) <645>;
(__ct_0s0.935 var=249) const () <967>;
(__rt.701 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.580 __ct_0s0.935) <643>;
(__ct_0s0.935 var=249) const () <965>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,291:0,0);
4 : (0,306:4,2);
5 : (0,307:33,3);
6 : (0,307:4,3);
7 : (0,308:44,4);
8 : (0,308:4,4);
10 : (0,311:4,5);
11 : (0,312:35,6);
12 : (0,312:4,6);
13 : (0,313:48,7);
14 : (0,313:4,7);
16 : (0,319:4,10);
17 : (0,320:88,11);
18 : (0,320:4,11);
20 : (0,323:4,13);
22 : (0,323:4,14);
23 : (0,323:4,14);
27 : (0,323:4,22);
30 : (0,327:0,25);
256 : (0,323:50,14);
276 : (0,306:4,2);
370 : (0,311:4,5);
466 : (0,323:4,13);
471 : (0,319:4,10);
474 : (0,317:16,9);
475 : (0,317:16,9);
480 : (0,317:7,9);
481 : (0,317:7,9);
0 : (0,294:0,0);
4 : (0,309:4,2);
5 : (0,310:33,3);
6 : (0,310:4,3);
7 : (0,311:44,4);
8 : (0,311:4,4);
10 : (0,314:4,5);
11 : (0,315:35,6);
12 : (0,315:4,6);
13 : (0,316:48,7);
14 : (0,316:4,7);
16 : (0,322:4,10);
17 : (0,323:88,11);
18 : (0,323:4,11);
20 : (0,326:4,13);
22 : (0,326:4,14);
23 : (0,326:4,14);
27 : (0,326:4,22);
30 : (0,330:0,25);
256 : (0,326:50,14);
276 : (0,309:4,2);
370 : (0,314:4,5);
466 : (0,326:4,13);
471 : (0,322:4,10);
474 : (0,320:16,9);
475 : (0,320:16,9);
480 : (0,320:7,9);
481 : (0,320:7,9);
----------
77 : (0,319:48,0);
81 : (0,320:49,0);
118 : (0,291:5,0);
122 : (0,291:5,0);
126 : (0,306:25,0);
127 : (0,306:48,0);
130 : (0,306:47,2);
131 : (0,306:47,0);
135 : (0,306:55,2);
136 : (0,306:55,0);
140 : (0,306:63,2);
141 : (0,306:63,0);
145 : (0,306:71,2);
146 : (0,306:71,0);
150 : (0,306:79,2);
151 : (0,306:79,0);
152 : (0,306:84,0);
154 : (0,306:84,0);
157 : (0,306:4,2);
158 : (0,306:4,0);
159 : (0,306:4,2);
160 : (0,307:14,0);
161 : (0,307:33,0);
164 : (0,307:4,3);
165 : (0,307:4,0);
166 : (0,307:4,3);
169 : (0,308:15,0);
170 : (0,308:34,0);
173 : (0,308:44,0);
176 : (0,308:4,4);
177 : (0,308:4,0);
178 : (0,308:4,4);
179 : (0,311:25,0);
183 : (0,311:51,5);
184 : (0,311:51,0);
188 : (0,311:61,5);
189 : (0,311:61,0);
193 : (0,311:71,5);
194 : (0,311:71,0);
198 : (0,311:81,5);
199 : (0,311:81,0);
203 : (0,311:91,5);
204 : (0,311:91,0);
207 : (0,311:96,0);
210 : (0,311:4,5);
211 : (0,311:4,0);
212 : (0,311:4,5);
213 : (0,312:14,0);
214 : (0,312:35,0);
217 : (0,312:4,6);
218 : (0,312:4,0);
219 : (0,312:4,6);
222 : (0,313:15,0);
223 : (0,313:36,0);
226 : (0,313:48,0);
229 : (0,313:4,7);
230 : (0,313:4,0);
231 : (0,313:4,7);
232 : (0,317:16,0);
236 : (0,317:4,9);
237 : (0,319:26,0);
238 : (0,319:48,0);
239 : (0,319:61,0);
240 : (0,319:82,0);
242 : (0,319:82,0);
245 : (0,319:4,10);
246 : (0,319:4,0);
247 : (0,319:4,10);
250 : (0,320:22,0);
251 : (0,320:49,0);
252 : (0,320:67,0);
255 : (0,320:88,0);
258 : (0,320:4,11);
259 : (0,320:4,0);
260 : (0,320:4,11);
306 : (0,323:4,13);
314 : (0,323:4,14);
315 : (0,323:4,14);
318 : (0,323:4,14);
321 : (0,323:4,14);
352 : (0,324:27,14);
357 : (0,324:37,14);
363 : (0,325:32,15);
368 : (0,325:42,15);
373 : (0,323:4,20);
380 : (0,323:4,20);
381 : (0,323:4,20);
384 : (0,323:4,20);
387 : (0,323:4,20);
413 : (0,323:4,24);
414 : (0,323:4,24);
415 : (0,323:4,24);
416 : (0,323:4,24);
419 : (0,327:0,0);
423 : (0,327:0,25);
424 : (0,327:0,25);
574 : (0,324:27,0);
576 : (0,325:32,0);
617 : (0,291:5,0);
645 : (0,327:0,0);
729 : (0,306:55,0);
757 : (0,306:63,0);
785 : (0,306:71,0);
813 : (0,306:79,0);
841 : (0,311:61,0);
869 : (0,311:71,0);
897 : (0,311:81,0);
925 : (0,311:91,0);
965 : (0,291:5,0);
967 : (0,327:0,0);
971 : (0,306:55,0);
989 : (0,323:4,13);
1022 : (0,317:16,0);
1023 : (0,317:16,9);
1024 : (0,317:16,9);
1025 : (0,317:16,9);
1026 : (0,317:16,9);
1027 : (0,317:16,9);
1028 : (0,317:16,9);
1034 : (0,317:7,0);
1035 : (0,317:7,9);
1036 : (0,317:7,9);
1037 : (0,317:7,9);
1038 : (0,317:7,9);
1039 : (0,317:7,9);
1098 : (0,323:4,13);
1127 : (0,323:4,13);
1133 : (0,323:4,20);
77 : (0,322:48,0);
81 : (0,323:49,0);
118 : (0,294:5,0);
122 : (0,294:5,0);
126 : (0,309:25,0);
127 : (0,309:48,0);
130 : (0,309:47,2);
131 : (0,309:47,0);
135 : (0,309:55,2);
136 : (0,309:55,0);
137 : (0,309:64,0);
140 : (0,309:63,2);
141 : (0,309:63,0);
145 : (0,309:71,2);
146 : (0,309:71,0);
150 : (0,309:79,2);
151 : (0,309:79,0);
152 : (0,309:84,0);
154 : (0,309:84,0);
157 : (0,309:4,2);
158 : (0,309:4,0);
159 : (0,309:4,2);
160 : (0,310:14,0);
161 : (0,310:33,0);
164 : (0,310:4,3);
165 : (0,310:4,0);
166 : (0,310:4,3);
169 : (0,311:15,0);
170 : (0,311:34,0);
173 : (0,311:44,0);
176 : (0,311:4,4);
177 : (0,311:4,0);
178 : (0,311:4,4);
179 : (0,314:25,0);
183 : (0,314:51,5);
184 : (0,314:51,0);
188 : (0,314:61,5);
189 : (0,314:61,0);
193 : (0,314:71,5);
194 : (0,314:71,0);
198 : (0,314:81,5);
199 : (0,314:81,0);
203 : (0,314:91,5);
204 : (0,314:91,0);
207 : (0,314:96,0);
210 : (0,314:4,5);
211 : (0,314:4,0);
212 : (0,314:4,5);
213 : (0,315:14,0);
214 : (0,315:35,0);
217 : (0,315:4,6);
218 : (0,315:4,0);
219 : (0,315:4,6);
222 : (0,316:15,0);
223 : (0,316:36,0);
226 : (0,316:48,0);
229 : (0,316:4,7);
230 : (0,316:4,0);
231 : (0,316:4,7);
232 : (0,320:16,0);
236 : (0,320:4,9);
237 : (0,322:26,0);
238 : (0,322:48,0);
239 : (0,322:61,0);
242 : (0,322:82,0);
245 : (0,322:4,10);
246 : (0,322:4,0);
247 : (0,322:4,10);
250 : (0,323:22,0);
251 : (0,323:49,0);
252 : (0,323:67,0);
255 : (0,323:88,0);
258 : (0,323:4,11);
259 : (0,323:4,0);
260 : (0,323:4,11);
306 : (0,326:4,13);
314 : (0,326:4,14);
315 : (0,326:4,14);
318 : (0,326:4,14);
321 : (0,326:4,14);
352 : (0,327:27,14);
357 : (0,327:37,14);
363 : (0,328:32,15);
368 : (0,328:42,15);
373 : (0,326:4,20);
380 : (0,326:4,20);
381 : (0,326:4,20);
384 : (0,326:4,20);
387 : (0,326:4,20);
413 : (0,326:4,24);
414 : (0,326:4,24);
415 : (0,326:4,24);
416 : (0,326:4,24);
419 : (0,330:0,0);
423 : (0,330:0,25);
424 : (0,330:0,25);
572 : (0,327:27,0);
574 : (0,328:32,0);
615 : (0,294:5,0);
643 : (0,330:0,0);
727 : (0,309:55,0);
755 : (0,309:63,0);
783 : (0,309:71,0);
811 : (0,309:79,0);
839 : (0,314:61,0);
867 : (0,314:71,0);
895 : (0,314:81,0);
923 : (0,314:91,0);
963 : (0,294:5,0);
965 : (0,330:0,0);
969 : (0,309:55,0);
987 : (0,326:4,13);
1020 : (0,320:16,0);
1021 : (0,320:16,9);
1022 : (0,320:16,9);
1023 : (0,320:16,9);
1024 : (0,320:16,9);
1025 : (0,320:16,9);
1026 : (0,320:16,9);
1032 : (0,320:7,0);
1033 : (0,320:7,9);
1034 : (0,320:7,9);
1035 : (0,320:7,9);
1036 : (0,320:7,9);
1037 : (0,320:7,9);
1096 : (0,326:4,13);
1125 : (0,326:4,13);
1131 : (0,326:4,20);