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Patrick Hangl
2026-01-15 13:06:36 +01:00
commit 1935e3d018
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simulation/Release/chesswork/signal_path.ini Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
_ZL7counter/6 $ counter
_ZL2mu/7 $ mu
_ZL4leak/8 $ leak
_ZL4leak/8 : #1d #ac #ff #7f
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre/13 $ c_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre/14 $ acc_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32/15 $ cSensor_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32/16 $ accSensor_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt/17 $ acc_block_filt _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32/18 $ out_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre/19 $ p_c_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre/19 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre #00 #00 #00 #00
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt/20 $ p_acc_block_filt _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt/20 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre #00 #00 #00 #00
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32/21 $ p_out_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32/21 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 #00 #00 #00 #00