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This commit is contained in:
Patrick Hangl
2026-01-15 13:06:36 +01:00
commit 1935e3d018
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simulation/Release/chesswork/signal_path.gvt Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
[
1 : _imsk_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=IMSK tref=uint15__IMSK
2 : _irq_stat_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=irq_stat tref=uint15__irq_stat
3 : ptr_fir_lms_coeffs typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
4 : ptr_fir_lms_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
5 : fir_lms_delay_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
6 : _ZL7counter typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
7 : _ZL2mu typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
8 : _ZL4leak typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
9 : fir_lms_delay_line typ=int8_ bnd=g sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
10 : ptr_fir_lms_delay_line typ=int8_ bnd=g sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
11 : ptr_fir_lms_coeffs typ=int8_ bnd=g sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
12 : fir_lms_coeffs typ=int8_ bnd=g sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
13 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
14 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
15 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
16 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
17 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
18 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
19 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__P__sint_DMA
20 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__P__sint_DMA
21 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sint_DMA
]
__signal_path_sttc {
} #0
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