Projekte angelegt
This commit is contained in:
Patrick Hangl
216
simulation/Release/chesswork/signal_path-f55921.sfg
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216
simulation/Release/chesswork/signal_path-f55921.sfg
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
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// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
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// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
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/***
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!! int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
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F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii : user_defined, called {
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fnm : "sig_init_buffer_DMB" 'int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)';
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arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
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loc : ( LR[0] RA[0] A[4] A[5] RA[1] RB[0] );
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vac : ( srIM[0] );
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frm : ( );
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}
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****
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***/
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[
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0 : _Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii typ=uint20_ bnd=e stl=PM tref=__sint_____PDMBBufferPtrDMB___PDMB__sint___sint___sint__
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12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
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26 : __R_SP typ=dmaddr_ bnd=d stl=SP
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34 : __sp typ=dmaddr_ bnd=b stl=SP
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36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
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37 : __extDM_BufferPtrDMB_buffer_len typ=int8_ bnd=b stl=DM
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38 : __extDM_BufferPtrDMB_ptr_start typ=int8_ bnd=b stl=DM
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40 : __extDM_BufferPtrDMB_ptr_current typ=int8_ bnd=b stl=DM
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41 : __rd___sp typ=dmaddr_ bnd=m
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42 : __ct_0 typ=uint1_ val=0f bnd=m
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43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
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44 : __rt typ=int32_ bnd=p tref=__sint__
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45 : buffer typ=dmaddr_ bnd=p tref=__PDMBBufferPtrDMB__
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46 : buffer_start_add typ=dmaddr_ bnd=p tref=__PDMB__sint__
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47 : length typ=int32_ bnd=p tref=__sint__
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48 : max_buffer_len typ=int32_ bnd=p tref=__sint__
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54 : __ct_0 typ=int32_ val=0f bnd=m
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65 : __tmp typ=bool bnd=m
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72 : __ct_1 typ=int32_ val=1f bnd=m
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76 : __tmp typ=bool bnd=m
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92 : __iv1_i typ=dmaddr_ bnd=m
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95 : __cv typ=uint16_ bnd=m
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103 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
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127 : __ct_0S0 typ=int18_ val=0S0 bnd=m
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128 : __ct_0s0 typ=int18_ val=0s0 bnd=m
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129 : __ct_4 typ=int18_ val=4f bnd=m
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133 : __tmp typ=uint3_ bnd=m
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138 : __tmp typ=uint3_ bnd=m
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148 : __either typ=bool bnd=m
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149 : __trgt typ=int10_ val=0j bnd=m
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150 : __trgt typ=int10_ val=0j bnd=m
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151 : __trgt typ=int10_ val=0j bnd=m
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152 : __trgt typ=int10_ val=0j bnd=m
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153 : __trgt typ=uint16_ val=0j bnd=m
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154 : __vcnt typ=uint16_ bnd=m
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]
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F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii {
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#239 off=0
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(__R_SP.24 var=26) st_def () <48>;
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(__sp.32 var=34) source () <56>;
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(__extDM_int32_.34 var=36) source () <58>;
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(__extDM_BufferPtrDMB_buffer_len.35 var=37) source () <59>;
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(__extDM_BufferPtrDMB_ptr_start.36 var=38) source () <60>;
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(__extDM_BufferPtrDMB_ptr_current.38 var=40) source () <62>;
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(__ct_0.40 var=42) const () <64>;
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(__la.42 var=43 stl=LR off=0) inp () <66>;
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(__la.43 var=43) deassign (__la.42) <67>;
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(buffer.46 var=45 stl=A off=4) inp () <70>;
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(buffer.47 var=45) deassign (buffer.46) <71>;
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(buffer_start_add.49 var=46 stl=A off=5) inp () <73>;
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(buffer_start_add.50 var=46) deassign (buffer_start_add.49) <74>;
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(length.52 var=47 stl=RA off=1) inp () <76>;
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(length.53 var=47) deassign (length.52) <77>;
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(max_buffer_len.55 var=48 stl=RB off=0) inp () <79>;
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(max_buffer_len.56 var=48) deassign (max_buffer_len.55) <80>;
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(__rd___sp.58 var=41) rd_res_reg (__R_SP.24 __sp.32) <82>;
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(__R_SP.62 var=26 __sp.63 var=34) wr_res_reg (__rt.274 __sp.32) <86>;
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(__ct_0.66 var=54) const () <90>;
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(__M_WDMB.69 var=12 __extDM_BufferPtrDMB_buffer_len.70 var=37) store (length.53 buffer.47 __extDM_BufferPtrDMB_buffer_len.35) <93>;
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(__M_WDMB.74 var=12 __extDM_BufferPtrDMB_ptr_start.75 var=38) store (buffer_start_add.50 __rt.340 __extDM_BufferPtrDMB_ptr_start.36) <97>;
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(__M_WDMB.79 var=12 __extDM_BufferPtrDMB_ptr_current.80 var=40) store (buffer_start_add.50 __rt.362 __extDM_BufferPtrDMB_ptr_current.38) <101>;
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(__rt.274 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.58 __ct_0S0.375) <320>;
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(__rt.340 var=103) __Pvoid__pl___Pvoid_int18_ (buffer.47 __ct_4.377) <404>;
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(__rt.362 var=103) __Pvoid__pl___Pvoid_int18_ (__rt.340 __ct_4.377) <432>;
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(__ct_0S0.375 var=127) const () <457>;
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(__ct_4.377 var=129) const () <461>;
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(__tmp.380 var=133) uint3__cmp_int72__int72_ (length.53 __ct_0.66) <466>;
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(__tmp.393 var=65) bool_nplus_uint3_ (__tmp.380) <500>;
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(__trgt.396 var=149) const () <511>;
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() void_jump_bool_int10_ (__tmp.393 __trgt.396) <512>;
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(__either.397 var=148) undefined () <513>;
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if {
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{
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() if_expr (__either.397) <126>;
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() chess_frequent_else () <127>;
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() chess_rear_then () <514>;
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} #5
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{
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(__trgt.398 var=150) const () <515>;
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() void_jump_int10_ (__trgt.398) <516>;
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} #11 off=4
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{
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#30 off=1
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(__cv.254 var=95) uint16__uint16____sint (length.53) <288>;
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(__trgt.402 var=153) const () <522>;
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() void_doloop_uint16__uint16_ (__cv.254 __trgt.402) <523>;
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(__vcnt.403 var=154) undefined () <524>;
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for {
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{
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(__extDM_int32_.112 var=36) entry (__extDM_int32_.152 __extDM_int32_.34) <135>;
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(__extDM_BufferPtrDMB_buffer_len.113 var=37) entry (__extDM_BufferPtrDMB_buffer_len.154 __extDM_BufferPtrDMB_buffer_len.70) <136>;
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(__iv1_i.245 var=92) entry (__iv1_i.246 buffer_start_add.50) <279>;
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} #8
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{
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(__M_WDMB.131 var=12 __extDM_BufferPtrDMB_buffer_len.132 var=37 __extDM_int32_.133 var=36) store (__ct_0.66 __iv1_i.245 __extDM_BufferPtrDMB_buffer_len.113 __extDM_int32_.112) <154>;
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(__rt.318 var=103) __Pvoid__pl___Pvoid_int18_ (__iv1_i.245 __ct_4.377) <376>;
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} #173 off=2
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{
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() for_count (__vcnt.403) <159>;
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(__extDM_int32_.152 var=36 __extDM_int32_.153 var=36) exit (__extDM_int32_.133) <167>;
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(__extDM_BufferPtrDMB_buffer_len.154 var=37 __extDM_BufferPtrDMB_buffer_len.155 var=37) exit (__extDM_BufferPtrDMB_buffer_len.132) <168>;
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(__iv1_i.246 var=92 __iv1_i.247 var=92) exit (__rt.318) <280>;
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} #10
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} #7 rng=[1,65535]
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} #6
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{
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(__extDM_int32_.178 var=36) merge (__extDM_int32_.34 __extDM_int32_.153) <180>;
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(__extDM_BufferPtrDMB_buffer_len.179 var=37) merge (__extDM_BufferPtrDMB_buffer_len.70 __extDM_BufferPtrDMB_buffer_len.155) <181>;
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} #12
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} #4
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#242 off=5
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(__tmp.385 var=138) uint3__cmp_int72__int72_ (length.53 max_buffer_len.56) <474>;
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(__tmp.386 var=76) bool_neg_uint3_ (__tmp.385) <475>;
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(__trgt.399 var=151) const () <517>;
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() void_jump_bool_int10_ (__tmp.386 __trgt.399) <518>;
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(__either.400 var=148) undefined () <519>;
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if {
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{
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() if_expr (__either.400) <205>;
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} #15
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{
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} #16 off=7
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{
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(__ct_1.134 var=72) const () <155>;
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(__trgt.401 var=152) const () <520>;
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() void_jump_int10_ (__trgt.401) <521>;
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} #17 off=6
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{
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(__rt.207 var=44) merge (__ct_0.66 __ct_1.134) <210>;
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} #18
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} #14
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#20 off=8 nxt=-2
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(__rd___sp.208 var=41) rd_res_reg (__R_SP.24 __sp.63) <211>;
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(__R_SP.212 var=26 __sp.213 var=34) wr_res_reg (__rt.296 __sp.63) <215>;
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() void_ret_dmaddr_ (__la.43) <216>;
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(__rt.214 var=44 stl=RA off=0) assign (__rt.207) <217>;
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() out (__rt.214) <218>;
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() sink (__sp.213) <224>;
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() sink (__extDM_int32_.178) <226>;
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() sink (__extDM_BufferPtrDMB_buffer_len.179) <227>;
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() sink (__extDM_BufferPtrDMB_ptr_start.75) <228>;
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() sink (__extDM_BufferPtrDMB_ptr_current.80) <230>;
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() sink (__ct_0.40) <231>;
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(__rt.296 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.208 __ct_0s0.376) <348>;
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(__ct_0s0.376 var=128) const () <459>;
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} #0
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0 : 'signal_processing\\signal_path.c';
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----------
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0 : (0,87:0,0);
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4 : (0,92:4,5);
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6 : (0,92:4,6);
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7 : (0,92:4,6);
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11 : (0,92:4,13);
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14 : (0,95:4,16);
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16 : (0,99:8,17);
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17 : (0,96:8,21);
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20 : (0,95:4,26);
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173 : (0,92:37,6);
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239 : (0,92:4,5);
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242 : (0,95:14,16);
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----------
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82 : (0,87:4,0);
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86 : (0,87:4,0);
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90 : (0,88:10,0);
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93 : (0,88:10,1);
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97 : (0,89:10,2);
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101 : (0,90:10,3);
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126 : (0,92:4,5);
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135 : (0,92:4,6);
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136 : (0,92:4,6);
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154 : (0,93:24,6);
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155 : (0,92:33,0);
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159 : (0,92:4,11);
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167 : (0,92:4,11);
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168 : (0,92:4,11);
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180 : (0,92:4,15);
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181 : (0,92:4,15);
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205 : (0,95:4,16);
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210 : (0,95:4,25);
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211 : (0,95:4,0);
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215 : (0,95:4,26);
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216 : (0,95:4,26);
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217 : (0,95:4,0);
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320 : (0,87:4,0);
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348 : (0,95:4,0);
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404 : (0,89:10,0);
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432 : (0,90:10,0);
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457 : (0,87:4,0);
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459 : (0,95:4,0);
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466 : (0,92:4,5);
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474 : (0,95:14,16);
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475 : (0,95:14,16);
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500 : (0,92:4,5);
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512 : (0,92:4,5);
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518 : (0,95:4,16);
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523 : (0,92:4,11);
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