Projekte angelegt
This commit is contained in:
Patrick Hangl
226
simulation/Release/chesswork/signal_path-a30375.sfg
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226
simulation/Release/chesswork/signal_path-a30375.sfg
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
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// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
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// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
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/***
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!! int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
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F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi : user_defined, called {
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fnm : "sig_delay_buffer_load_and_get" 'int sig_delay_buffer_load_and_get(SingleSignalPath *, int)';
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arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
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loc : ( LR[0] RA[0] A[0] RA[1] );
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vac : ( srIM[0] );
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frm : ( );
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}
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****
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!! void sig_cirular_buffer_ptr_increment(BufferPtr *, int)
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F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri : user_defined, called {
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fnm : "sig_cirular_buffer_ptr_increment" 'void sig_cirular_buffer_ptr_increment(BufferPtr *, int)';
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arg : ( dmaddr_:i dmaddr_:i int32_:i );
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loc : ( LR[0] A[0] RA[0] );
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vac : ( srIM[0] );
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llv : 0 0 0 0 0 ;
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}
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***/
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[
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0 : _Z29sig_delay_buffer_load_and_getP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___2
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11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
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26 : __R_SP typ=dmaddr_ bnd=d stl=SP
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29 : __vola typ=uint20_ bnd=b stl=PM
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32 : __extDM typ=int8_ bnd=b stl=DM
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33 : __extPM typ=uint20_ bnd=b stl=PM
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34 : __sp typ=dmaddr_ bnd=b stl=SP
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35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
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36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
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37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
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38 : __extDM_SingleSignalPath_delay_buffer_buffer_len typ=int8_ bnd=b stl=DM
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39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
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40 : __extDM_SingleSignalPath_delay_buffer_ptr_current typ=int8_ bnd=b stl=DM
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41 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
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42 : __extDM_void typ=int8_ bnd=b stl=DM
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43 : __extPM_void typ=uint20_ bnd=b stl=PM
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44 : __rd___sp typ=dmaddr_ bnd=m
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45 : __ct_0 typ=uint1_ val=0f bnd=m
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46 : __la typ=dmaddr_ bnd=p tref=dmaddr___
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47 : __rt typ=int32_ bnd=p tref=__sint__
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48 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
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49 : x typ=int32_ bnd=p tref=__sint__
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57 : __ct_0 typ=int32_ val=0f bnd=m
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60 : __fch___extDM_SingleSignalPath_delay_buffer_buffer_len typ=int32_ bnd=m
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63 : __tmp typ=bool bnd=m
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70 : __fch___extDM_SingleSignalPath_delay_buffer_ptr_current typ=dmaddr_ bnd=m
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81 : __tmp typ=dmaddr_ bnd=m
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82 : __ct_1 typ=int32_ val=1f bnd=m
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83 : __ct typ=int32_ bnd=m
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84 : _Z32sig_cirular_buffer_ptr_incrementP9BufferPtri typ=dmaddr_ val=0r bnd=m
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86 : __link typ=dmaddr_ bnd=m
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100 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
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124 : __ct_0S0 typ=int18_ val=0S0 bnd=m
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125 : __ct_116 typ=int18_ val=116f bnd=m
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128 : __ct_8 typ=int18_ val=8f bnd=m
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130 : __ct_0s0 typ=int18_ val=0s0 bnd=m
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134 : __tmp typ=uint3_ bnd=m
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144 : __either typ=bool bnd=m
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145 : __trgt typ=int10_ val=0j bnd=m
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146 : __trgt typ=int10_ val=0j bnd=m
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]
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F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi {
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#228 off=0
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(__M_WDMA.9 var=11) st_def () <18>;
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(__R_SP.24 var=26) st_def () <48>;
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(__vola.27 var=29) source () <51>;
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(__extDM.30 var=32) source () <54>;
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(__extPM.31 var=33) source () <55>;
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(__sp.32 var=34) source () <56>;
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(__extDM_SingleSignalPath.33 var=35) source () <57>;
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(__extDM_SingleSignalPath_delay_buffer.34 var=36) source () <58>;
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(__extDM_BufferPtr.35 var=37) source () <59>;
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(__extDM_SingleSignalPath_delay_buffer_buffer_len.36 var=38) source () <60>;
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(__extDM_int32_.37 var=39) source () <61>;
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(__extDM_SingleSignalPath_delay_buffer_ptr_current.38 var=40) source () <62>;
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(__extDM___PDMint32_.39 var=41) source () <63>;
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(__extDM_void.40 var=42) source () <64>;
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(__extPM_void.41 var=43) source () <65>;
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(__ct_0.43 var=45) const () <67>;
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(__la.45 var=46 stl=LR off=0) inp () <69>;
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(__la.46 var=46) deassign (__la.45) <70>;
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(signal.49 var=48 stl=A off=0) inp () <73>;
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(signal.50 var=48) deassign (signal.49) <74>;
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(x.52 var=49 stl=RA off=1) inp () <76>;
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(x.53 var=49) deassign (x.52) <77>;
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(__rd___sp.55 var=44) rd_res_reg (__R_SP.24 __sp.32) <79>;
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(__R_SP.59 var=26 __sp.60 var=34) wr_res_reg (__rt.195 __sp.32) <83>;
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(__ct_0.65 var=57) const () <89>;
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(__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 var=60) load (__M_WDMA.9 __rt.217 __extDM_SingleSignalPath_delay_buffer_buffer_len.36) <92>;
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(__rt.195 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.55 __ct_0S0.296) <259>;
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(__rt.217 var=100) __Pvoid__pl___Pvoid_int18_ (signal.50 __ct_116.297) <287>;
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(__ct_0S0.296 var=124) const () <399>;
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(__ct_116.297 var=125) const () <401>;
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(__tmp.305 var=134) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 __ct_0.65) <416>;
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(__tmp.306 var=63) bool_equal_uint3_ (__tmp.305) <417>;
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(__trgt.314 var=145) const () <457>;
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() void_jump_bool_int10_ (__tmp.306 __trgt.314) <458>;
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(__either.315 var=144) undefined () <459>;
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if {
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{
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() if_expr (__either.315) <116>;
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} #5
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{
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} #6 off=4
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{
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#157 off=1
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(__fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 var=70) load (__M_WDMA.9 __rt.239 __extDM_SingleSignalPath_delay_buffer_ptr_current.38) <124>;
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(__rt.100 var=47) load (__M_WDMA.9 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37) <125>;
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(__M_WDMA.108 var=11 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 var=38 __extDM_int32_.110 var=39) store (x.53 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37) <133>;
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(__ct_1.115 var=82) const () <138>;
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(_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri.118 var=84) const () <141>;
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(__link.120 var=86) dmaddr__call_dmaddr_ (_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri.118) <143>;
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(__rt.239 var=100) __Pvoid__pl___Pvoid_int18_ (__rt.217 __ct_8.300) <315>;
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(__rt.283 var=100) __Pvoid__mi___Pvoid_int18_ (__rt.239 __ct_8.300) <371>;
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(__ct_8.300 var=128) const () <407>;
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call {
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(__tmp.114 var=81 stl=A off=0) assign (__rt.283) <137>;
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(__ct.117 var=83 stl=RA off=0) assign (__ct_1.115) <140>;
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(__link.121 var=86 stl=LR off=0) assign (__link.120) <144>;
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(__extDM.122 var=32 __extDM_BufferPtr.123 var=37 __extDM_SingleSignalPath.124 var=35 __extDM_SingleSignalPath_delay_buffer.125 var=36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126 var=38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127 var=40 __extDM___PDMint32_.128 var=41 __extDM_int32_.129 var=39 __extDM_void.130 var=42 __extPM.131 var=33 __extPM_void.132 var=43 __vola.133 var=29) F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri (__link.121 __tmp.114 __ct.117 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 __extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM___PDMint32_.39 __extDM_int32_.110 __extDM_void.40 __extPM.31 __extPM_void.41 __vola.27) <145>;
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} #9 off=2
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#231 off=3
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(__trgt.316 var=146) const () <460>;
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() void_jump_int10_ (__trgt.316) <461>;
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} #7
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{
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(__vola.134 var=29) merge (__vola.27 __vola.133) <146>;
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(__extDM.135 var=32) merge (__extDM.30 __extDM.122) <147>;
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(__extPM.136 var=33) merge (__extPM.31 __extPM.131) <148>;
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(__extDM_SingleSignalPath.137 var=35) merge (__extDM_SingleSignalPath.33 __extDM_SingleSignalPath.124) <149>;
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(__extDM_SingleSignalPath_delay_buffer.138 var=36) merge (__extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer.125) <150>;
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(__extDM_BufferPtr.139 var=37) merge (__extDM_BufferPtr.35 __extDM_BufferPtr.123) <151>;
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(__extDM_SingleSignalPath_delay_buffer_buffer_len.140 var=38) merge (__extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126) <152>;
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(__extDM_int32_.141 var=39) merge (__extDM_int32_.37 __extDM_int32_.129) <153>;
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(__extDM_SingleSignalPath_delay_buffer_ptr_current.142 var=40) merge (__extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127) <154>;
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(__extDM___PDMint32_.143 var=41) merge (__extDM___PDMint32_.39 __extDM___PDMint32_.128) <155>;
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(__extDM_void.144 var=42) merge (__extDM_void.40 __extDM_void.130) <156>;
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(__extPM_void.145 var=43) merge (__extPM_void.41 __extPM_void.132) <157>;
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(__rt.146 var=47) merge (x.53 __rt.100) <158>;
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} #10
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} #4
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#12 off=5 nxt=-2
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(__rd___sp.148 var=44) rd_res_reg (__R_SP.24 __sp.60) <160>;
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(__R_SP.152 var=26 __sp.153 var=34) wr_res_reg (__rt.261 __sp.60) <164>;
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() void_ret_dmaddr_ (__la.46) <165>;
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(__rt.154 var=47 stl=RA off=0) assign (__rt.146) <166>;
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() out (__rt.154) <167>;
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() sink (__vola.134) <168>;
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() sink (__extDM.135) <171>;
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() sink (__extPM.136) <172>;
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() sink (__sp.153) <173>;
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() sink (__extDM_SingleSignalPath.137) <174>;
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() sink (__extDM_SingleSignalPath_delay_buffer.138) <175>;
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() sink (__extDM_BufferPtr.139) <176>;
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() sink (__extDM_SingleSignalPath_delay_buffer_buffer_len.140) <177>;
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() sink (__extDM_int32_.141) <178>;
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() sink (__extDM_SingleSignalPath_delay_buffer_ptr_current.142) <179>;
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() sink (__extDM___PDMint32_.143) <180>;
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() sink (__extDM_void.144) <181>;
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() sink (__extPM_void.145) <182>;
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() sink (__ct_0.43) <183>;
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(__rt.261 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.148 __ct_0s0.302) <343>;
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(__ct_0s0.302 var=130) const () <411>;
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} #0
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0 : 'signal_processing\\signal_path.c';
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----------
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0 : (0,194:0,0);
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4 : (0,195:4,1);
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6 : (0,195:46,2);
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7 : (0,196:8,5);
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9 : (0,200:4,8);
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12 : (0,201:4,13);
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157 : (0,200:4,8);
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228 : (0,195:40,1);
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----------
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79 : (0,194:4,0);
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83 : (0,194:4,0);
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89 : (0,195:28,0);
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92 : (0,195:28,1);
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116 : (0,195:4,1);
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124 : (0,198:35,6);
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125 : (0,198:14,6);
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133 : (0,199:4,7);
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137 : (0,200:44,0);
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138 : (0,200:60,0);
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140 : (0,200:60,0);
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143 : (0,200:4,8);
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144 : (0,200:4,0);
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145 : (0,200:4,8);
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146 : (0,195:4,12);
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147 : (0,195:4,12);
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148 : (0,195:4,12);
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149 : (0,195:4,12);
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150 : (0,195:4,12);
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151 : (0,195:4,12);
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152 : (0,195:4,12);
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153 : (0,195:4,12);
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154 : (0,195:4,12);
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155 : (0,195:4,12);
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156 : (0,195:4,12);
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157 : (0,195:4,12);
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158 : (0,195:4,12);
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160 : (0,201:4,0);
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164 : (0,201:4,13);
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165 : (0,201:4,13);
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166 : (0,201:4,0);
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259 : (0,194:4,0);
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287 : (0,195:14,1);
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315 : (0,198:35,6);
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343 : (0,201:4,0);
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371 : (0,195:14,0);
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399 : (0,194:4,0);
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401 : (0,195:14,0);
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407 : (0,198:35,0);
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411 : (0,201:4,0);
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416 : (0,195:40,1);
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417 : (0,195:40,1);
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458 : (0,195:4,1);
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