C/DSP_Simulation
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Patrick Hangl
2026-01-15 13:06:36 +01:00
commit 1935e3d018
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simulation/Release/chesswork/main.lib Normal file
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
toolrelease _25R2;
// additional
prop gp_offset_type = ( __sint );
prop static_variable_registers = ( IMSK irq_stat );
// inline assembly void enable_interrupts()
Fvoid_enable_interrupts : user_defined, volatile, assembly {
fnm : "enable_interrupts" 'inline assembly void enable_interrupts()';
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
// inline assembly void core_halt()
Fvoid_core_halt : user_defined, volatile, assembly {
fnm : "core_halt" 'inline assembly void core_halt()';
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
vac : ( srIM[0] );
llv : 0 0 0 0 0 ;
}
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
vac : ( srIM[0] );
}
// void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
vac : ( srIM[0] );
}
// void isr0()
Fisr0 : user_defined, isr, called {
fnm : "isr0" 'void isr0()';
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] srFlags[0] );
svd : ( srIM[0] );
frm : ( );
llv : 0 0 0 0 0 ;
}
// int main()
F_main : user_defined, called {
fnm : "main" 'int main()';
arg : ( dmaddr_:i int32_:r );
loc : ( LR[0] RA[0] );
vac : ( srIM[0] );
frm : ( l=80 b=8 );
llv : 0 4 0 0 0 ;
}