C/DSP_Simulation
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Projekte angelegt

Browse Source
This commit is contained in:
Patrick Hangl
2026-01-15 13:06:36 +01:00
commit 1935e3d018
155 changed files with 23303 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
simulation/Release/chesswork/main-b11aa2.sfg Normal file
View File

@@ -0,0 +1,75 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
/***
!! extern void isr0()
Fisr0 : user_defined, isr, called {
fnm : "isr0" 'void isr0()';
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] srFlags[0] );
svd : ( srIM[0] );
frm : ( );
}
****
***/
[
0 : isr0 typ=uint20_ bnd=e stl=PM tref=void____
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
27 : __R_ILR typ=dmaddr_ bnd=d stl=ILR
30 : __vola typ=uint20_ bnd=b stl=PM
35 : __sp typ=dmaddr_ bnd=b stl=SP
36 : __ila typ=dmaddr_ bnd=b stl=ILR
37 : _ZL15action_required typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
39 : __rd___sp typ=dmaddr_ bnd=m
40 : __rd___ila typ=dmaddr_ bnd=m
42 : __ptr_action_required typ=dmaddr_ val=0a bnd=m adro=37
46 : __ct_1 typ=int32_ val=1f bnd=m
58 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
79 : __ct_0S0 typ=int18_ val=0S0 bnd=m
80 : __ct_0s0 typ=int18_ val=0s0 bnd=m
]
Fisr0 {
(__R_SP.24 var=26) st_def () <48>;
(__R_ILR.25 var=27) st_def () <49>;
(__vola.28 var=30) source () <52>;
(__sp.33 var=35) source () <57>;
(__ila.34 var=36) source () <58>;
(_ZL15action_required.35 var=37) source () <59>;
(__ptr_action_required.39 var=42) const () <63>;
(__rd___sp.41 var=39) rd_res_reg (__R_SP.24 __sp.33) <65>;
(__R_SP.45 var=26 __sp.46 var=35) wr_res_reg (__rt.87 __sp.33) <69>;
(__ct_1.47 var=46) const () <71>;
(__M_WDMA.49 var=11 _ZL15action_required.50 var=37 __vola.51 var=30) store (__ct_1.47 __ptr_action_required.39 _ZL15action_required.35 __vola.28) <73>;
(__rd___sp.52 var=39) rd_res_reg (__R_SP.24 __sp.46) <74>;
(__R_SP.56 var=26 __sp.57 var=35) wr_res_reg (__rt.109 __sp.46) <78>;
(__rd___ila.58 var=40) rd_res_reg (__R_ILR.25 __ila.34) <79>;
() void_reti_dmaddr_ (__rd___ila.58) <80>;
() sink (__vola.51) <81>;
() sink (__sp.57) <86>;
() sink (_ZL15action_required.50) <88>;
(__rt.87 var=58) __Pvoid__pl___Pvoid_int18_ (__rd___sp.41 __ct_0S0.122) <139>;
(__rt.109 var=58) __Pvoid__pl___Pvoid_int18_ (__rd___sp.52 __ct_0s0.123) <167>;
(__ct_0S0.122 var=79) const () <191>;
(__ct_0s0.123 var=80) const () <193>;
} #5 off=0 nxt=-2
0 : 'main.c';
----------
5 : (0,44:1,2);
----------
65 : (0,42:16,0);
69 : (0,42:16,0);
71 : (0,43:19,0);
73 : (0,43:1,1);
74 : (0,44:1,0);
78 : (0,44:1,2);
79 : (0,44:1,0);
80 : (0,44:1,2);
139 : (0,42:16,0);
167 : (0,44:1,0);
191 : (0,42:16,0);
193 : (0,44:1,0);