Projekte angelegt
This commit is contained in:
Patrick Hangl
591
simulation/Release/chesswork/main-9f2435.sfg
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591
simulation/Release/chesswork/main-9f2435.sfg
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
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// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
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// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
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|
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/***
|
||||
!! int main()
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F_main : user_defined, called {
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fnm : "main" 'int main()';
|
||||
arg : ( dmaddr_:i int32_:r );
|
||||
loc : ( LR[0] RA[0] );
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||||
vac : ( srIM[0] );
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||||
frm : ( l=80 b=8 );
|
||||
}
|
||||
****
|
||||
!! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
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F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
|
||||
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
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||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
|
||||
vac : ( srIM[0] );
|
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}
|
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!! void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
|
||||
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
|
||||
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
|
||||
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
|
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vac : ( srIM[0] );
|
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}
|
||||
!! inline assembly inline assembly void enable_interrupts()
|
||||
Fvoid_enable_interrupts : user_defined, volatile, assembly {
|
||||
fnm : "enable_interrupts" 'inline assembly void enable_interrupts()';
|
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flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
|
||||
vac : ( srIM[0] );
|
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llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! inline assembly inline assembly void core_halt()
|
||||
Fvoid_core_halt : user_defined, volatile, assembly {
|
||||
fnm : "core_halt" 'inline assembly void core_halt()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
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vac : ( srIM[0] );
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llv : 0 0 0 0 0 ;
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}
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***/
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|
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[
|
||||
0 : _main typ=uint20_ bnd=e stl=PM tref=__sint____
|
||||
5 : __M_DMIO typ=int8_ bnd=d stl=DMIO
|
||||
8 : __M_SDMB typ=int16_ bnd=d stl=SDMB
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : b0 typ=int8_ val=8t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA
|
||||
36 : b1 typ=int8_ val=48t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA
|
||||
37 : _ZL16corrupted_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
38 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
|
||||
39 : _ZL22reference_noise_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
40 : _ZL14output_pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
41 : __extDM___PDMint16_ typ=int8_ bnd=b stl=DM
|
||||
42 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
43 : __extDM_int16_ typ=int8_ bnd=b stl=DM
|
||||
44 : _ZL14sample_pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
45 : _ZL6sample typ=int8_ bnd=i sz=2 algn=2 stl=DMB tref=int16_t_DMB
|
||||
46 : _ZL15action_required typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
47 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
48 : _ZL12css_cmd_flag typ=int8_ val=12582916f bnd=i sz=1 algn=1 stl=DMIO tref=__uchar_DMIO
|
||||
49 : __extDM_uint8_ typ=int8_ bnd=b stl=DM
|
||||
50 : _ZZ4mainvE4mode typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=OutputMode_DMA
|
||||
51 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
52 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
53 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
54 : __extDM_int64_ typ=int8_ bnd=b stl=DM
|
||||
55 : __rd___sp typ=dmaddr_ bnd=m
|
||||
56 : __ptr_corrupted_signal typ=dmaddr_ bnd=m
|
||||
57 : __ptr_corrupted_signal typ=dmaddr_ val=0a bnd=m adro=37
|
||||
58 : __ptr_reference_noise_signal typ=dmaddr_ bnd=m
|
||||
59 : __ptr_reference_noise_signal typ=dmaddr_ val=0a bnd=m adro=39
|
||||
61 : __ptr_output_pointer typ=dmaddr_ val=0a bnd=m adro=40
|
||||
63 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m
|
||||
65 : __ptr_sample_pointer typ=dmaddr_ val=0a bnd=m adro=44
|
||||
67 : __ptr_sample typ=dmaddr_ val=0a bnd=m adro=45
|
||||
69 : __ptr_action_required typ=dmaddr_ val=0a bnd=m adro=46
|
||||
71 : __ct_12582916 typ=dmaddr_ val=12582916f bnd=m
|
||||
73 : __ptr_mode typ=dmaddr_ val=0a bnd=m adro=50
|
||||
76 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
77 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
82 : __ptr_b0 typ=dmaddr_ bnd=m
|
||||
86 : __ptr_b1 typ=dmaddr_ bnd=m
|
||||
90 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m
|
||||
92 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
95 : __ct_0 typ=uint40_ val=0f bnd=m
|
||||
140 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
141 : __ct typ=int32_ bnd=m
|
||||
143 : __ct typ=int32_ bnd=m
|
||||
144 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m
|
||||
145 : __ct typ=int64_ bnd=m
|
||||
147 : __ct typ=int64_ bnd=m
|
||||
148 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m
|
||||
149 : __ct typ=int64_ bnd=m
|
||||
150 : __ct_64 typ=int32_ val=64f bnd=m
|
||||
151 : __ct typ=int32_ bnd=m
|
||||
152 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
|
||||
154 : __link typ=dmaddr_ bnd=m
|
||||
162 : __ct_2 typ=uint8_ val=2f bnd=m
|
||||
164 : __fch__ZL15action_required typ=int32_ bnd=m
|
||||
165 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
167 : __tmp typ=bool bnd=m
|
||||
168 : __ct_1 typ=uint8_ val=1f bnd=m
|
||||
172 : __fch__ZL14output_pointer typ=dmaddr_ bnd=m
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||||
177 : __tmp typ=dmaddr_ bnd=m
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||||
178 : __fch__ZL14sample_pointer typ=dmaddr_ bnd=m
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||||
179 : __fchtmp typ=int16_ bnd=m
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||||
181 : __fch__ZZ4mainvE4mode typ=int32_ bnd=m
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||||
184 : __tmp typ=dmaddr_ bnd=m
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||||
187 : __tmp typ=dmaddr_ bnd=m
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||||
188 : __fch__ZL14sample_pointer typ=dmaddr_ bnd=m
|
||||
189 : _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=dmaddr_ val=0r bnd=m
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||||
191 : __link typ=dmaddr_ bnd=m
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||||
211 : __ct_4 typ=int18_ val=4f bnd=m
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||||
212 : __ct_8 typ=int18_ val=8f bnd=m
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||||
222 : __ct_8388626 typ=dmaddr_ val=8388626f bnd=m
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||||
223 : __ct_8388610 typ=dmaddr_ val=8388610f bnd=m
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||||
244 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
275 : __ct_m80S0 typ=int18_ val=-88S0 bnd=m
|
||||
278 : __ct_0t0 typ=int18_ val=8t0 bnd=m
|
||||
279 : __ct_40t0 typ=int18_ val=48t0 bnd=m
|
||||
283 : __ct_2 typ=int18_ val=2f bnd=m
|
||||
284 : __ct_8t0 typ=int18_ val=16t0 bnd=m
|
||||
287 : __ct_16t0 typ=int18_ val=24t0 bnd=m
|
||||
290 : __ct_24t0 typ=int18_ val=32t0 bnd=m
|
||||
293 : __ct_32t0 typ=int18_ val=40t0 bnd=m
|
||||
296 : __ct_48t0 typ=int18_ val=56t0 bnd=m
|
||||
299 : __ct_56t0 typ=int18_ val=64t0 bnd=m
|
||||
302 : __ct_64t0 typ=int18_ val=72t0 bnd=m
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||||
305 : __ct_72t0 typ=int18_ val=80t0 bnd=m
|
||||
311 : __tmp typ=uint3_ bnd=m
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||||
319 : __true typ=bool val=1f bnd=m
|
||||
321 : __either typ=bool bnd=m
|
||||
322 : __trgt typ=int10_ val=0j bnd=m
|
||||
323 : __trgt typ=int10_ val=0j bnd=m
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||||
324 : __trgt typ=int10_ val=0j bnd=m
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||||
]
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F_main {
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||||
#250 off=0
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||||
(__M_SDMB.6 var=8) st_def () <12>;
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||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
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||||
(__sp.32 var=34) source () <56>;
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||||
(b0.33 var=35) source () <57>;
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||||
(b1.34 var=36) source () <58>;
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||||
(_ZL16corrupted_signal.35 var=37) source () <59>;
|
||||
(__extDM_SingleSignalPath.36 var=38) source () <60>;
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||||
(_ZL22reference_noise_signal.37 var=39) source () <61>;
|
||||
(_ZL14output_pointer.38 var=40) source () <62>;
|
||||
(__extDM___PDMint16_.39 var=41) source () <63>;
|
||||
(_ZL11output_port.40 var=42) source () <64>;
|
||||
(__extDM_int16_.41 var=43) source () <65>;
|
||||
(_ZL14sample_pointer.42 var=44) source () <66>;
|
||||
(_ZL6sample.43 var=45) source () <67>;
|
||||
(_ZL15action_required.44 var=46) source () <68>;
|
||||
(__extDM_int32_.45 var=47) source () <69>;
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||||
(_ZL12css_cmd_flag.46 var=48) source () <70>;
|
||||
(__extDM_uint8_.47 var=49) source () <71>;
|
||||
(_ZZ4mainvE4mode.48 var=50) source () <72>;
|
||||
(_ZL10input_port.49 var=51) source () <73>;
|
||||
(__extDM_void.50 var=52) source () <74>;
|
||||
(__extPM_void.51 var=53) source () <75>;
|
||||
(__extDM_int64_.52 var=54) source () <76>;
|
||||
(__ptr_corrupted_signal.54 var=57) const () <78>;
|
||||
(__ptr_reference_noise_signal.56 var=59) const () <80>;
|
||||
(__ct_0.77 var=76) const () <101>;
|
||||
(__la.79 var=77 stl=LR off=0) inp () <103>;
|
||||
(__rd___sp.83 var=55) rd_res_reg (__R_SP.24 __sp.32) <107>;
|
||||
(__R_SP.87 var=26 __sp.88 var=34) wr_res_reg (__rt.700 __sp.32) <111>;
|
||||
(__rd___sp.89 var=55) rd_res_reg (__R_SP.24 __sp.88) <113>;
|
||||
(__ct_4604930618986332160.99 var=90) const () <123>;
|
||||
(__M_LDMA.104 var=14 b0.105 var=35) store (__ct_4604930618986332160.99 __rt.722 b0.33) <128>;
|
||||
(__ct_0.106 var=95) const () <129>;
|
||||
(__M_LDMA.111 var=14 b0.112 var=35) store (__ct_0.106 __rt.788 b0.105) <134>;
|
||||
(__M_LDMA.118 var=14 b0.119 var=35) store (__ct_0.106 __rt.810 b0.112) <140>;
|
||||
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_0.106 __rt.832 b0.119) <146>;
|
||||
(__M_LDMA.132 var=14 b0.133 var=35) store (__ct_0.106 __rt.854 b0.126) <152>;
|
||||
(__M_LDMA.139 var=14 b1.140 var=36) store (__ct_4604930618986332160.99 __rt.744 b1.34) <158>;
|
||||
(__M_LDMA.146 var=14 b1.147 var=36) store (__ct_0.106 __rt.876 b1.140) <164>;
|
||||
(__M_LDMA.153 var=14 b1.154 var=36) store (__ct_0.106 __rt.898 b1.147) <170>;
|
||||
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_0.106 __rt.920 b1.154) <176>;
|
||||
(__M_LDMA.167 var=14 b1.168 var=36) store (__ct_0.106 __rt.942 b1.161) <182>;
|
||||
(__ct_2.173 var=140) const () <187>;
|
||||
(__ct_4606281698874543309.179 var=144) const () <193>;
|
||||
(__ct_4576918229304087675.185 var=148) const () <199>;
|
||||
(__ct_64.188 var=150) const () <202>;
|
||||
(_Z4initP16SingleSignalPathS0_PdS1_iidddi.191 var=152) const () <205>;
|
||||
(__link.193 var=154) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.191) <207>;
|
||||
(__rt.700 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.83 __ct_m80S0.955) <789>;
|
||||
(__rt.722 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_0t0.958) <817>;
|
||||
(__rt.744 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_40t0.959) <845>;
|
||||
(__rt.788 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_8t0.964) <901>;
|
||||
(__rt.810 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_16t0.967) <929>;
|
||||
(__rt.832 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_24t0.970) <957>;
|
||||
(__rt.854 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_32t0.973) <985>;
|
||||
(__rt.876 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_48t0.976) <1013>;
|
||||
(__rt.898 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_56t0.979) <1041>;
|
||||
(__rt.920 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_64t0.982) <1069>;
|
||||
(__rt.942 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_72t0.985) <1097>;
|
||||
(__ct_m80S0.955 var=275) const () <1154>;
|
||||
(__ct_0t0.958 var=278) const () <1160>;
|
||||
(__ct_40t0.959 var=279) const () <1162>;
|
||||
(__ct_8t0.964 var=284) const () <1172>;
|
||||
(__ct_16t0.967 var=287) const () <1178>;
|
||||
(__ct_24t0.970 var=290) const () <1184>;
|
||||
(__ct_32t0.973 var=293) const () <1190>;
|
||||
(__ct_48t0.976 var=296) const () <1196>;
|
||||
(__ct_56t0.979 var=299) const () <1202>;
|
||||
(__ct_64t0.982 var=302) const () <1208>;
|
||||
(__ct_72t0.985 var=305) const () <1214>;
|
||||
call {
|
||||
(__ptr_corrupted_signal.169 var=56 stl=A off=0) assign (__ptr_corrupted_signal.54) <183>;
|
||||
(__ptr_reference_noise_signal.170 var=58 stl=A off=1) assign (__ptr_reference_noise_signal.56) <184>;
|
||||
(__ptr_b0.171 var=82 stl=A off=2) assign (__rt.722) <185>;
|
||||
(__ptr_b1.172 var=86 stl=A off=3) assign (__rt.744) <186>;
|
||||
(__ct.175 var=141 stl=RA off=0) assign (__ct_2.173) <189>;
|
||||
(__ct.178 var=143 stl=RA off=1) assign (__ct_2.173) <192>;
|
||||
(__ct.181 var=145 stl=AX off=0) assign (__ct_4606281698874543309.179) <195>;
|
||||
(__ct.184 var=147 stl=AX off=1) assign (__ct_4606281698874543309.179) <198>;
|
||||
(__ct.187 var=149 stl=BX off=0) assign (__ct_4576918229304087675.185) <201>;
|
||||
(__ct.190 var=151 stl=RB off=0) assign (__ct_64.188) <204>;
|
||||
(__link.194 var=154 stl=LR off=0) assign (__link.193) <208>;
|
||||
(_ZL10input_port.195 var=51 _ZL11output_port.196 var=42 _ZL12css_cmd_flag.197 var=48 _ZL14output_pointer.198 var=40 _ZL14sample_pointer.199 var=44 _ZL15action_required.200 var=46 _ZL16corrupted_signal.201 var=37 _ZL22reference_noise_signal.202 var=39 _ZL6sample.203 var=45 __extDM.204 var=32 __extDM_SingleSignalPath.205 var=38 __extDM___PDMint16_.206 var=41 __extDM_int16_.207 var=43 __extDM_int32_.208 var=47 __extDM_int64_.209 var=54 __extDM_uint8_.210 var=49 __extDM_void.211 var=52 __extPM.212 var=33 __extPM_void.213 var=53 b0.214 var=35 b1.215 var=36 __vola.216 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.194 __ptr_corrupted_signal.169 __ptr_reference_noise_signal.170 __ptr_b0.171 __ptr_b1.172 __ct.175 __ct.178 __ct.181 __ct.184 __ct.187 __ct.190 _ZL10input_port.49 _ZL11output_port.40 _ZL12css_cmd_flag.46 _ZL14output_pointer.38 _ZL14sample_pointer.42 _ZL15action_required.44 _ZL16corrupted_signal.35 _ZL22reference_noise_signal.37 _ZL6sample.43 __extDM.30 __extDM_SingleSignalPath.36 __extDM___PDMint16_.39 __extDM_int16_.41 __extDM_int32_.45 __extDM_int64_.52 __extDM_uint8_.47 __extDM_void.50 __extPM.31 __extPM_void.51 b0.133 b1.168 __vola.27) <209>;
|
||||
} #4 off=1
|
||||
call {
|
||||
(__vola.217 var=29) Fvoid_enable_interrupts (__vola.216) <210>;
|
||||
} #5 off=2
|
||||
#6 off=3
|
||||
(__ptr_output_pointer.58 var=61) const () <82>;
|
||||
(__ct_8388624.60 var=63) const () <84>;
|
||||
(__ptr_sample_pointer.63 var=65) const () <87>;
|
||||
(__ptr_sample.65 var=67) const () <89>;
|
||||
(__ptr_action_required.67 var=69) const () <91>;
|
||||
(__ct_12582916.69 var=71) const () <93>;
|
||||
(__ptr_mode.72 var=73) const () <96>;
|
||||
(__ct_0.101 var=92) const () <125>;
|
||||
(__M_WDMA.221 var=11 _ZL14output_pointer.222 var=40) store (__ct_8388626.667 __ptr_output_pointer.58 _ZL14output_pointer.198) <214>;
|
||||
(__M_WDMA.223 var=11 _ZL14sample_pointer.224 var=44) store (__ptr_sample.65 __ptr_sample_pointer.63 _ZL14sample_pointer.199) <215>;
|
||||
(__M_WDMA.227 var=11 _ZL15action_required.228 var=46 __vola.229 var=29) store (__ct_0.101 __ptr_action_required.67 _ZL15action_required.200 __vola.217) <218>;
|
||||
(__ct_2.312 var=162) const () <303>;
|
||||
(__ct_1.321 var=165) const () <308>;
|
||||
(__ct_1.364 var=168) const () <352>;
|
||||
(__fch__ZZ4mainvE4mode.398 var=181) load (__M_WDMA.9 __ptr_mode.72 _ZZ4mainvE4mode.48) <371>;
|
||||
(_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.410 var=189) const () <383>;
|
||||
(__ct_4.623 var=211) const () <633>;
|
||||
(__ct_8.624 var=212) const () <635>;
|
||||
(__ct_8388626.667 var=222) const () <703>;
|
||||
(__ct_8388610.668 var=223) const () <705>;
|
||||
(__ct_2.963 var=283) const () <1170>;
|
||||
(__trgt.1000 var=322) const () <1355>;
|
||||
(__trgt.1002 var=323) const () <1358>;
|
||||
(__trgt.1003 var=324) const () <1360>;
|
||||
do {
|
||||
{
|
||||
(__vola.272 var=29) entry (__vola.460 __vola.229) <263>;
|
||||
(__extDM.275 var=32) entry (__extDM.466 __extDM.204) <266>;
|
||||
(__extPM.276 var=33) entry (__extPM.468 __extPM.212) <267>;
|
||||
(b0.278 var=35) entry (b0.472 b0.214) <269>;
|
||||
(b1.279 var=36) entry (b1.474 b1.215) <270>;
|
||||
(_ZL16corrupted_signal.280 var=37) entry (_ZL16corrupted_signal.476 _ZL16corrupted_signal.201) <271>;
|
||||
(__extDM_SingleSignalPath.281 var=38) entry (__extDM_SingleSignalPath.478 __extDM_SingleSignalPath.205) <272>;
|
||||
(_ZL22reference_noise_signal.282 var=39) entry (_ZL22reference_noise_signal.480 _ZL22reference_noise_signal.202) <273>;
|
||||
(_ZL14output_pointer.283 var=40) entry (_ZL14output_pointer.482 _ZL14output_pointer.222) <274>;
|
||||
(__extDM___PDMint16_.284 var=41) entry (__extDM___PDMint16_.484 __extDM___PDMint16_.206) <275>;
|
||||
(_ZL11output_port.285 var=42) entry (_ZL11output_port.486 _ZL11output_port.196) <276>;
|
||||
(__extDM_int16_.286 var=43) entry (__extDM_int16_.488 __extDM_int16_.207) <277>;
|
||||
(_ZL14sample_pointer.287 var=44) entry (_ZL14sample_pointer.490 _ZL14sample_pointer.224) <278>;
|
||||
(_ZL6sample.288 var=45) entry (_ZL6sample.492 _ZL6sample.203) <279>;
|
||||
(_ZL15action_required.289 var=46) entry (_ZL15action_required.494 _ZL15action_required.228) <280>;
|
||||
(__extDM_int32_.290 var=47) entry (__extDM_int32_.496 __extDM_int32_.208) <281>;
|
||||
(_ZL12css_cmd_flag.291 var=48) entry (_ZL12css_cmd_flag.498 _ZL12css_cmd_flag.197) <282>;
|
||||
(__extDM_uint8_.292 var=49) entry (__extDM_uint8_.500 __extDM_uint8_.210) <283>;
|
||||
(_ZL10input_port.294 var=51) entry (_ZL10input_port.504 _ZL10input_port.195) <285>;
|
||||
(__extDM_void.295 var=52) entry (__extDM_void.506 __extDM_void.211) <286>;
|
||||
(__extPM_void.296 var=53) entry (__extPM_void.508 __extPM_void.213) <287>;
|
||||
(__extDM_int64_.297 var=54) entry (__extDM_int64_.510 __extDM_int64_.209) <288>;
|
||||
} #11
|
||||
{
|
||||
#13 off=4
|
||||
(__M_DMIO.314 var=5 _ZL12css_cmd_flag.315 var=48 __vola.316 var=29) store (__ct_2.312 __ct_12582916.69 _ZL12css_cmd_flag.291 __vola.272) <305>;
|
||||
call {
|
||||
(__vola.317 var=29) Fvoid_core_halt (__vola.316) <306>;
|
||||
} #14 off=5
|
||||
#496 off=6
|
||||
(__fch__ZL15action_required.318 var=164 _ZL15action_required.319 var=46 __vola.320 var=29) load (__M_WDMA.9 __ptr_action_required.67 _ZL15action_required.289 __vola.317) <307>;
|
||||
(__tmp.990 var=311) uint3__cmp_int72__int72_ (__fch__ZL15action_required.318 __ct_1.321) <1223>;
|
||||
(__tmp.997 var=167) bool_nequal_uint3_ (__tmp.990) <1312>;
|
||||
() void_jump_bool_int10_ (__tmp.997 __trgt.1000) <1356>;
|
||||
(__either.1001 var=321) undefined () <1357>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.1001) <351>;
|
||||
} #17
|
||||
{
|
||||
} #21 off=10
|
||||
{
|
||||
#303 off=7
|
||||
(__M_DMIO.366 var=5 _ZL12css_cmd_flag.367 var=48 __vola.368 var=29) store (__ct_1.364 __ct_12582916.69 _ZL12css_cmd_flag.315 __vola.320) <354>;
|
||||
(__M_WDMA.371 var=11 _ZL15action_required.372 var=46 __vola.373 var=29) store (__ct_0.101 __ptr_action_required.67 _ZL15action_required.319 __vola.368) <357>;
|
||||
(__fch__ZL14output_pointer.374 var=172) load (__M_WDMA.9 __ptr_output_pointer.58 _ZL14output_pointer.283) <358>;
|
||||
(__M_WDMA.380 var=11 _ZL14output_pointer.381 var=40) store (__tmp.619 __ptr_output_pointer.58 _ZL14output_pointer.283) <364>;
|
||||
(__fch__ZL14sample_pointer.382 var=178) load (__M_WDMA.9 __ptr_sample_pointer.63 _ZL14sample_pointer.287) <365>;
|
||||
(__fchtmp.383 var=179 _ZL10input_port.384 var=51 _ZL11output_port.385 var=42 _ZL6sample.386 var=45 __extDM_int16_.387 var=43 __vola.388 var=29) load (__M_SDMB.6 __fch__ZL14sample_pointer.382 _ZL10input_port.294 _ZL11output_port.285 _ZL6sample.288 __extDM_int16_.286 __vola.373) <366>;
|
||||
(__M_SDMB.390 var=8 _ZL10input_port.391 var=51 _ZL11output_port.392 var=42 _ZL6sample.393 var=45 __extDM_int16_.394 var=43 __vola.395 var=29) store (__fchtmp.383 __tmp.619 _ZL10input_port.384 _ZL11output_port.385 _ZL6sample.386 __extDM_int16_.387 __vola.388) <368>;
|
||||
(__link.412 var=191) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.410) <385>;
|
||||
(__tmp.619 var=177) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch__ZL14output_pointer.374 __ct_4.623 __ct_8388624.60 __ct_8.624) <593>;
|
||||
(__rt.766 var=244) __Pvoid__mi___Pvoid_int18_ (__ct_8388610.668 __ct_2.963) <873>;
|
||||
call {
|
||||
(__ptr_corrupted_signal.396 var=56 stl=A off=0) assign (__ptr_corrupted_signal.54) <369>;
|
||||
(__ptr_reference_noise_signal.397 var=58 stl=A off=1) assign (__ptr_reference_noise_signal.56) <370>;
|
||||
(__fch__ZZ4mainvE4mode.399 var=181 stl=RA off=0) assign (__fch__ZZ4mainvE4mode.398) <372>;
|
||||
(__tmp.403 var=184 stl=A off=4) assign (__ct_8388610.668) <376>;
|
||||
(__tmp.407 var=187 stl=A off=5) assign (__rt.766) <380>;
|
||||
(__fch__ZL14sample_pointer.409 var=188 stl=__spill_WDMA off=0) assign (__fch__ZL14sample_pointer.382) <382>;
|
||||
(__link.413 var=191 stl=LR off=0) assign (__link.412) <386>;
|
||||
(_ZL10input_port.414 var=51 _ZL11output_port.415 var=42 _ZL12css_cmd_flag.416 var=48 _ZL14output_pointer.417 var=40 _ZL14sample_pointer.418 var=44 _ZL15action_required.419 var=46 _ZL16corrupted_signal.420 var=37 _ZL22reference_noise_signal.421 var=39 _ZL6sample.422 var=45 __extDM.423 var=32 __extDM_SingleSignalPath.424 var=38 __extDM___PDMint16_.425 var=41 __extDM_int16_.426 var=43 __extDM_int32_.427 var=47 __extDM_int64_.428 var=54 __extDM_uint8_.429 var=49 __extDM_void.430 var=52 __extPM.431 var=33 __extPM_void.432 var=53 b0.433 var=35 b1.434 var=36 __vola.435 var=29) F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ (__link.413 __ptr_corrupted_signal.396 __ptr_reference_noise_signal.397 __fch__ZZ4mainvE4mode.399 __tmp.403 __tmp.407 __fch__ZL14sample_pointer.409 _ZL10input_port.391 _ZL11output_port.392 _ZL12css_cmd_flag.367 _ZL14output_pointer.381 _ZL14sample_pointer.287 _ZL15action_required.372 _ZL16corrupted_signal.280 _ZL22reference_noise_signal.282 _ZL6sample.393 __extDM.275 __extDM_SingleSignalPath.281 __extDM___PDMint16_.284 __extDM_int16_.394 __extDM_int32_.290 __extDM_int64_.297 __extDM_uint8_.292 __extDM_void.295 __extPM.276 __extPM_void.296 b0.278 b1.279 __vola.395) <387>;
|
||||
} #20 off=8
|
||||
#499 off=9
|
||||
() void_jump_int10_ (__trgt.1002) <1359>;
|
||||
} #18
|
||||
{
|
||||
(__vola.436 var=29) merge (__vola.320 __vola.435) <388>;
|
||||
(__extDM.437 var=32) merge (__extDM.275 __extDM.423) <389>;
|
||||
(__extPM.438 var=33) merge (__extPM.276 __extPM.431) <390>;
|
||||
(b0.439 var=35) merge (b0.278 b0.433) <391>;
|
||||
(b1.440 var=36) merge (b1.279 b1.434) <392>;
|
||||
(_ZL16corrupted_signal.441 var=37) merge (_ZL16corrupted_signal.280 _ZL16corrupted_signal.420) <393>;
|
||||
(__extDM_SingleSignalPath.442 var=38) merge (__extDM_SingleSignalPath.281 __extDM_SingleSignalPath.424) <394>;
|
||||
(_ZL22reference_noise_signal.443 var=39) merge (_ZL22reference_noise_signal.282 _ZL22reference_noise_signal.421) <395>;
|
||||
(_ZL14output_pointer.444 var=40) merge (_ZL14output_pointer.283 _ZL14output_pointer.417) <396>;
|
||||
(__extDM___PDMint16_.445 var=41) merge (__extDM___PDMint16_.284 __extDM___PDMint16_.425) <397>;
|
||||
(_ZL11output_port.446 var=42) merge (_ZL11output_port.285 _ZL11output_port.415) <398>;
|
||||
(__extDM_int16_.447 var=43) merge (__extDM_int16_.286 __extDM_int16_.426) <399>;
|
||||
(_ZL14sample_pointer.448 var=44) merge (_ZL14sample_pointer.287 _ZL14sample_pointer.418) <400>;
|
||||
(_ZL6sample.449 var=45) merge (_ZL6sample.288 _ZL6sample.422) <401>;
|
||||
(_ZL15action_required.450 var=46) merge (_ZL15action_required.319 _ZL15action_required.419) <402>;
|
||||
(__extDM_int32_.451 var=47) merge (__extDM_int32_.290 __extDM_int32_.427) <403>;
|
||||
(_ZL12css_cmd_flag.452 var=48) merge (_ZL12css_cmd_flag.315 _ZL12css_cmd_flag.416) <404>;
|
||||
(__extDM_uint8_.453 var=49) merge (__extDM_uint8_.292 __extDM_uint8_.429) <405>;
|
||||
(_ZL10input_port.454 var=51) merge (_ZL10input_port.294 _ZL10input_port.414) <406>;
|
||||
(__extDM_void.455 var=52) merge (__extDM_void.295 __extDM_void.430) <407>;
|
||||
(__extPM_void.456 var=53) merge (__extPM_void.296 __extPM_void.432) <408>;
|
||||
(__extDM_int64_.457 var=54) merge (__extDM_int64_.297 __extDM_int64_.428) <409>;
|
||||
} #22
|
||||
} #16
|
||||
#500 off=11
|
||||
() void_jump_int10_ (__trgt.1003) <1361>;
|
||||
(__true.1004 var=319) const () <1362>;
|
||||
} #12
|
||||
{
|
||||
() while_expr (__true.1004) <412>;
|
||||
(__vola.460 var=29 __vola.461 var=29) exit (__vola.436) <413>;
|
||||
(__extDM.466 var=32 __extDM.467 var=32) exit (__extDM.437) <416>;
|
||||
(__extPM.468 var=33 __extPM.469 var=33) exit (__extPM.438) <417>;
|
||||
(b0.472 var=35 b0.473 var=35) exit (b0.439) <419>;
|
||||
(b1.474 var=36 b1.475 var=36) exit (b1.440) <420>;
|
||||
(_ZL16corrupted_signal.476 var=37 _ZL16corrupted_signal.477 var=37) exit (_ZL16corrupted_signal.441) <421>;
|
||||
(__extDM_SingleSignalPath.478 var=38 __extDM_SingleSignalPath.479 var=38) exit (__extDM_SingleSignalPath.442) <422>;
|
||||
(_ZL22reference_noise_signal.480 var=39 _ZL22reference_noise_signal.481 var=39) exit (_ZL22reference_noise_signal.443) <423>;
|
||||
(_ZL14output_pointer.482 var=40 _ZL14output_pointer.483 var=40) exit (_ZL14output_pointer.444) <424>;
|
||||
(__extDM___PDMint16_.484 var=41 __extDM___PDMint16_.485 var=41) exit (__extDM___PDMint16_.445) <425>;
|
||||
(_ZL11output_port.486 var=42 _ZL11output_port.487 var=42) exit (_ZL11output_port.446) <426>;
|
||||
(__extDM_int16_.488 var=43 __extDM_int16_.489 var=43) exit (__extDM_int16_.447) <427>;
|
||||
(_ZL14sample_pointer.490 var=44 _ZL14sample_pointer.491 var=44) exit (_ZL14sample_pointer.448) <428>;
|
||||
(_ZL6sample.492 var=45 _ZL6sample.493 var=45) exit (_ZL6sample.449) <429>;
|
||||
(_ZL15action_required.494 var=46 _ZL15action_required.495 var=46) exit (_ZL15action_required.450) <430>;
|
||||
(__extDM_int32_.496 var=47 __extDM_int32_.497 var=47) exit (__extDM_int32_.451) <431>;
|
||||
(_ZL12css_cmd_flag.498 var=48 _ZL12css_cmd_flag.499 var=48) exit (_ZL12css_cmd_flag.452) <432>;
|
||||
(__extDM_uint8_.500 var=49 __extDM_uint8_.501 var=49) exit (__extDM_uint8_.453) <433>;
|
||||
(_ZL10input_port.504 var=51 _ZL10input_port.505 var=51) exit (_ZL10input_port.454) <435>;
|
||||
(__extDM_void.506 var=52 __extDM_void.507 var=52) exit (__extDM_void.455) <436>;
|
||||
(__extPM_void.508 var=53 __extPM_void.509 var=53) exit (__extPM_void.456) <437>;
|
||||
(__extDM_int64_.510 var=54 __extDM_int64_.511 var=54) exit (__extDM_int64_.457) <438>;
|
||||
} #24
|
||||
} #10 rng=[1,65535]
|
||||
#49 off=12 nxt=-4
|
||||
() sink (__vola.461) <659>;
|
||||
() sink (__extDM.467) <660>;
|
||||
() sink (__extPM.469) <661>;
|
||||
() sink (__sp.88) <662>;
|
||||
() sink (_ZL16corrupted_signal.477) <663>;
|
||||
() sink (__extDM_SingleSignalPath.479) <664>;
|
||||
() sink (_ZL22reference_noise_signal.481) <665>;
|
||||
() sink (_ZL14output_pointer.483) <666>;
|
||||
() sink (__extDM___PDMint16_.485) <667>;
|
||||
() sink (_ZL11output_port.487) <668>;
|
||||
() sink (__extDM_int16_.489) <669>;
|
||||
() sink (_ZL14sample_pointer.491) <670>;
|
||||
() sink (_ZL6sample.493) <671>;
|
||||
() sink (_ZL15action_required.495) <672>;
|
||||
() sink (__extDM_int32_.497) <673>;
|
||||
() sink (_ZL12css_cmd_flag.499) <674>;
|
||||
() sink (__extDM_uint8_.501) <675>;
|
||||
() sink (_ZL10input_port.505) <676>;
|
||||
() sink (__extDM_void.507) <677>;
|
||||
() sink (__extPM_void.509) <678>;
|
||||
() sink (__extDM_int64_.511) <679>;
|
||||
() sink (__ct_0.77) <680>;
|
||||
} #0
|
||||
0 : 'main.c';
|
||||
----------
|
||||
0 : (0,46:0,0);
|
||||
4 : (0,56:4,15);
|
||||
5 : (0,95:8,16);
|
||||
6 : (0,101:8,20);
|
||||
10 : (0,101:8,21);
|
||||
12 : (0,101:17,21);
|
||||
13 : (0,102:25,22);
|
||||
14 : (0,103:12,22);
|
||||
16 : (0,104:12,23);
|
||||
18 : (0,104:38,24);
|
||||
20 : (0,109:16,28);
|
||||
21 : (0,104:12,31);
|
||||
250 : (0,56:4,15);
|
||||
303 : (0,109:16,28);
|
||||
496 : (0,104:32,23);
|
||||
----------
|
||||
84 : (0,96:26,0);
|
||||
107 : (0,46:4,0);
|
||||
111 : (0,46:4,0);
|
||||
113 : (0,51:11,0);
|
||||
123 : (0,51:18,0);
|
||||
125 : (0,51:18,0);
|
||||
128 : (0,51:18,2);
|
||||
129 : (0,51:24,0);
|
||||
134 : (0,51:24,3);
|
||||
140 : (0,51:28,4);
|
||||
146 : (0,51:32,5);
|
||||
152 : (0,51:36,6);
|
||||
158 : (0,52:18,8);
|
||||
164 : (0,52:24,9);
|
||||
170 : (0,52:28,10);
|
||||
176 : (0,52:32,11);
|
||||
182 : (0,52:36,12);
|
||||
183 : (0,57:8,0);
|
||||
184 : (0,57:27,0);
|
||||
185 : (0,58:8,0);
|
||||
186 : (0,59:8,0);
|
||||
187 : (0,60:8,0);
|
||||
189 : (0,60:8,0);
|
||||
192 : (0,61:8,0);
|
||||
193 : (0,62:8,0);
|
||||
195 : (0,62:8,0);
|
||||
198 : (0,63:8,0);
|
||||
199 : (0,64:8,0);
|
||||
201 : (0,64:8,0);
|
||||
202 : (0,65:8,0);
|
||||
204 : (0,65:8,0);
|
||||
207 : (0,56:4,15);
|
||||
208 : (0,56:4,0);
|
||||
209 : (0,56:4,15);
|
||||
210 : (0,95:8,16);
|
||||
214 : (0,96:8,17);
|
||||
215 : (0,97:8,18);
|
||||
218 : (0,100:8,19);
|
||||
263 : (0,101:8,21);
|
||||
266 : (0,101:8,21);
|
||||
267 : (0,101:8,21);
|
||||
269 : (0,101:8,21);
|
||||
270 : (0,101:8,21);
|
||||
271 : (0,101:8,21);
|
||||
272 : (0,101:8,21);
|
||||
273 : (0,101:8,21);
|
||||
274 : (0,101:8,21);
|
||||
275 : (0,101:8,21);
|
||||
276 : (0,101:8,21);
|
||||
277 : (0,101:8,21);
|
||||
278 : (0,101:8,21);
|
||||
279 : (0,101:8,21);
|
||||
280 : (0,101:8,21);
|
||||
281 : (0,101:8,21);
|
||||
282 : (0,101:8,21);
|
||||
283 : (0,101:8,21);
|
||||
285 : (0,101:8,21);
|
||||
286 : (0,101:8,21);
|
||||
287 : (0,101:8,21);
|
||||
288 : (0,101:8,21);
|
||||
303 : (0,102:25,0);
|
||||
305 : (0,102:12,21);
|
||||
306 : (0,103:12,22);
|
||||
307 : (0,104:16,23);
|
||||
308 : (0,104:35,0);
|
||||
351 : (0,104:12,23);
|
||||
352 : (0,105:29,0);
|
||||
354 : (0,105:16,24);
|
||||
357 : (0,106:16,25);
|
||||
358 : (0,107:44,26);
|
||||
364 : (0,107:16,26);
|
||||
365 : (0,108:35,27);
|
||||
366 : (0,108:34,27);
|
||||
368 : (0,108:16,27);
|
||||
369 : (0,109:21,0);
|
||||
370 : (0,109:40,0);
|
||||
371 : (0,109:65,28);
|
||||
372 : (0,109:65,0);
|
||||
376 : (0,109:82,0);
|
||||
380 : (0,109:98,0);
|
||||
382 : (0,109:103,0);
|
||||
385 : (0,109:16,28);
|
||||
386 : (0,109:16,0);
|
||||
387 : (0,109:16,28);
|
||||
388 : (0,104:12,33);
|
||||
389 : (0,104:12,33);
|
||||
390 : (0,104:12,33);
|
||||
391 : (0,104:12,33);
|
||||
392 : (0,104:12,33);
|
||||
393 : (0,104:12,33);
|
||||
394 : (0,104:12,33);
|
||||
395 : (0,104:12,33);
|
||||
396 : (0,104:12,33);
|
||||
397 : (0,104:12,33);
|
||||
398 : (0,104:12,33);
|
||||
399 : (0,104:12,33);
|
||||
400 : (0,104:12,33);
|
||||
401 : (0,104:12,33);
|
||||
402 : (0,104:12,33);
|
||||
403 : (0,104:12,33);
|
||||
404 : (0,104:12,33);
|
||||
405 : (0,104:12,33);
|
||||
406 : (0,104:12,33);
|
||||
407 : (0,104:12,33);
|
||||
408 : (0,104:12,33);
|
||||
409 : (0,104:12,33);
|
||||
412 : (0,101:8,35);
|
||||
413 : (0,101:8,35);
|
||||
416 : (0,101:8,35);
|
||||
417 : (0,101:8,35);
|
||||
419 : (0,101:8,35);
|
||||
420 : (0,101:8,35);
|
||||
421 : (0,101:8,35);
|
||||
422 : (0,101:8,35);
|
||||
423 : (0,101:8,35);
|
||||
424 : (0,101:8,35);
|
||||
425 : (0,101:8,35);
|
||||
426 : (0,101:8,35);
|
||||
427 : (0,101:8,35);
|
||||
428 : (0,101:8,35);
|
||||
429 : (0,101:8,35);
|
||||
430 : (0,101:8,35);
|
||||
431 : (0,101:8,35);
|
||||
432 : (0,101:8,35);
|
||||
433 : (0,101:8,35);
|
||||
435 : (0,101:8,35);
|
||||
436 : (0,101:8,35);
|
||||
437 : (0,101:8,35);
|
||||
438 : (0,101:8,35);
|
||||
593 : (0,107:33,26);
|
||||
633 : (0,107:33,0);
|
||||
635 : (0,107:33,0);
|
||||
703 : (0,96:37,0);
|
||||
705 : (0,109:82,0);
|
||||
789 : (0,46:4,0);
|
||||
817 : (0,51:11,0);
|
||||
845 : (0,52:11,0);
|
||||
901 : (0,51:24,0);
|
||||
929 : (0,51:28,0);
|
||||
957 : (0,51:32,0);
|
||||
985 : (0,51:36,0);
|
||||
1013 : (0,52:24,0);
|
||||
1041 : (0,52:28,0);
|
||||
1069 : (0,52:32,0);
|
||||
1097 : (0,52:36,0);
|
||||
1154 : (0,46:4,0);
|
||||
1160 : (0,51:11,0);
|
||||
1162 : (0,52:11,0);
|
||||
1172 : (0,51:24,0);
|
||||
1178 : (0,51:28,0);
|
||||
1184 : (0,51:32,0);
|
||||
1190 : (0,51:36,0);
|
||||
1196 : (0,52:24,0);
|
||||
1202 : (0,52:28,0);
|
||||
1208 : (0,52:32,0);
|
||||
1214 : (0,52:36,0);
|
||||
1223 : (0,104:32,23);
|
||||
1312 : (0,104:32,23);
|
||||
1356 : (0,104:12,23);
|
||||
1361 : (0,101:8,35);
|
||||
|
||||
Reference in New Issue
Block a user