Projekte angelegt
This commit is contained in:
Patrick Hangl
8
simulation/Release/chesswork/main-2c657d.#
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8
simulation/Release/chesswork/main-2c657d.#
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@@ -0,0 +1,8 @@
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0b3a1439876c35d4e2e78ed4e229a1ffbdca4df3
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b85c95c92e890cf0233f9e50ae029a827db9f04a
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
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1c47baffc25d7adbfe1360500633829beb76d995
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
0
|
||||
0
|
||||
12
simulation/Release/chesswork/main-2c657d.asm
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12
simulation/Release/chesswork/main-2c657d.asm
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@@ -0,0 +1,12 @@
|
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|
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
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.dir 0 "C:\Users\phangl\OneDrive - MED-EL\Desktop\LPDSP32_Modell\lib"
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.text local 1 void_enable_interrupts
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.placeholder
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||||
.src_ref 0 "lpdsp32_irq.h" 47 first
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ie = 1
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.src_ref 0 "lpdsp32_irq.h" 48
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nop
|
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9
simulation/Release/chesswork/main-2c657d.asm.mic
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9
simulation/Release/chesswork/main-2c657d.asm.mic
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@@ -0,0 +1,9 @@
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||||
|
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// File generated by darts version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:47 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\darts.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib +m -g +HC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/elongation -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 main-2c657d.asm -omain-2c657d.asm.mic lpdsp32
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|
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// Release: ipp X-2025.06
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//.text local void_enable_interrupts void_enable_interrupts
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0 1/*first*/ "10111010000100010000" .srcref "%PROCDIR%" "lpdsp32_irq.h" 47 // ie = 1
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1 1/*first*/ "00000000000000000000" .srcref "%PROCDIR%" "lpdsp32_irq.h" 48 // nop
|
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8
simulation/Release/chesswork/main-9f2435.#
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8
simulation/Release/chesswork/main-9f2435.#
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@@ -0,0 +1,8 @@
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466ba9a29dd6732e5048de41303e492793f3e524
|
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842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
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42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
9bc11a5ae02d860ea1a49be9ba20510fbd931a4a
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||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
69cfd8cc3fbe170e72ebc0ce327cc94c5afbcf7b
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46
|
||||
0
|
||||
BIN
simulation/Release/chesswork/main-9f2435.o
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BIN
simulation/Release/chesswork/main-9f2435.o
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Binary file not shown.
591
simulation/Release/chesswork/main-9f2435.sfg
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591
simulation/Release/chesswork/main-9f2435.sfg
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@@ -0,0 +1,591 @@
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||||
|
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// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
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/***
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!! int main()
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F_main : user_defined, called {
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fnm : "main" 'int main()';
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arg : ( dmaddr_:i int32_:r );
|
||||
loc : ( LR[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( l=80 b=8 );
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}
|
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****
|
||||
!! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
|
||||
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
|
||||
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
}
|
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!! void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
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F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
|
||||
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
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||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
|
||||
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
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vac : ( srIM[0] );
|
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}
|
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!! inline assembly inline assembly void enable_interrupts()
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Fvoid_enable_interrupts : user_defined, volatile, assembly {
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fnm : "enable_interrupts" 'inline assembly void enable_interrupts()';
|
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flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! inline assembly inline assembly void core_halt()
|
||||
Fvoid_core_halt : user_defined, volatile, assembly {
|
||||
fnm : "core_halt" 'inline assembly void core_halt()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _main typ=uint20_ bnd=e stl=PM tref=__sint____
|
||||
5 : __M_DMIO typ=int8_ bnd=d stl=DMIO
|
||||
8 : __M_SDMB typ=int16_ bnd=d stl=SDMB
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : b0 typ=int8_ val=8t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA
|
||||
36 : b1 typ=int8_ val=48t0 bnd=a sz=40 algn=8 stl=DMA tref=__A5__fdouble_DMA
|
||||
37 : _ZL16corrupted_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
38 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
|
||||
39 : _ZL22reference_noise_signal typ=int8_ bnd=i sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
40 : _ZL14output_pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
41 : __extDM___PDMint16_ typ=int8_ bnd=b stl=DM
|
||||
42 : _ZL11output_port typ=int8_ val=8388624f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
43 : __extDM_int16_ typ=int8_ bnd=b stl=DM
|
||||
44 : _ZL14sample_pointer typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
45 : _ZL6sample typ=int8_ bnd=i sz=2 algn=2 stl=DMB tref=int16_t_DMB
|
||||
46 : _ZL15action_required typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
47 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
48 : _ZL12css_cmd_flag typ=int8_ val=12582916f bnd=i sz=1 algn=1 stl=DMIO tref=__uchar_DMIO
|
||||
49 : __extDM_uint8_ typ=int8_ bnd=b stl=DM
|
||||
50 : _ZZ4mainvE4mode typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=OutputMode_DMA
|
||||
51 : _ZL10input_port typ=int8_ val=8388608f bnd=i sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
52 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
53 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
54 : __extDM_int64_ typ=int8_ bnd=b stl=DM
|
||||
55 : __rd___sp typ=dmaddr_ bnd=m
|
||||
56 : __ptr_corrupted_signal typ=dmaddr_ bnd=m
|
||||
57 : __ptr_corrupted_signal typ=dmaddr_ val=0a bnd=m adro=37
|
||||
58 : __ptr_reference_noise_signal typ=dmaddr_ bnd=m
|
||||
59 : __ptr_reference_noise_signal typ=dmaddr_ val=0a bnd=m adro=39
|
||||
61 : __ptr_output_pointer typ=dmaddr_ val=0a bnd=m adro=40
|
||||
63 : __ct_8388624 typ=dmaddr_ val=8388624f bnd=m
|
||||
65 : __ptr_sample_pointer typ=dmaddr_ val=0a bnd=m adro=44
|
||||
67 : __ptr_sample typ=dmaddr_ val=0a bnd=m adro=45
|
||||
69 : __ptr_action_required typ=dmaddr_ val=0a bnd=m adro=46
|
||||
71 : __ct_12582916 typ=dmaddr_ val=12582916f bnd=m
|
||||
73 : __ptr_mode typ=dmaddr_ val=0a bnd=m adro=50
|
||||
76 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
77 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
82 : __ptr_b0 typ=dmaddr_ bnd=m
|
||||
86 : __ptr_b1 typ=dmaddr_ bnd=m
|
||||
90 : __ct_4604930618986332160 typ=int64_ val=4604930618986332160f bnd=m
|
||||
92 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
95 : __ct_0 typ=uint40_ val=0f bnd=m
|
||||
140 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
141 : __ct typ=int32_ bnd=m
|
||||
143 : __ct typ=int32_ bnd=m
|
||||
144 : __ct_4606281698874543309 typ=int64_ val=4606281698874543309f bnd=m
|
||||
145 : __ct typ=int64_ bnd=m
|
||||
147 : __ct typ=int64_ bnd=m
|
||||
148 : __ct_4576918229304087675 typ=int64_ val=4576918229304087675f bnd=m
|
||||
149 : __ct typ=int64_ bnd=m
|
||||
150 : __ct_64 typ=int32_ val=64f bnd=m
|
||||
151 : __ct typ=int32_ bnd=m
|
||||
152 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=dmaddr_ val=0r bnd=m
|
||||
154 : __link typ=dmaddr_ bnd=m
|
||||
162 : __ct_2 typ=uint8_ val=2f bnd=m
|
||||
164 : __fch__ZL15action_required typ=int32_ bnd=m
|
||||
165 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
167 : __tmp typ=bool bnd=m
|
||||
168 : __ct_1 typ=uint8_ val=1f bnd=m
|
||||
172 : __fch__ZL14output_pointer typ=dmaddr_ bnd=m
|
||||
177 : __tmp typ=dmaddr_ bnd=m
|
||||
178 : __fch__ZL14sample_pointer typ=dmaddr_ bnd=m
|
||||
179 : __fchtmp typ=int16_ bnd=m
|
||||
181 : __fch__ZZ4mainvE4mode typ=int32_ bnd=m
|
||||
184 : __tmp typ=dmaddr_ bnd=m
|
||||
187 : __tmp typ=dmaddr_ bnd=m
|
||||
188 : __fch__ZL14sample_pointer typ=dmaddr_ bnd=m
|
||||
189 : _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=dmaddr_ val=0r bnd=m
|
||||
191 : __link typ=dmaddr_ bnd=m
|
||||
211 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
212 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
222 : __ct_8388626 typ=dmaddr_ val=8388626f bnd=m
|
||||
223 : __ct_8388610 typ=dmaddr_ val=8388610f bnd=m
|
||||
244 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
275 : __ct_m80S0 typ=int18_ val=-88S0 bnd=m
|
||||
278 : __ct_0t0 typ=int18_ val=8t0 bnd=m
|
||||
279 : __ct_40t0 typ=int18_ val=48t0 bnd=m
|
||||
283 : __ct_2 typ=int18_ val=2f bnd=m
|
||||
284 : __ct_8t0 typ=int18_ val=16t0 bnd=m
|
||||
287 : __ct_16t0 typ=int18_ val=24t0 bnd=m
|
||||
290 : __ct_24t0 typ=int18_ val=32t0 bnd=m
|
||||
293 : __ct_32t0 typ=int18_ val=40t0 bnd=m
|
||||
296 : __ct_48t0 typ=int18_ val=56t0 bnd=m
|
||||
299 : __ct_56t0 typ=int18_ val=64t0 bnd=m
|
||||
302 : __ct_64t0 typ=int18_ val=72t0 bnd=m
|
||||
305 : __ct_72t0 typ=int18_ val=80t0 bnd=m
|
||||
311 : __tmp typ=uint3_ bnd=m
|
||||
319 : __true typ=bool val=1f bnd=m
|
||||
321 : __either typ=bool bnd=m
|
||||
322 : __trgt typ=int10_ val=0j bnd=m
|
||||
323 : __trgt typ=int10_ val=0j bnd=m
|
||||
324 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_main {
|
||||
#250 off=0
|
||||
(__M_SDMB.6 var=8) st_def () <12>;
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(b0.33 var=35) source () <57>;
|
||||
(b1.34 var=36) source () <58>;
|
||||
(_ZL16corrupted_signal.35 var=37) source () <59>;
|
||||
(__extDM_SingleSignalPath.36 var=38) source () <60>;
|
||||
(_ZL22reference_noise_signal.37 var=39) source () <61>;
|
||||
(_ZL14output_pointer.38 var=40) source () <62>;
|
||||
(__extDM___PDMint16_.39 var=41) source () <63>;
|
||||
(_ZL11output_port.40 var=42) source () <64>;
|
||||
(__extDM_int16_.41 var=43) source () <65>;
|
||||
(_ZL14sample_pointer.42 var=44) source () <66>;
|
||||
(_ZL6sample.43 var=45) source () <67>;
|
||||
(_ZL15action_required.44 var=46) source () <68>;
|
||||
(__extDM_int32_.45 var=47) source () <69>;
|
||||
(_ZL12css_cmd_flag.46 var=48) source () <70>;
|
||||
(__extDM_uint8_.47 var=49) source () <71>;
|
||||
(_ZZ4mainvE4mode.48 var=50) source () <72>;
|
||||
(_ZL10input_port.49 var=51) source () <73>;
|
||||
(__extDM_void.50 var=52) source () <74>;
|
||||
(__extPM_void.51 var=53) source () <75>;
|
||||
(__extDM_int64_.52 var=54) source () <76>;
|
||||
(__ptr_corrupted_signal.54 var=57) const () <78>;
|
||||
(__ptr_reference_noise_signal.56 var=59) const () <80>;
|
||||
(__ct_0.77 var=76) const () <101>;
|
||||
(__la.79 var=77 stl=LR off=0) inp () <103>;
|
||||
(__rd___sp.83 var=55) rd_res_reg (__R_SP.24 __sp.32) <107>;
|
||||
(__R_SP.87 var=26 __sp.88 var=34) wr_res_reg (__rt.700 __sp.32) <111>;
|
||||
(__rd___sp.89 var=55) rd_res_reg (__R_SP.24 __sp.88) <113>;
|
||||
(__ct_4604930618986332160.99 var=90) const () <123>;
|
||||
(__M_LDMA.104 var=14 b0.105 var=35) store (__ct_4604930618986332160.99 __rt.722 b0.33) <128>;
|
||||
(__ct_0.106 var=95) const () <129>;
|
||||
(__M_LDMA.111 var=14 b0.112 var=35) store (__ct_0.106 __rt.788 b0.105) <134>;
|
||||
(__M_LDMA.118 var=14 b0.119 var=35) store (__ct_0.106 __rt.810 b0.112) <140>;
|
||||
(__M_LDMA.125 var=14 b0.126 var=35) store (__ct_0.106 __rt.832 b0.119) <146>;
|
||||
(__M_LDMA.132 var=14 b0.133 var=35) store (__ct_0.106 __rt.854 b0.126) <152>;
|
||||
(__M_LDMA.139 var=14 b1.140 var=36) store (__ct_4604930618986332160.99 __rt.744 b1.34) <158>;
|
||||
(__M_LDMA.146 var=14 b1.147 var=36) store (__ct_0.106 __rt.876 b1.140) <164>;
|
||||
(__M_LDMA.153 var=14 b1.154 var=36) store (__ct_0.106 __rt.898 b1.147) <170>;
|
||||
(__M_LDMA.160 var=14 b1.161 var=36) store (__ct_0.106 __rt.920 b1.154) <176>;
|
||||
(__M_LDMA.167 var=14 b1.168 var=36) store (__ct_0.106 __rt.942 b1.161) <182>;
|
||||
(__ct_2.173 var=140) const () <187>;
|
||||
(__ct_4606281698874543309.179 var=144) const () <193>;
|
||||
(__ct_4576918229304087675.185 var=148) const () <199>;
|
||||
(__ct_64.188 var=150) const () <202>;
|
||||
(_Z4initP16SingleSignalPathS0_PdS1_iidddi.191 var=152) const () <205>;
|
||||
(__link.193 var=154) dmaddr__call_dmaddr_ (_Z4initP16SingleSignalPathS0_PdS1_iidddi.191) <207>;
|
||||
(__rt.700 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.83 __ct_m80S0.955) <789>;
|
||||
(__rt.722 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_0t0.958) <817>;
|
||||
(__rt.744 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_40t0.959) <845>;
|
||||
(__rt.788 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_8t0.964) <901>;
|
||||
(__rt.810 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_16t0.967) <929>;
|
||||
(__rt.832 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_24t0.970) <957>;
|
||||
(__rt.854 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_32t0.973) <985>;
|
||||
(__rt.876 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_48t0.976) <1013>;
|
||||
(__rt.898 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_56t0.979) <1041>;
|
||||
(__rt.920 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_64t0.982) <1069>;
|
||||
(__rt.942 var=244) __Pvoid__pl___Pvoid_int18_ (__rd___sp.89 __ct_72t0.985) <1097>;
|
||||
(__ct_m80S0.955 var=275) const () <1154>;
|
||||
(__ct_0t0.958 var=278) const () <1160>;
|
||||
(__ct_40t0.959 var=279) const () <1162>;
|
||||
(__ct_8t0.964 var=284) const () <1172>;
|
||||
(__ct_16t0.967 var=287) const () <1178>;
|
||||
(__ct_24t0.970 var=290) const () <1184>;
|
||||
(__ct_32t0.973 var=293) const () <1190>;
|
||||
(__ct_48t0.976 var=296) const () <1196>;
|
||||
(__ct_56t0.979 var=299) const () <1202>;
|
||||
(__ct_64t0.982 var=302) const () <1208>;
|
||||
(__ct_72t0.985 var=305) const () <1214>;
|
||||
call {
|
||||
(__ptr_corrupted_signal.169 var=56 stl=A off=0) assign (__ptr_corrupted_signal.54) <183>;
|
||||
(__ptr_reference_noise_signal.170 var=58 stl=A off=1) assign (__ptr_reference_noise_signal.56) <184>;
|
||||
(__ptr_b0.171 var=82 stl=A off=2) assign (__rt.722) <185>;
|
||||
(__ptr_b1.172 var=86 stl=A off=3) assign (__rt.744) <186>;
|
||||
(__ct.175 var=141 stl=RA off=0) assign (__ct_2.173) <189>;
|
||||
(__ct.178 var=143 stl=RA off=1) assign (__ct_2.173) <192>;
|
||||
(__ct.181 var=145 stl=AX off=0) assign (__ct_4606281698874543309.179) <195>;
|
||||
(__ct.184 var=147 stl=AX off=1) assign (__ct_4606281698874543309.179) <198>;
|
||||
(__ct.187 var=149 stl=BX off=0) assign (__ct_4576918229304087675.185) <201>;
|
||||
(__ct.190 var=151 stl=RB off=0) assign (__ct_64.188) <204>;
|
||||
(__link.194 var=154 stl=LR off=0) assign (__link.193) <208>;
|
||||
(_ZL10input_port.195 var=51 _ZL11output_port.196 var=42 _ZL12css_cmd_flag.197 var=48 _ZL14output_pointer.198 var=40 _ZL14sample_pointer.199 var=44 _ZL15action_required.200 var=46 _ZL16corrupted_signal.201 var=37 _ZL22reference_noise_signal.202 var=39 _ZL6sample.203 var=45 __extDM.204 var=32 __extDM_SingleSignalPath.205 var=38 __extDM___PDMint16_.206 var=41 __extDM_int16_.207 var=43 __extDM_int32_.208 var=47 __extDM_int64_.209 var=54 __extDM_uint8_.210 var=49 __extDM_void.211 var=52 __extPM.212 var=33 __extPM_void.213 var=53 b0.214 var=35 b1.215 var=36 __vola.216 var=29) F_Z4initP16SingleSignalPathS0_PdS1_iidddi (__link.194 __ptr_corrupted_signal.169 __ptr_reference_noise_signal.170 __ptr_b0.171 __ptr_b1.172 __ct.175 __ct.178 __ct.181 __ct.184 __ct.187 __ct.190 _ZL10input_port.49 _ZL11output_port.40 _ZL12css_cmd_flag.46 _ZL14output_pointer.38 _ZL14sample_pointer.42 _ZL15action_required.44 _ZL16corrupted_signal.35 _ZL22reference_noise_signal.37 _ZL6sample.43 __extDM.30 __extDM_SingleSignalPath.36 __extDM___PDMint16_.39 __extDM_int16_.41 __extDM_int32_.45 __extDM_int64_.52 __extDM_uint8_.47 __extDM_void.50 __extPM.31 __extPM_void.51 b0.133 b1.168 __vola.27) <209>;
|
||||
} #4 off=1
|
||||
call {
|
||||
(__vola.217 var=29) Fvoid_enable_interrupts (__vola.216) <210>;
|
||||
} #5 off=2
|
||||
#6 off=3
|
||||
(__ptr_output_pointer.58 var=61) const () <82>;
|
||||
(__ct_8388624.60 var=63) const () <84>;
|
||||
(__ptr_sample_pointer.63 var=65) const () <87>;
|
||||
(__ptr_sample.65 var=67) const () <89>;
|
||||
(__ptr_action_required.67 var=69) const () <91>;
|
||||
(__ct_12582916.69 var=71) const () <93>;
|
||||
(__ptr_mode.72 var=73) const () <96>;
|
||||
(__ct_0.101 var=92) const () <125>;
|
||||
(__M_WDMA.221 var=11 _ZL14output_pointer.222 var=40) store (__ct_8388626.667 __ptr_output_pointer.58 _ZL14output_pointer.198) <214>;
|
||||
(__M_WDMA.223 var=11 _ZL14sample_pointer.224 var=44) store (__ptr_sample.65 __ptr_sample_pointer.63 _ZL14sample_pointer.199) <215>;
|
||||
(__M_WDMA.227 var=11 _ZL15action_required.228 var=46 __vola.229 var=29) store (__ct_0.101 __ptr_action_required.67 _ZL15action_required.200 __vola.217) <218>;
|
||||
(__ct_2.312 var=162) const () <303>;
|
||||
(__ct_1.321 var=165) const () <308>;
|
||||
(__ct_1.364 var=168) const () <352>;
|
||||
(__fch__ZZ4mainvE4mode.398 var=181) load (__M_WDMA.9 __ptr_mode.72 _ZZ4mainvE4mode.48) <371>;
|
||||
(_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.410 var=189) const () <383>;
|
||||
(__ct_4.623 var=211) const () <633>;
|
||||
(__ct_8.624 var=212) const () <635>;
|
||||
(__ct_8388626.667 var=222) const () <703>;
|
||||
(__ct_8388610.668 var=223) const () <705>;
|
||||
(__ct_2.963 var=283) const () <1170>;
|
||||
(__trgt.1000 var=322) const () <1355>;
|
||||
(__trgt.1002 var=323) const () <1358>;
|
||||
(__trgt.1003 var=324) const () <1360>;
|
||||
do {
|
||||
{
|
||||
(__vola.272 var=29) entry (__vola.460 __vola.229) <263>;
|
||||
(__extDM.275 var=32) entry (__extDM.466 __extDM.204) <266>;
|
||||
(__extPM.276 var=33) entry (__extPM.468 __extPM.212) <267>;
|
||||
(b0.278 var=35) entry (b0.472 b0.214) <269>;
|
||||
(b1.279 var=36) entry (b1.474 b1.215) <270>;
|
||||
(_ZL16corrupted_signal.280 var=37) entry (_ZL16corrupted_signal.476 _ZL16corrupted_signal.201) <271>;
|
||||
(__extDM_SingleSignalPath.281 var=38) entry (__extDM_SingleSignalPath.478 __extDM_SingleSignalPath.205) <272>;
|
||||
(_ZL22reference_noise_signal.282 var=39) entry (_ZL22reference_noise_signal.480 _ZL22reference_noise_signal.202) <273>;
|
||||
(_ZL14output_pointer.283 var=40) entry (_ZL14output_pointer.482 _ZL14output_pointer.222) <274>;
|
||||
(__extDM___PDMint16_.284 var=41) entry (__extDM___PDMint16_.484 __extDM___PDMint16_.206) <275>;
|
||||
(_ZL11output_port.285 var=42) entry (_ZL11output_port.486 _ZL11output_port.196) <276>;
|
||||
(__extDM_int16_.286 var=43) entry (__extDM_int16_.488 __extDM_int16_.207) <277>;
|
||||
(_ZL14sample_pointer.287 var=44) entry (_ZL14sample_pointer.490 _ZL14sample_pointer.224) <278>;
|
||||
(_ZL6sample.288 var=45) entry (_ZL6sample.492 _ZL6sample.203) <279>;
|
||||
(_ZL15action_required.289 var=46) entry (_ZL15action_required.494 _ZL15action_required.228) <280>;
|
||||
(__extDM_int32_.290 var=47) entry (__extDM_int32_.496 __extDM_int32_.208) <281>;
|
||||
(_ZL12css_cmd_flag.291 var=48) entry (_ZL12css_cmd_flag.498 _ZL12css_cmd_flag.197) <282>;
|
||||
(__extDM_uint8_.292 var=49) entry (__extDM_uint8_.500 __extDM_uint8_.210) <283>;
|
||||
(_ZL10input_port.294 var=51) entry (_ZL10input_port.504 _ZL10input_port.195) <285>;
|
||||
(__extDM_void.295 var=52) entry (__extDM_void.506 __extDM_void.211) <286>;
|
||||
(__extPM_void.296 var=53) entry (__extPM_void.508 __extPM_void.213) <287>;
|
||||
(__extDM_int64_.297 var=54) entry (__extDM_int64_.510 __extDM_int64_.209) <288>;
|
||||
} #11
|
||||
{
|
||||
#13 off=4
|
||||
(__M_DMIO.314 var=5 _ZL12css_cmd_flag.315 var=48 __vola.316 var=29) store (__ct_2.312 __ct_12582916.69 _ZL12css_cmd_flag.291 __vola.272) <305>;
|
||||
call {
|
||||
(__vola.317 var=29) Fvoid_core_halt (__vola.316) <306>;
|
||||
} #14 off=5
|
||||
#496 off=6
|
||||
(__fch__ZL15action_required.318 var=164 _ZL15action_required.319 var=46 __vola.320 var=29) load (__M_WDMA.9 __ptr_action_required.67 _ZL15action_required.289 __vola.317) <307>;
|
||||
(__tmp.990 var=311) uint3__cmp_int72__int72_ (__fch__ZL15action_required.318 __ct_1.321) <1223>;
|
||||
(__tmp.997 var=167) bool_nequal_uint3_ (__tmp.990) <1312>;
|
||||
() void_jump_bool_int10_ (__tmp.997 __trgt.1000) <1356>;
|
||||
(__either.1001 var=321) undefined () <1357>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.1001) <351>;
|
||||
} #17
|
||||
{
|
||||
} #21 off=10
|
||||
{
|
||||
#303 off=7
|
||||
(__M_DMIO.366 var=5 _ZL12css_cmd_flag.367 var=48 __vola.368 var=29) store (__ct_1.364 __ct_12582916.69 _ZL12css_cmd_flag.315 __vola.320) <354>;
|
||||
(__M_WDMA.371 var=11 _ZL15action_required.372 var=46 __vola.373 var=29) store (__ct_0.101 __ptr_action_required.67 _ZL15action_required.319 __vola.368) <357>;
|
||||
(__fch__ZL14output_pointer.374 var=172) load (__M_WDMA.9 __ptr_output_pointer.58 _ZL14output_pointer.283) <358>;
|
||||
(__M_WDMA.380 var=11 _ZL14output_pointer.381 var=40) store (__tmp.619 __ptr_output_pointer.58 _ZL14output_pointer.283) <364>;
|
||||
(__fch__ZL14sample_pointer.382 var=178) load (__M_WDMA.9 __ptr_sample_pointer.63 _ZL14sample_pointer.287) <365>;
|
||||
(__fchtmp.383 var=179 _ZL10input_port.384 var=51 _ZL11output_port.385 var=42 _ZL6sample.386 var=45 __extDM_int16_.387 var=43 __vola.388 var=29) load (__M_SDMB.6 __fch__ZL14sample_pointer.382 _ZL10input_port.294 _ZL11output_port.285 _ZL6sample.288 __extDM_int16_.286 __vola.373) <366>;
|
||||
(__M_SDMB.390 var=8 _ZL10input_port.391 var=51 _ZL11output_port.392 var=42 _ZL6sample.393 var=45 __extDM_int16_.394 var=43 __vola.395 var=29) store (__fchtmp.383 __tmp.619 _ZL10input_port.384 _ZL11output_port.385 _ZL6sample.386 __extDM_int16_.387 __vola.388) <368>;
|
||||
(__link.412 var=191) dmaddr__call_dmaddr_ (_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.410) <385>;
|
||||
(__tmp.619 var=177) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch__ZL14output_pointer.374 __ct_4.623 __ct_8388624.60 __ct_8.624) <593>;
|
||||
(__rt.766 var=244) __Pvoid__mi___Pvoid_int18_ (__ct_8388610.668 __ct_2.963) <873>;
|
||||
call {
|
||||
(__ptr_corrupted_signal.396 var=56 stl=A off=0) assign (__ptr_corrupted_signal.54) <369>;
|
||||
(__ptr_reference_noise_signal.397 var=58 stl=A off=1) assign (__ptr_reference_noise_signal.56) <370>;
|
||||
(__fch__ZZ4mainvE4mode.399 var=181 stl=RA off=0) assign (__fch__ZZ4mainvE4mode.398) <372>;
|
||||
(__tmp.403 var=184 stl=A off=4) assign (__ct_8388610.668) <376>;
|
||||
(__tmp.407 var=187 stl=A off=5) assign (__rt.766) <380>;
|
||||
(__fch__ZL14sample_pointer.409 var=188 stl=__spill_WDMA off=0) assign (__fch__ZL14sample_pointer.382) <382>;
|
||||
(__link.413 var=191 stl=LR off=0) assign (__link.412) <386>;
|
||||
(_ZL10input_port.414 var=51 _ZL11output_port.415 var=42 _ZL12css_cmd_flag.416 var=48 _ZL14output_pointer.417 var=40 _ZL14sample_pointer.418 var=44 _ZL15action_required.419 var=46 _ZL16corrupted_signal.420 var=37 _ZL22reference_noise_signal.421 var=39 _ZL6sample.422 var=45 __extDM.423 var=32 __extDM_SingleSignalPath.424 var=38 __extDM___PDMint16_.425 var=41 __extDM_int16_.426 var=43 __extDM_int32_.427 var=47 __extDM_int64_.428 var=54 __extDM_uint8_.429 var=49 __extDM_void.430 var=52 __extPM.431 var=33 __extPM_void.432 var=53 b0.433 var=35 b1.434 var=36 __vola.435 var=29) F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ (__link.413 __ptr_corrupted_signal.396 __ptr_reference_noise_signal.397 __fch__ZZ4mainvE4mode.399 __tmp.403 __tmp.407 __fch__ZL14sample_pointer.409 _ZL10input_port.391 _ZL11output_port.392 _ZL12css_cmd_flag.367 _ZL14output_pointer.381 _ZL14sample_pointer.287 _ZL15action_required.372 _ZL16corrupted_signal.280 _ZL22reference_noise_signal.282 _ZL6sample.393 __extDM.275 __extDM_SingleSignalPath.281 __extDM___PDMint16_.284 __extDM_int16_.394 __extDM_int32_.290 __extDM_int64_.297 __extDM_uint8_.292 __extDM_void.295 __extPM.276 __extPM_void.296 b0.278 b1.279 __vola.395) <387>;
|
||||
} #20 off=8
|
||||
#499 off=9
|
||||
() void_jump_int10_ (__trgt.1002) <1359>;
|
||||
} #18
|
||||
{
|
||||
(__vola.436 var=29) merge (__vola.320 __vola.435) <388>;
|
||||
(__extDM.437 var=32) merge (__extDM.275 __extDM.423) <389>;
|
||||
(__extPM.438 var=33) merge (__extPM.276 __extPM.431) <390>;
|
||||
(b0.439 var=35) merge (b0.278 b0.433) <391>;
|
||||
(b1.440 var=36) merge (b1.279 b1.434) <392>;
|
||||
(_ZL16corrupted_signal.441 var=37) merge (_ZL16corrupted_signal.280 _ZL16corrupted_signal.420) <393>;
|
||||
(__extDM_SingleSignalPath.442 var=38) merge (__extDM_SingleSignalPath.281 __extDM_SingleSignalPath.424) <394>;
|
||||
(_ZL22reference_noise_signal.443 var=39) merge (_ZL22reference_noise_signal.282 _ZL22reference_noise_signal.421) <395>;
|
||||
(_ZL14output_pointer.444 var=40) merge (_ZL14output_pointer.283 _ZL14output_pointer.417) <396>;
|
||||
(__extDM___PDMint16_.445 var=41) merge (__extDM___PDMint16_.284 __extDM___PDMint16_.425) <397>;
|
||||
(_ZL11output_port.446 var=42) merge (_ZL11output_port.285 _ZL11output_port.415) <398>;
|
||||
(__extDM_int16_.447 var=43) merge (__extDM_int16_.286 __extDM_int16_.426) <399>;
|
||||
(_ZL14sample_pointer.448 var=44) merge (_ZL14sample_pointer.287 _ZL14sample_pointer.418) <400>;
|
||||
(_ZL6sample.449 var=45) merge (_ZL6sample.288 _ZL6sample.422) <401>;
|
||||
(_ZL15action_required.450 var=46) merge (_ZL15action_required.319 _ZL15action_required.419) <402>;
|
||||
(__extDM_int32_.451 var=47) merge (__extDM_int32_.290 __extDM_int32_.427) <403>;
|
||||
(_ZL12css_cmd_flag.452 var=48) merge (_ZL12css_cmd_flag.315 _ZL12css_cmd_flag.416) <404>;
|
||||
(__extDM_uint8_.453 var=49) merge (__extDM_uint8_.292 __extDM_uint8_.429) <405>;
|
||||
(_ZL10input_port.454 var=51) merge (_ZL10input_port.294 _ZL10input_port.414) <406>;
|
||||
(__extDM_void.455 var=52) merge (__extDM_void.295 __extDM_void.430) <407>;
|
||||
(__extPM_void.456 var=53) merge (__extPM_void.296 __extPM_void.432) <408>;
|
||||
(__extDM_int64_.457 var=54) merge (__extDM_int64_.297 __extDM_int64_.428) <409>;
|
||||
} #22
|
||||
} #16
|
||||
#500 off=11
|
||||
() void_jump_int10_ (__trgt.1003) <1361>;
|
||||
(__true.1004 var=319) const () <1362>;
|
||||
} #12
|
||||
{
|
||||
() while_expr (__true.1004) <412>;
|
||||
(__vola.460 var=29 __vola.461 var=29) exit (__vola.436) <413>;
|
||||
(__extDM.466 var=32 __extDM.467 var=32) exit (__extDM.437) <416>;
|
||||
(__extPM.468 var=33 __extPM.469 var=33) exit (__extPM.438) <417>;
|
||||
(b0.472 var=35 b0.473 var=35) exit (b0.439) <419>;
|
||||
(b1.474 var=36 b1.475 var=36) exit (b1.440) <420>;
|
||||
(_ZL16corrupted_signal.476 var=37 _ZL16corrupted_signal.477 var=37) exit (_ZL16corrupted_signal.441) <421>;
|
||||
(__extDM_SingleSignalPath.478 var=38 __extDM_SingleSignalPath.479 var=38) exit (__extDM_SingleSignalPath.442) <422>;
|
||||
(_ZL22reference_noise_signal.480 var=39 _ZL22reference_noise_signal.481 var=39) exit (_ZL22reference_noise_signal.443) <423>;
|
||||
(_ZL14output_pointer.482 var=40 _ZL14output_pointer.483 var=40) exit (_ZL14output_pointer.444) <424>;
|
||||
(__extDM___PDMint16_.484 var=41 __extDM___PDMint16_.485 var=41) exit (__extDM___PDMint16_.445) <425>;
|
||||
(_ZL11output_port.486 var=42 _ZL11output_port.487 var=42) exit (_ZL11output_port.446) <426>;
|
||||
(__extDM_int16_.488 var=43 __extDM_int16_.489 var=43) exit (__extDM_int16_.447) <427>;
|
||||
(_ZL14sample_pointer.490 var=44 _ZL14sample_pointer.491 var=44) exit (_ZL14sample_pointer.448) <428>;
|
||||
(_ZL6sample.492 var=45 _ZL6sample.493 var=45) exit (_ZL6sample.449) <429>;
|
||||
(_ZL15action_required.494 var=46 _ZL15action_required.495 var=46) exit (_ZL15action_required.450) <430>;
|
||||
(__extDM_int32_.496 var=47 __extDM_int32_.497 var=47) exit (__extDM_int32_.451) <431>;
|
||||
(_ZL12css_cmd_flag.498 var=48 _ZL12css_cmd_flag.499 var=48) exit (_ZL12css_cmd_flag.452) <432>;
|
||||
(__extDM_uint8_.500 var=49 __extDM_uint8_.501 var=49) exit (__extDM_uint8_.453) <433>;
|
||||
(_ZL10input_port.504 var=51 _ZL10input_port.505 var=51) exit (_ZL10input_port.454) <435>;
|
||||
(__extDM_void.506 var=52 __extDM_void.507 var=52) exit (__extDM_void.455) <436>;
|
||||
(__extPM_void.508 var=53 __extPM_void.509 var=53) exit (__extPM_void.456) <437>;
|
||||
(__extDM_int64_.510 var=54 __extDM_int64_.511 var=54) exit (__extDM_int64_.457) <438>;
|
||||
} #24
|
||||
} #10 rng=[1,65535]
|
||||
#49 off=12 nxt=-4
|
||||
() sink (__vola.461) <659>;
|
||||
() sink (__extDM.467) <660>;
|
||||
() sink (__extPM.469) <661>;
|
||||
() sink (__sp.88) <662>;
|
||||
() sink (_ZL16corrupted_signal.477) <663>;
|
||||
() sink (__extDM_SingleSignalPath.479) <664>;
|
||||
() sink (_ZL22reference_noise_signal.481) <665>;
|
||||
() sink (_ZL14output_pointer.483) <666>;
|
||||
() sink (__extDM___PDMint16_.485) <667>;
|
||||
() sink (_ZL11output_port.487) <668>;
|
||||
() sink (__extDM_int16_.489) <669>;
|
||||
() sink (_ZL14sample_pointer.491) <670>;
|
||||
() sink (_ZL6sample.493) <671>;
|
||||
() sink (_ZL15action_required.495) <672>;
|
||||
() sink (__extDM_int32_.497) <673>;
|
||||
() sink (_ZL12css_cmd_flag.499) <674>;
|
||||
() sink (__extDM_uint8_.501) <675>;
|
||||
() sink (_ZL10input_port.505) <676>;
|
||||
() sink (__extDM_void.507) <677>;
|
||||
() sink (__extPM_void.509) <678>;
|
||||
() sink (__extDM_int64_.511) <679>;
|
||||
() sink (__ct_0.77) <680>;
|
||||
} #0
|
||||
0 : 'main.c';
|
||||
----------
|
||||
0 : (0,46:0,0);
|
||||
4 : (0,56:4,15);
|
||||
5 : (0,95:8,16);
|
||||
6 : (0,101:8,20);
|
||||
10 : (0,101:8,21);
|
||||
12 : (0,101:17,21);
|
||||
13 : (0,102:25,22);
|
||||
14 : (0,103:12,22);
|
||||
16 : (0,104:12,23);
|
||||
18 : (0,104:38,24);
|
||||
20 : (0,109:16,28);
|
||||
21 : (0,104:12,31);
|
||||
250 : (0,56:4,15);
|
||||
303 : (0,109:16,28);
|
||||
496 : (0,104:32,23);
|
||||
----------
|
||||
84 : (0,96:26,0);
|
||||
107 : (0,46:4,0);
|
||||
111 : (0,46:4,0);
|
||||
113 : (0,51:11,0);
|
||||
123 : (0,51:18,0);
|
||||
125 : (0,51:18,0);
|
||||
128 : (0,51:18,2);
|
||||
129 : (0,51:24,0);
|
||||
134 : (0,51:24,3);
|
||||
140 : (0,51:28,4);
|
||||
146 : (0,51:32,5);
|
||||
152 : (0,51:36,6);
|
||||
158 : (0,52:18,8);
|
||||
164 : (0,52:24,9);
|
||||
170 : (0,52:28,10);
|
||||
176 : (0,52:32,11);
|
||||
182 : (0,52:36,12);
|
||||
183 : (0,57:8,0);
|
||||
184 : (0,57:27,0);
|
||||
185 : (0,58:8,0);
|
||||
186 : (0,59:8,0);
|
||||
187 : (0,60:8,0);
|
||||
189 : (0,60:8,0);
|
||||
192 : (0,61:8,0);
|
||||
193 : (0,62:8,0);
|
||||
195 : (0,62:8,0);
|
||||
198 : (0,63:8,0);
|
||||
199 : (0,64:8,0);
|
||||
201 : (0,64:8,0);
|
||||
202 : (0,65:8,0);
|
||||
204 : (0,65:8,0);
|
||||
207 : (0,56:4,15);
|
||||
208 : (0,56:4,0);
|
||||
209 : (0,56:4,15);
|
||||
210 : (0,95:8,16);
|
||||
214 : (0,96:8,17);
|
||||
215 : (0,97:8,18);
|
||||
218 : (0,100:8,19);
|
||||
263 : (0,101:8,21);
|
||||
266 : (0,101:8,21);
|
||||
267 : (0,101:8,21);
|
||||
269 : (0,101:8,21);
|
||||
270 : (0,101:8,21);
|
||||
271 : (0,101:8,21);
|
||||
272 : (0,101:8,21);
|
||||
273 : (0,101:8,21);
|
||||
274 : (0,101:8,21);
|
||||
275 : (0,101:8,21);
|
||||
276 : (0,101:8,21);
|
||||
277 : (0,101:8,21);
|
||||
278 : (0,101:8,21);
|
||||
279 : (0,101:8,21);
|
||||
280 : (0,101:8,21);
|
||||
281 : (0,101:8,21);
|
||||
282 : (0,101:8,21);
|
||||
283 : (0,101:8,21);
|
||||
285 : (0,101:8,21);
|
||||
286 : (0,101:8,21);
|
||||
287 : (0,101:8,21);
|
||||
288 : (0,101:8,21);
|
||||
303 : (0,102:25,0);
|
||||
305 : (0,102:12,21);
|
||||
306 : (0,103:12,22);
|
||||
307 : (0,104:16,23);
|
||||
308 : (0,104:35,0);
|
||||
351 : (0,104:12,23);
|
||||
352 : (0,105:29,0);
|
||||
354 : (0,105:16,24);
|
||||
357 : (0,106:16,25);
|
||||
358 : (0,107:44,26);
|
||||
364 : (0,107:16,26);
|
||||
365 : (0,108:35,27);
|
||||
366 : (0,108:34,27);
|
||||
368 : (0,108:16,27);
|
||||
369 : (0,109:21,0);
|
||||
370 : (0,109:40,0);
|
||||
371 : (0,109:65,28);
|
||||
372 : (0,109:65,0);
|
||||
376 : (0,109:82,0);
|
||||
380 : (0,109:98,0);
|
||||
382 : (0,109:103,0);
|
||||
385 : (0,109:16,28);
|
||||
386 : (0,109:16,0);
|
||||
387 : (0,109:16,28);
|
||||
388 : (0,104:12,33);
|
||||
389 : (0,104:12,33);
|
||||
390 : (0,104:12,33);
|
||||
391 : (0,104:12,33);
|
||||
392 : (0,104:12,33);
|
||||
393 : (0,104:12,33);
|
||||
394 : (0,104:12,33);
|
||||
395 : (0,104:12,33);
|
||||
396 : (0,104:12,33);
|
||||
397 : (0,104:12,33);
|
||||
398 : (0,104:12,33);
|
||||
399 : (0,104:12,33);
|
||||
400 : (0,104:12,33);
|
||||
401 : (0,104:12,33);
|
||||
402 : (0,104:12,33);
|
||||
403 : (0,104:12,33);
|
||||
404 : (0,104:12,33);
|
||||
405 : (0,104:12,33);
|
||||
406 : (0,104:12,33);
|
||||
407 : (0,104:12,33);
|
||||
408 : (0,104:12,33);
|
||||
409 : (0,104:12,33);
|
||||
412 : (0,101:8,35);
|
||||
413 : (0,101:8,35);
|
||||
416 : (0,101:8,35);
|
||||
417 : (0,101:8,35);
|
||||
419 : (0,101:8,35);
|
||||
420 : (0,101:8,35);
|
||||
421 : (0,101:8,35);
|
||||
422 : (0,101:8,35);
|
||||
423 : (0,101:8,35);
|
||||
424 : (0,101:8,35);
|
||||
425 : (0,101:8,35);
|
||||
426 : (0,101:8,35);
|
||||
427 : (0,101:8,35);
|
||||
428 : (0,101:8,35);
|
||||
429 : (0,101:8,35);
|
||||
430 : (0,101:8,35);
|
||||
431 : (0,101:8,35);
|
||||
432 : (0,101:8,35);
|
||||
433 : (0,101:8,35);
|
||||
435 : (0,101:8,35);
|
||||
436 : (0,101:8,35);
|
||||
437 : (0,101:8,35);
|
||||
438 : (0,101:8,35);
|
||||
593 : (0,107:33,26);
|
||||
633 : (0,107:33,0);
|
||||
635 : (0,107:33,0);
|
||||
703 : (0,96:37,0);
|
||||
705 : (0,109:82,0);
|
||||
789 : (0,46:4,0);
|
||||
817 : (0,51:11,0);
|
||||
845 : (0,52:11,0);
|
||||
901 : (0,51:24,0);
|
||||
929 : (0,51:28,0);
|
||||
957 : (0,51:32,0);
|
||||
985 : (0,51:36,0);
|
||||
1013 : (0,52:24,0);
|
||||
1041 : (0,52:28,0);
|
||||
1069 : (0,52:32,0);
|
||||
1097 : (0,52:36,0);
|
||||
1154 : (0,46:4,0);
|
||||
1160 : (0,51:11,0);
|
||||
1162 : (0,52:11,0);
|
||||
1172 : (0,51:24,0);
|
||||
1178 : (0,51:28,0);
|
||||
1184 : (0,51:32,0);
|
||||
1190 : (0,51:36,0);
|
||||
1196 : (0,52:24,0);
|
||||
1202 : (0,52:28,0);
|
||||
1208 : (0,52:32,0);
|
||||
1214 : (0,52:36,0);
|
||||
1223 : (0,104:32,23);
|
||||
1312 : (0,104:32,23);
|
||||
1356 : (0,104:12,23);
|
||||
1361 : (0,101:8,35);
|
||||
|
||||
8
simulation/Release/chesswork/main-b11aa2.#
Normal file
8
simulation/Release/chesswork/main-b11aa2.#
Normal file
@@ -0,0 +1,8 @@
|
||||
466ba9a29dd6732e5048de41303e492793f3e524
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
8c9014769355b236211cd7156468f42706cc2c17
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
fa4a2bbf63f4c53259a8af9b8f5234ce21cdd3d5
|
||||
44
|
||||
0
|
||||
BIN
simulation/Release/chesswork/main-b11aa2.o
Normal file
BIN
simulation/Release/chesswork/main-b11aa2.o
Normal file
Binary file not shown.
75
simulation/Release/chesswork/main-b11aa2.sfg
Normal file
75
simulation/Release/chesswork/main-b11aa2.sfg
Normal file
@@ -0,0 +1,75 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! extern void isr0()
|
||||
Fisr0 : user_defined, isr, called {
|
||||
fnm : "isr0" 'void isr0()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] srFlags[0] );
|
||||
svd : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : isr0 typ=uint20_ bnd=e stl=PM tref=void____
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
27 : __R_ILR typ=dmaddr_ bnd=d stl=ILR
|
||||
30 : __vola typ=uint20_ bnd=b stl=PM
|
||||
35 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __ila typ=dmaddr_ bnd=b stl=ILR
|
||||
37 : _ZL15action_required typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
39 : __rd___sp typ=dmaddr_ bnd=m
|
||||
40 : __rd___ila typ=dmaddr_ bnd=m
|
||||
42 : __ptr_action_required typ=dmaddr_ val=0a bnd=m adro=37
|
||||
46 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
58 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
79 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
80 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
]
|
||||
Fisr0 {
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__R_ILR.25 var=27) st_def () <49>;
|
||||
(__vola.28 var=30) source () <52>;
|
||||
(__sp.33 var=35) source () <57>;
|
||||
(__ila.34 var=36) source () <58>;
|
||||
(_ZL15action_required.35 var=37) source () <59>;
|
||||
(__ptr_action_required.39 var=42) const () <63>;
|
||||
(__rd___sp.41 var=39) rd_res_reg (__R_SP.24 __sp.33) <65>;
|
||||
(__R_SP.45 var=26 __sp.46 var=35) wr_res_reg (__rt.87 __sp.33) <69>;
|
||||
(__ct_1.47 var=46) const () <71>;
|
||||
(__M_WDMA.49 var=11 _ZL15action_required.50 var=37 __vola.51 var=30) store (__ct_1.47 __ptr_action_required.39 _ZL15action_required.35 __vola.28) <73>;
|
||||
(__rd___sp.52 var=39) rd_res_reg (__R_SP.24 __sp.46) <74>;
|
||||
(__R_SP.56 var=26 __sp.57 var=35) wr_res_reg (__rt.109 __sp.46) <78>;
|
||||
(__rd___ila.58 var=40) rd_res_reg (__R_ILR.25 __ila.34) <79>;
|
||||
() void_reti_dmaddr_ (__rd___ila.58) <80>;
|
||||
() sink (__vola.51) <81>;
|
||||
() sink (__sp.57) <86>;
|
||||
() sink (_ZL15action_required.50) <88>;
|
||||
(__rt.87 var=58) __Pvoid__pl___Pvoid_int18_ (__rd___sp.41 __ct_0S0.122) <139>;
|
||||
(__rt.109 var=58) __Pvoid__pl___Pvoid_int18_ (__rd___sp.52 __ct_0s0.123) <167>;
|
||||
(__ct_0S0.122 var=79) const () <191>;
|
||||
(__ct_0s0.123 var=80) const () <193>;
|
||||
} #5 off=0 nxt=-2
|
||||
0 : 'main.c';
|
||||
----------
|
||||
5 : (0,44:1,2);
|
||||
----------
|
||||
65 : (0,42:16,0);
|
||||
69 : (0,42:16,0);
|
||||
71 : (0,43:19,0);
|
||||
73 : (0,43:1,1);
|
||||
74 : (0,44:1,0);
|
||||
78 : (0,44:1,2);
|
||||
79 : (0,44:1,0);
|
||||
80 : (0,44:1,2);
|
||||
139 : (0,42:16,0);
|
||||
167 : (0,44:1,0);
|
||||
191 : (0,42:16,0);
|
||||
193 : (0,44:1,0);
|
||||
|
||||
8
simulation/Release/chesswork/main-d47062.#
Normal file
8
simulation/Release/chesswork/main-d47062.#
Normal file
@@ -0,0 +1,8 @@
|
||||
0b3a1439876c35d4e2e78ed4e229a1ffbdca4df3
|
||||
b85c95c92e890cf0233f9e50ae029a827db9f04a
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
c238342daf0be0efc059b5ac898db49a2a4f5cd4
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
0
|
||||
0
|
||||
10
simulation/Release/chesswork/main-d47062.asm
Normal file
10
simulation/Release/chesswork/main-d47062.asm
Normal file
@@ -0,0 +1,10 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
.dir 0 "C:\Users\phangl\OneDrive - MED-EL\Desktop\LPDSP32_Modell\lib"
|
||||
.text local 1 void_core_halt
|
||||
.placeholder
|
||||
.src_ref 0 "lpdsp32_irq.h" 66 first
|
||||
powerdown; nop
|
||||
9
simulation/Release/chesswork/main-d47062.asm.mic
Normal file
9
simulation/Release/chesswork/main-d47062.asm.mic
Normal file
@@ -0,0 +1,9 @@
|
||||
|
||||
// File generated by darts version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:47 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\darts.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib +m -g +HC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/elongation -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 main-d47062.asm -omain-d47062.asm.mic lpdsp32
|
||||
|
||||
// Release: ipp X-2025.06
|
||||
//.text local void_core_halt void_core_halt
|
||||
0 2/*first*/ "01000110000011100000" .srcref "%PROCDIR%" "lpdsp32_irq.h" 66 // powerdown ; nop
|
||||
1 0 "00111000000000000000"
|
||||
0
simulation/Release/chesswork/main.aliases
Normal file
0
simulation/Release/chesswork/main.aliases
Normal file
19
simulation/Release/chesswork/main.ctt
Normal file
19
simulation/Release/chesswork/main.ctt
Normal file
@@ -0,0 +1,19 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
#const float_tininess_after_rounding enum __anonymous0__main_ 0 (0x0)
|
||||
#const float_tininess_before_rounding enum __anonymous0__main_ 1 (0x1)
|
||||
#const float_round_nearest_even enum __anonymous1__main_ 0 (0x0)
|
||||
#const float_round_to_zero enum __anonymous1__main_ 1 (0x1)
|
||||
#const float_round_up enum __anonymous1__main_ 2 (0x2)
|
||||
#const float_round_down enum __anonymous1__main_ 3 (0x3)
|
||||
#const block_len const int 1 (0x1)
|
||||
#const OUTPUT_MODE_C_SENSOR enum OutputMode 0 (0x0)
|
||||
#const OUTPUT_MODE_ACC_SENSOR enum OutputMode 1 (0x1)
|
||||
#const OUTPUT_MODE_FIR_LMS enum OutputMode 2 (0x2)
|
||||
#const OUTPUT_MODE_FIR enum OutputMode 3 (0x3)
|
||||
#const OUTPUT_MODE_FIR_LMS_LEAKY enum OutputMode 4 (0x4)
|
||||
#const ones unsigned 4294967295 (0xffffffff)
|
||||
#const coefficients int 64 (0x40)
|
||||
228
simulation/Release/chesswork/main.dti
Normal file
228
simulation/Release/chesswork/main.dti
Normal file
@@ -0,0 +1,228 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
bool__ : _basic() bool;
|
||||
__cchar__ : _basic() __cchar;
|
||||
__schar__ : _basic() __schar;
|
||||
__uchar__ : _basic() __uchar;
|
||||
__sshort__ : _basic() __sshort;
|
||||
__ushort__ : _basic() __ushort;
|
||||
__sint__ : _basic() __sint;
|
||||
__uint__ : _basic() __uint;
|
||||
__slong__ : _basic() __slong;
|
||||
__ulong__ : _basic() __ulong;
|
||||
__flongdouble__ : _basic() __flongdouble;
|
||||
int72___ : _basic() int72_;
|
||||
int32___ : _basic() int32_;
|
||||
__slonglong__ : _basic() __slonglong;
|
||||
__ulonglong__ : _basic() __ulonglong;
|
||||
__Pvoid__ : _basic() __Pvoid;
|
||||
int64___ : _basic() int64_;
|
||||
accum_t__ : _basic() accum_t;
|
||||
flags_t__ : _basic() flags_t;
|
||||
__rtp__ : _typedef() __rtp $__ulonglong__;
|
||||
__atp0__ : _typedef() __atp0 $accum_t__;
|
||||
__atp1__ : _typedef() __atp1 $accum_t__;
|
||||
__atp2__ : _typedef() __atp2 $__ulonglong__;
|
||||
dmaddr___ : _basic() dmaddr_;
|
||||
float32__ : _typedef() float32 $__uint__;
|
||||
__rtp___1 : _typedef() __rtp $float32__;
|
||||
__atp0___1 : _typedef() __atp0 $__sint__;
|
||||
float64__ : _typedef() float64 $__ulonglong__;
|
||||
__rtp___2 : _typedef() __rtp $float64__;
|
||||
__atp0___2 : _typedef() __atp0 $__sint__;
|
||||
__rtp___3 : _typedef() __rtp $float32__;
|
||||
__atp0___3 : _typedef() __atp0 $__slonglong__;
|
||||
__rtp___4 : _typedef() __rtp $float64__;
|
||||
__atp0___4 : _typedef() __atp0 $__slonglong__;
|
||||
__rtp___5 : _typedef() __rtp $__sint__;
|
||||
__atp0___5 : _typedef() __atp0 $float32__;
|
||||
__rtp___6 : _typedef() __rtp $__slonglong__;
|
||||
__atp0___6 : _typedef() __atp0 $float32__;
|
||||
__rtp___7 : _typedef() __rtp $float64__;
|
||||
__atp0___7 : _typedef() __atp0 $float32__;
|
||||
__rtp___8 : _typedef() __rtp $float32__;
|
||||
__atp0___8 : _typedef() __atp0 $float32__;
|
||||
__rtp___9 : _typedef() __rtp $float32__;
|
||||
__atp0___9 : _typedef() __atp0 $float32__;
|
||||
__atp1___1 : _typedef() __atp1 $float32__;
|
||||
__rtp___10 : _typedef() __rtp $float32__;
|
||||
__atp0___10 : _typedef() __atp0 $float32__;
|
||||
__atp1___2 : _typedef() __atp1 $float32__;
|
||||
__rtp___11 : _typedef() __rtp $float32__;
|
||||
__atp0___11 : _typedef() __atp0 $float32__;
|
||||
__atp1___3 : _typedef() __atp1 $float32__;
|
||||
__rtp___12 : _typedef() __rtp $float32__;
|
||||
__atp0___12 : _typedef() __atp0 $float32__;
|
||||
__atp1___4 : _typedef() __atp1 $float32__;
|
||||
__rtp___13 : _typedef() __rtp $__sint__;
|
||||
__atp0___13 : _typedef() __atp0 $float32__;
|
||||
__atp1___5 : _typedef() __atp1 $float32__;
|
||||
__rtp___14 : _typedef() __rtp $__sint__;
|
||||
__atp0___14 : _typedef() __atp0 $float32__;
|
||||
__atp1___6 : _typedef() __atp1 $float32__;
|
||||
__rtp___15 : _typedef() __rtp $__sint__;
|
||||
__atp0___15 : _typedef() __atp0 $float32__;
|
||||
__atp1___7 : _typedef() __atp1 $float32__;
|
||||
__rtp___16 : _typedef() __rtp $__sint__;
|
||||
__atp0___16 : _typedef() __atp0 $float64__;
|
||||
__rtp___17 : _typedef() __rtp $__slonglong__;
|
||||
__atp0___17 : _typedef() __atp0 $float64__;
|
||||
__rtp___18 : _typedef() __rtp $float32__;
|
||||
__atp0___18 : _typedef() __atp0 $float64__;
|
||||
__rtp___19 : _typedef() __rtp $float64__;
|
||||
__atp0___19 : _typedef() __atp0 $float64__;
|
||||
__rtp___20 : _typedef() __rtp $float64__;
|
||||
__atp0___20 : _typedef() __atp0 $float64__;
|
||||
__atp1___8 : _typedef() __atp1 $float64__;
|
||||
__rtp___21 : _typedef() __rtp $float64__;
|
||||
__atp0___21 : _typedef() __atp0 $float64__;
|
||||
__atp1___9 : _typedef() __atp1 $float64__;
|
||||
__rtp___22 : _typedef() __rtp $float64__;
|
||||
__atp0___22 : _typedef() __atp0 $float64__;
|
||||
__atp1___10 : _typedef() __atp1 $float64__;
|
||||
__rtp___23 : _typedef() __rtp $float64__;
|
||||
__atp0___23 : _typedef() __atp0 $float64__;
|
||||
__atp1___11 : _typedef() __atp1 $float64__;
|
||||
__rtp___24 : _typedef() __rtp $__sint__;
|
||||
__atp0___24 : _typedef() __atp0 $float64__;
|
||||
__atp1___12 : _typedef() __atp1 $float64__;
|
||||
__rtp___25 : _typedef() __rtp $__sint__;
|
||||
__atp0___25 : _typedef() __atp0 $float64__;
|
||||
__atp1___13 : _typedef() __atp1 $float64__;
|
||||
__rtp___26 : _typedef() __rtp $__sint__;
|
||||
__atp0___26 : _typedef() __atp0 $float64__;
|
||||
__atp1___14 : _typedef() __atp1 $float64__;
|
||||
__ffloat__ : _basic() __ffloat;
|
||||
__fdouble__ : _basic() __fdouble;
|
||||
uint15__IMSK : _basic(IMSK,1,1) uint15_;
|
||||
uint15__irq_stat : _basic(irq_stat,1,1) uint15_;
|
||||
__sint_DMA : _basic(DMA,4,4) __sint;
|
||||
__Pvoid_DMA : _basic(DMA,4,4) __Pvoid;
|
||||
__P__sint_DMA : _pointer(DMA,4,4) $__Pvoid_DMA $__sint_DMA;
|
||||
BufferPtr_DMA : _struct(DMA,12,4) BufferPtr {
|
||||
buffer_len $__sint_DMA @0;
|
||||
ptr_start $__P__sint_DMA @4;
|
||||
ptr_current $__P__sint_DMA @8;
|
||||
}
|
||||
__sint_DMB : _basic(DMB,4,4) __sint;
|
||||
__Pvoid_DMB : _basic(DMB,4,4) __Pvoid;
|
||||
__PDMB__sint_DMB : _pointer(DMB,4,4) $__Pvoid_DMB $__sint_DMB;
|
||||
BufferPtrDMB_DMB : _struct(DMB,12,4) BufferPtrDMB {
|
||||
buffer_len $__sint_DMB @0;
|
||||
ptr_start $__PDMB__sint_DMB @4;
|
||||
ptr_current $__PDMB__sint_DMB @8;
|
||||
}
|
||||
__A64DMB__sint_DMB : _array(DMB,256,4) [64] $__sint_DMB;
|
||||
__uchar_DMIO : _basic(DMIO,1,1) __uchar;
|
||||
__A5__sint_DMA : _array(DMA,20,4) [5] $__sint_DMA;
|
||||
__A2__sint_DMA : _array(DMA,8,4) [2] $__sint_DMA;
|
||||
__A16__sint_DMA : _array(DMA,64,4) [16] $__sint_DMA;
|
||||
SingleSignalPath_DMA : _struct(DMA,144,4) SingleSignalPath {
|
||||
input_scale $__sint_DMA @0;
|
||||
x_nbit_bitshift $__sint_DMA @4;
|
||||
preemph_activated $__sint_DMA @8;
|
||||
b_preemph $__A5__sint_DMA @12;
|
||||
_preemph_scale_nbits $__sint_DMA @32;
|
||||
_xd $__A2__sint_DMA @36;
|
||||
_yd $__A2__sint_DMA @44;
|
||||
_delay_buffer $__A16__sint_DMA @52;
|
||||
delay_buffer $BufferPtr_DMA @116;
|
||||
n_delay_samps $__sint_DMA @128;
|
||||
weight_actived $__sint_DMA @132;
|
||||
weight $__sint_DMA @136;
|
||||
_weight_scale_nbits $__sint_DMA @140;
|
||||
}
|
||||
__sshort_DMB : _basic(DMB,2,2) __sshort;
|
||||
int16_t_DMB : _typedef(DMB,2,2) int16_t $__sshort_DMB;
|
||||
__A4DMB__sshort_DMB : _array(DMB,8,2) [4] $int16_t_DMB;
|
||||
__PDMB__sshort_DMA : _pointer(DMA,4,4) $__Pvoid_DMA $int16_t_DMB;
|
||||
__rtp___27 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___27 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___15 : _typedef() __atp1 $__sint__;
|
||||
__rtp___28 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___28 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___16 : _typedef() __atp1 $__sint__;
|
||||
__rtp___29 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___29 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___30 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___30 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___31 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___31 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___32 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___32 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___33 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___33 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___34 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___34 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___35 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___35 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___36 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___36 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___37 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___37 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___38 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___38 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___39 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___39 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___40 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___40 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___41 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___41 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___42 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___42 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___43 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___43 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___44 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___44 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___45 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___45 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___46 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___46 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___47 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___47 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___17 : _typedef() __atp1 $__ffloat__;
|
||||
__rtp___48 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___48 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___18 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___49 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___49 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___19 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___50 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___50 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___51 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___51 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___52 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___52 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___53 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___53 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___54 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___54 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___55 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___55 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___20 : _typedef() __atp1 $__ffloat__;
|
||||
__rtp___56 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___56 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___21 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___57 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___57 : _typedef() __atp0 $__ffloat__;
|
||||
__PDMBvoid__ : _basic() __PDMBvoid;
|
||||
fract_t__ : _basic() fract_t;
|
||||
pmem_t__ : _basic() pmem_t;
|
||||
__PDMvoid__ : _basic() __PDMvoid;
|
||||
__PDMAvoid__ : _basic() __PDMAvoid;
|
||||
__PDMIOvoid__ : _basic() __PDMIOvoid;
|
||||
__PPMvoid__ : _basic() __PPMvoid;
|
||||
OutputMode_DMA : _enum(DMA,4,4) OutputMode $__sint_DMA {
|
||||
OUTPUT_MODE_C_SENSOR = 0;
|
||||
OUTPUT_MODE_ACC_SENSOR = 1;
|
||||
OUTPUT_MODE_FIR_LMS = 2;
|
||||
OUTPUT_MODE_FIR = 3;
|
||||
OUTPUT_MODE_FIR_LMS_LEAKY = 4;
|
||||
}
|
||||
void____ : _function() _void;
|
||||
__sint____ : _function() $__sint__;
|
||||
__fdouble_DMA : _basic(DMA,8,8) __fdouble;
|
||||
__A5__fdouble_DMA : _array(DMA,40,8) [5] $__fdouble_DMA;
|
||||
50
simulation/Release/chesswork/main.fnm
Normal file
50
simulation/Release/chesswork/main.fnm
Normal file
@@ -0,0 +1,50 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
// toolrelease _25R2;
|
||||
|
||||
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\simulation\\main.c"
|
||||
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\simulation"
|
||||
|
||||
"main-b11aa2.sfg"
|
||||
: isr0
|
||||
: "isr0" global "main.c" 42 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"main-9f2435.sfg"
|
||||
: _main
|
||||
: "main" global "main.c" 46 Ofile
|
||||
(
|
||||
_Z4initP16SingleSignalPathS0_PdS1_iidddi
|
||||
_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
void_enable_interrupts
|
||||
void_core_halt
|
||||
)
|
||||
|
||||
"main-2c657d.asm"
|
||||
: void_enable_interrupts
|
||||
: "enable_interrupts" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\lpdsp32_irq.h" 43 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"main-d47062.asm"
|
||||
: void_core_halt
|
||||
: "core_halt" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\lpdsp32_irq.h" 62 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z4initP16SingleSignalPathS0_PdS1_iidddi
|
||||
: "init" global "signal_processing\\include\\signal_path.h" 121 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
: "calc" global "signal_processing\\include\\signal_path.h" 125 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
26
simulation/Release/chesswork/main.gvt
Normal file
26
simulation/Release/chesswork/main.gvt
Normal file
@@ -0,0 +1,26 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
[
|
||||
1 : _imsk_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=IMSK tref=uint15__IMSK
|
||||
2 : _irq_stat_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=irq_stat tref=uint15__irq_stat
|
||||
6 : _ZL12css_cmd_flag typ=int8_ val=12582916f bnd=f sz=1 algn=1 stl=DMIO tref=__uchar_DMIO
|
||||
7 : _ZL15action_required typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
8 : _ZL16corrupted_signal typ=int8_ bnd=f sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
9 : _ZL22reference_noise_signal typ=int8_ bnd=f sz=144 algn=4 stl=DMA tref=SingleSignalPath_DMA
|
||||
10 : _ZL10input_port typ=int8_ val=8388608f bnd=f sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
11 : _ZL11output_port typ=int8_ val=8388624f bnd=f sz=8 algn=2 stl=DMB tref=__A4DMB__sshort_DMB
|
||||
12 : _ZL15input_pointer_0 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
13 : _ZL15input_pointer_1 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
14 : _ZL14output_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
15 : _ZL14sample_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
|
||||
16 : _ZL6sample typ=int8_ bnd=f sz=2 algn=2 stl=DMB tref=int16_t_DMB
|
||||
17 : _ZZ4mainvE4mode typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=OutputMode_DMA
|
||||
]
|
||||
__main_sttc {
|
||||
} #0
|
||||
----------
|
||||
----------
|
||||
|
||||
8
simulation/Release/chesswork/main.gvt.#
Normal file
8
simulation/Release/chesswork/main.gvt.#
Normal file
@@ -0,0 +1,8 @@
|
||||
b94f5e81f66808a8f4f9315bd020e05811fb8d4a
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
d125357c90bc01d214517ac1f8dd127ce36fc2ee
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
0
|
||||
0
|
||||
BIN
simulation/Release/chesswork/main.gvt.o
Normal file
BIN
simulation/Release/chesswork/main.gvt.o
Normal file
Binary file not shown.
18
simulation/Release/chesswork/main.ini
Normal file
18
simulation/Release/chesswork/main.ini
Normal file
@@ -0,0 +1,18 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
_ZL12css_cmd_flag/6 $ css_cmd_flag
|
||||
_ZL15action_required/7 $ action_required
|
||||
_ZL16corrupted_signal/8 $ corrupted_signal
|
||||
_ZL22reference_noise_signal/9 $ reference_noise_signal
|
||||
_ZL10input_port/10 $ input_port
|
||||
_ZL11output_port/11 $ output_port
|
||||
_ZL15input_pointer_0/12 $ input_pointer_0
|
||||
_ZL15input_pointer_1/13 $ input_pointer_1
|
||||
_ZL14output_pointer/14 $ output_pointer
|
||||
_ZL14sample_pointer/15 $ sample_pointer
|
||||
_ZL6sample/16 $ sample
|
||||
_ZZ4mainvE4mode/17 $ mode _main
|
||||
_ZZ4mainvE4mode/17 : #02 #00 #00 #00
|
||||
64
simulation/Release/chesswork/main.lib
Normal file
64
simulation/Release/chesswork/main.lib
Normal file
@@ -0,0 +1,64 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
toolrelease _25R2;
|
||||
|
||||
|
||||
// additional
|
||||
prop gp_offset_type = ( __sint );
|
||||
|
||||
prop static_variable_registers = ( IMSK irq_stat );
|
||||
|
||||
// inline assembly void enable_interrupts()
|
||||
Fvoid_enable_interrupts : user_defined, volatile, assembly {
|
||||
fnm : "enable_interrupts" 'inline assembly void enable_interrupts()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// inline assembly void core_halt()
|
||||
Fvoid_core_halt : user_defined, volatile, assembly {
|
||||
fnm : "core_halt" 'inline assembly void core_halt()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
|
||||
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
|
||||
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
}
|
||||
|
||||
// void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
|
||||
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
|
||||
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
|
||||
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
|
||||
vac : ( srIM[0] );
|
||||
}
|
||||
|
||||
// void isr0()
|
||||
Fisr0 : user_defined, isr, called {
|
||||
fnm : "isr0" 'void isr0()';
|
||||
flc : ( A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] Ae[0] Ae[1] Ah[0] Ah[1] Al[0] Al[1] Be[0] Be[1] Bh[0] Bh[1] Bl[0] Bl[1] C[0] C[1] C[2] C[3] LB[0] LB[1] LR[0] LSZ[0] LSZ[1] RA[0] RA[1] RB[0] RB[1] srFlags[0] );
|
||||
svd : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// int main()
|
||||
F_main : user_defined, called {
|
||||
fnm : "main" 'int main()';
|
||||
arg : ( dmaddr_:i int32_:r );
|
||||
loc : ( LR[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( l=80 b=8 );
|
||||
llv : 0 4 0 0 0 ;
|
||||
}
|
||||
|
||||
3
simulation/Release/chesswork/main.objlist
Normal file
3
simulation/Release/chesswork/main.objlist
Normal file
@@ -0,0 +1,3 @@
|
||||
"main-b11aa2.o" 0
|
||||
"main-9f2435.o" 0
|
||||
"main.gvt.o" 0
|
||||
13
simulation/Release/chesswork/main.tof
Normal file
13
simulation/Release/chesswork/main.tof
Normal file
@@ -0,0 +1,13 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
|
||||
|
||||
|
||||
// per defined called function, table of invoked intrinsic functions (excluding built-in operators):
|
||||
|
||||
// void isr0()
|
||||
|
||||
// int main()
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-101f20.#
Normal file
8
simulation/Release/chesswork/signal_path-101f20.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
e09177406743480e193022463cd660529462057a
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
51f321a08bbf6d068e6d50c4fac79f685b77b8d9
|
||||
348
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-101f20.o
Normal file
BIN
simulation/Release/chesswork/signal_path-101f20.o
Normal file
Binary file not shown.
523
simulation/Release/chesswork/signal_path-101f20.sfg
Normal file
523
simulation/Release/chesswork/signal_path-101f20.sfg
Normal file
@@ -0,0 +1,523 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
|
||||
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
|
||||
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
|
||||
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)
|
||||
F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_put_sample_DMB" 'void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[4] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___PSingleSignalPath_OutputMode___PDMB__sshort___PDMB__sshort___PDMB__sshort__
|
||||
8 : __M_SDMB typ=int16_ bnd=d stl=SDMB
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
|
||||
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
36 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
37 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
38 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
39 : ptr_fir_lms_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
|
||||
40 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
|
||||
41 : ptr_fir_lms_coeffs typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
|
||||
42 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
|
||||
43 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
|
||||
44 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int8_ bnd=i sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
|
||||
45 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
46 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
47 : __extDM_int16_ typ=int8_ bnd=b stl=DM
|
||||
48 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
49 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
50 : ptr_fir_lms_delay_line_ptr_current typ=int8_ bnd=b stl=DM
|
||||
51 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
|
||||
52 : ptr_fir_lms_delay_line_ptr_start typ=int8_ bnd=b stl=DM
|
||||
53 : ptr_fir_lms_coeffs_ptr_current typ=int8_ bnd=b stl=DM
|
||||
54 : ptr_fir_lms_delay_line_buffer_len typ=int8_ bnd=b stl=DM
|
||||
55 : ptr_fir_lms_coeffs_buffer_len typ=int8_ bnd=b stl=DM
|
||||
56 : ptr_fir_lms_coeffs_ptr_start typ=int8_ bnd=b stl=DM
|
||||
57 : __extDM_int64_ typ=int8_ bnd=b stl=DM
|
||||
58 : __rd___sp typ=dmaddr_ bnd=m
|
||||
60 : __ptr_cSensor_32 typ=dmaddr_ val=0a bnd=m adro=35
|
||||
62 : __ptr_accSensor_32 typ=dmaddr_ val=0a bnd=m adro=36
|
||||
64 : __ptr_c_block_pre typ=dmaddr_ val=0a bnd=m adro=37
|
||||
66 : __ptr_acc_block_pre typ=dmaddr_ val=0a bnd=m adro=38
|
||||
67 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ bnd=m
|
||||
68 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ val=0a bnd=m adro=39
|
||||
70 : __ptr_ptr_fir_lms_coeffs typ=dmaddr_ val=0a bnd=m adro=41
|
||||
72 : __ptr_acc_block_filt typ=dmaddr_ val=0a bnd=m adro=43
|
||||
74 : __ptr_out_32 typ=dmaddr_ val=0a bnd=m adro=44
|
||||
76 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=45
|
||||
77 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
78 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
79 : cSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
80 : accSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
81 : output_mode typ=int32_ bnd=p tref=OutputMode__
|
||||
82 : cSensor typ=dmaddr_ bnd=p tref=__PDMB__sshort__
|
||||
83 : accSensor typ=dmaddr_ bnd=p tref=__PDMB__sshort__
|
||||
84 : out_16 typ=dmaddr_ bnd=p tref=__PDMB__sshort__
|
||||
92 : __tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ typ=int32_ bnd=m tref=__sint__
|
||||
97 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__
|
||||
99 : __inl_p_h typ=dmaddr_ bnd=m tref=__P__sint__
|
||||
102 : __inl_acc1_A typ=int72_ bnd=m tref=accum_t__
|
||||
103 : __inl_acc1_B typ=int72_ bnd=m tref=accum_t__
|
||||
111 : __inl_acc1_C typ=int72_ bnd=m tref=accum_t__
|
||||
118 : __inl_p_h0 typ=dmaddr_ bnd=m tref=__P__sint__
|
||||
119 : __inl_p_x0 typ=dmaddr_ bnd=m tref=__PDMB__sint__
|
||||
120 : __inl_p_x1 typ=dmaddr_ bnd=m tref=__PDMB__sint__
|
||||
124 : __inl_acc_C typ=int72_ bnd=m tref=accum_t__
|
||||
125 : __inl_prod typ=int32_ bnd=m tref=__sint__
|
||||
127 : __inl_h0 typ=int32_ bnd=m tref=__sint__
|
||||
128 : __inl_h1 typ=int32_ bnd=m tref=__sint__
|
||||
129 : __inl_acc_A typ=int72_ bnd=m tref=accum_t__
|
||||
130 : __inl_acc_B typ=int72_ bnd=m tref=accum_t__
|
||||
137 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
141 : __fch___extDM_int16_ typ=int16_ bnd=m
|
||||
143 : __ct_16 typ=int32_ val=16f bnd=m
|
||||
145 : __tmp typ=int32_ bnd=m
|
||||
156 : __fch___extDM_int16_ typ=int16_ bnd=m
|
||||
160 : __tmp typ=int32_ bnd=m
|
||||
202 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
205 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int32_ bnd=m
|
||||
206 : _Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi typ=dmaddr_ val=0r bnd=m
|
||||
208 : __link typ=dmaddr_ bnd=m
|
||||
212 : __fch_ptr_fir_lms_delay_line_ptr_current typ=dmaddr_ bnd=m
|
||||
216 : __fch_ptr_fir_lms_delay_line_ptr_start typ=dmaddr_ bnd=m
|
||||
220 : __fch_ptr_fir_lms_coeffs_ptr_current typ=dmaddr_ bnd=m
|
||||
224 : __fch_ptr_fir_lms_delay_line_buffer_len typ=int32_ bnd=m
|
||||
228 : __fch_ptr_fir_lms_coeffs_buffer_len typ=int32_ bnd=m
|
||||
237 : __fchtmp typ=int32_ bnd=m
|
||||
238 : __fchtmp typ=int32_ bnd=m
|
||||
248 : __fchtmp typ=int32_ bnd=m
|
||||
249 : __fchtmp typ=int32_ bnd=m
|
||||
259 : __tmp typ=int72_ bnd=m
|
||||
261 : __tmp typ=int72_ bnd=m
|
||||
263 : __tmp typ=int32_ bnd=m
|
||||
265 : __tmp typ=int32_ bnd=m
|
||||
279 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int32_ bnd=m
|
||||
284 : __tmp typ=int32_ bnd=m
|
||||
295 : __fch_ptr_fir_lms_coeffs_ptr_start typ=dmaddr_ bnd=m
|
||||
332 : __fch__ZL2mu typ=int32_ bnd=m
|
||||
337 : __fchtmp typ=int64_ bnd=m
|
||||
343 : __fchtmp typ=int32_ bnd=m
|
||||
344 : __tmp typ=int72_ bnd=m
|
||||
346 : __fchtmp typ=int32_ bnd=m
|
||||
347 : __tmp typ=int72_ bnd=m
|
||||
361 : __tmp typ=int32_ bnd=m
|
||||
362 : __tmp typ=int32_ bnd=m
|
||||
363 : __tmp typ=int64_ bnd=m
|
||||
382 : __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int32_ bnd=m
|
||||
386 : __tmp typ=int72_ bnd=m
|
||||
387 : __tmp typ=int32_ bnd=m
|
||||
388 : __tmp typ=int16_ bnd=m
|
||||
428 : __ct_m4 typ=int18_ val=-4f bnd=m
|
||||
429 : __ct_m8 typ=int18_ val=-8f bnd=m
|
||||
453 : __vcnt typ=int32_ bnd=m
|
||||
454 : __ct_m1 typ=int32_ val=-1f bnd=m
|
||||
455 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
456 : __cv typ=uint16_ bnd=m
|
||||
482 : __ptr_ptr_fir_lms_coeffs__a8 typ=dmaddr_ val=8a bnd=m adro=41
|
||||
485 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
513 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
514 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
515 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
516 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
520 : __ct_2 typ=uint2_ val=2f bnd=m
|
||||
527 : __ct_1 typ=uint2_ val=1f bnd=m
|
||||
532 : __tmp typ=int72_ bnd=m
|
||||
537 : __tmp typ=int18_ bnd=m
|
||||
540 : __inl_acc1_A typ=int32_ bnd=m
|
||||
541 : __inl_acc1_B typ=int32_ bnd=m
|
||||
547 : __trgt typ=uint16_ val=0j bnd=m
|
||||
548 : __vcnt typ=uint16_ bnd=m
|
||||
549 : __trgt typ=uint16_ val=0j bnd=m
|
||||
550 : __vcnt typ=uint16_ bnd=m
|
||||
]
|
||||
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ {
|
||||
#602 off=0
|
||||
(__M_SDMB.6 var=8) st_def () <12>;
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__M_WDMB.10 var=12) st_def () <20>;
|
||||
(__M_LDMA.12 var=14) st_def () <24>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.33 var=35) source () <57>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.34 var=36) source () <58>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.35 var=37) source () <59>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.36 var=38) source () <60>;
|
||||
(ptr_fir_lms_delay_line.37 var=39) source () <61>;
|
||||
(__extDM_BufferPtrDMB.38 var=40) source () <62>;
|
||||
(ptr_fir_lms_coeffs.39 var=41) source () <63>;
|
||||
(__extDM_BufferPtr.40 var=42) source () <64>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.41 var=43) source () <65>;
|
||||
(_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.42 var=44) source () <66>;
|
||||
(_ZL2mu.43 var=45) source () <67>;
|
||||
(__extDM_int32_.44 var=46) source () <68>;
|
||||
(__extDM_int16_.45 var=47) source () <69>;
|
||||
(__extDM_void.46 var=48) source () <70>;
|
||||
(__extPM_void.47 var=49) source () <71>;
|
||||
(ptr_fir_lms_delay_line_ptr_current.48 var=50) source () <72>;
|
||||
(__extDM___PDMint32_.49 var=51) source () <73>;
|
||||
(ptr_fir_lms_delay_line_ptr_start.50 var=52) source () <74>;
|
||||
(ptr_fir_lms_coeffs_ptr_current.51 var=53) source () <75>;
|
||||
(ptr_fir_lms_delay_line_buffer_len.52 var=54) source () <76>;
|
||||
(ptr_fir_lms_coeffs_buffer_len.53 var=55) source () <77>;
|
||||
(ptr_fir_lms_coeffs_ptr_start.54 var=56) source () <78>;
|
||||
(__extDM_int64_.55 var=57) source () <79>;
|
||||
(__ptr_cSensor_32.57 var=60) const () <81>;
|
||||
(__ptr_accSensor_32.59 var=62) const () <83>;
|
||||
(__ptr_c_block_pre.61 var=64) const () <85>;
|
||||
(__ptr_acc_block_pre.63 var=66) const () <87>;
|
||||
(__ptr_ptr_fir_lms_delay_line.65 var=68) const () <89>;
|
||||
(__ct_0.75 var=77) const () <99>;
|
||||
(__la.77 var=78 stl=LR off=0) inp () <101>;
|
||||
(__la.78 var=78) deassign (__la.77) <102>;
|
||||
(cSensorSignal.80 var=79 stl=A off=0) inp () <104>;
|
||||
(accSensorSignal.83 var=80 stl=A off=1) inp () <107>;
|
||||
(output_mode.86 var=81 stl=RA off=0) inp () <110>;
|
||||
(cSensor.89 var=82 stl=A off=4) inp () <113>;
|
||||
(cSensor.90 var=82) deassign (cSensor.89) <114>;
|
||||
(accSensor.92 var=83 stl=A off=5) inp () <116>;
|
||||
(accSensor.93 var=83) deassign (accSensor.92) <117>;
|
||||
(out_16.95 var=84 stl=__spill_WDMA off=0) inp () <119>;
|
||||
(out_16.96 var=84) deassign (out_16.95) <120>;
|
||||
(__rd___sp.98 var=58) rd_res_reg (__R_SP.24 __sp.32) <122>;
|
||||
(__R_SP.102 var=26 __sp.103 var=34) wr_res_reg (__rt.2223 __sp.32) <126>;
|
||||
(__fch___extDM_int16_.246 var=141 __extDM_int16_.247 var=47 __vola.248 var=29) load (__M_SDMB.6 cSensor.90 __extDM_int16_.45 __vola.27) <270>;
|
||||
(__ct_16.250 var=143) const () <272>;
|
||||
(__M_WDMA.258 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.259 var=35) store (__tmp.2419 __ptr_cSensor_32.57 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.33) <280>;
|
||||
(__fch___extDM_int16_.265 var=156 __extDM_int16_.266 var=47 __vola.267 var=29) load (__M_SDMB.6 accSensor.93 __extDM_int16_.247 __vola.248) <286>;
|
||||
(__M_WDMA.277 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.278 var=36) store (__tmp.2424 __ptr_accSensor_32.59 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.34) <296>;
|
||||
(__M_WDMA.563 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564 var=37) store (__tmp.2419 __ptr_c_block_pre.61 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.35) <494>;
|
||||
(__M_WDMA.576 var=11 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.577 var=38) store (__tmp.2424 __ptr_acc_block_pre.63 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.36) <506>;
|
||||
(_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi.766 var=206) const () <608>;
|
||||
(__link.768 var=208) dmaddr__call_dmaddr_ (_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi.766) <610>;
|
||||
(__rt.2223 var=485) __Pvoid__pl___Pvoid_int18_ (__rd___sp.98 __ct_0S0.2412) <1909>;
|
||||
(__ct_0S0.2412 var=513) const () <2176>;
|
||||
(__ct_2.2418 var=520) const () <2187>;
|
||||
(__tmp.2419 var=145) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.246 __ct_16.250 __ct_2.2418) <2188>;
|
||||
(__tmp.2424 var=160) int72__shift_int72__int72__uint2_ (__fch___extDM_int16_.265 __ct_16.250 __ct_2.2418) <2196>;
|
||||
call {
|
||||
(__ptr_ptr_fir_lms_delay_line.760 var=67 stl=A off=4) assign (__ptr_ptr_fir_lms_delay_line.65) <602>;
|
||||
(__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.765 var=205 stl=RA off=0) assign (__tmp.2424) <607>;
|
||||
(__link.769 var=208 stl=LR off=0) assign (__link.768) <611>;
|
||||
(_ZL2mu.770 var=45 __extDM.771 var=32 __extDM_BufferPtr.772 var=42 __extDM_BufferPtrDMB.773 var=40 __extDM___PDMint32_.774 var=51 __extDM_int16_.775 var=47 __extDM_int32_.776 var=46 __extDM_int64_.777 var=57 __extDM_void.778 var=48 __extPM.779 var=33 __extPM_void.780 var=49 ptr_fir_lms_coeffs.781 var=41 ptr_fir_lms_coeffs_buffer_len.782 var=55 ptr_fir_lms_coeffs_ptr_current.783 var=53 ptr_fir_lms_coeffs_ptr_start.784 var=56 ptr_fir_lms_delay_line.785 var=39 ptr_fir_lms_delay_line_buffer_len.786 var=54 ptr_fir_lms_delay_line_ptr_current.787 var=50 ptr_fir_lms_delay_line_ptr_start.788 var=52 __vola.789 var=29) F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi (__link.769 __ptr_ptr_fir_lms_delay_line.760 __fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.765 _ZL2mu.43 __extDM.30 __extDM_BufferPtr.40 __extDM_BufferPtrDMB.38 __extDM___PDMint32_.49 __extDM_int16_.266 __extDM_int32_.44 __extDM_int64_.55 __extDM_void.46 __extPM.31 __extPM_void.47 ptr_fir_lms_coeffs.39 ptr_fir_lms_coeffs_buffer_len.53 ptr_fir_lms_coeffs_ptr_current.51 ptr_fir_lms_coeffs_ptr_start.54 ptr_fir_lms_delay_line.37 ptr_fir_lms_delay_line_buffer_len.52 ptr_fir_lms_delay_line_ptr_current.48 ptr_fir_lms_delay_line_ptr_start.50 __vola.267) <612>;
|
||||
} #14 off=1
|
||||
#624 off=2
|
||||
(__ptr_ptr_fir_lms_coeffs.67 var=70) const () <91>;
|
||||
(__ct_2.242 var=137) const () <266>;
|
||||
(__ct_0.761 var=202) const () <603>;
|
||||
(__fch_ptr_fir_lms_delay_line_ptr_current.799 var=212) load (__M_WDMB.10 __rt.2333 ptr_fir_lms_delay_line_ptr_current.787) <622>;
|
||||
(__fch_ptr_fir_lms_delay_line_ptr_start.804 var=216) load (__M_WDMB.10 __rt.2355 ptr_fir_lms_delay_line_ptr_start.788) <627>;
|
||||
(__fch_ptr_fir_lms_coeffs_ptr_current.809 var=220) load (__M_WDMA.9 __ptr_ptr_fir_lms_coeffs__a8.2209 ptr_fir_lms_coeffs_ptr_current.783) <632>;
|
||||
(__fch_ptr_fir_lms_delay_line_buffer_len.814 var=224) load (__M_WDMB.10 __rt.2377 ptr_fir_lms_delay_line_buffer_len.786) <637>;
|
||||
(__fch_ptr_fir_lms_coeffs_buffer_len.819 var=228) load (__M_WDMA.9 __ptr_ptr_fir_lms_coeffs.67 ptr_fir_lms_coeffs_buffer_len.782) <642>;
|
||||
(__ct_m4.2080 var=428) const () <1742>;
|
||||
(__ct_m1.2141 var=454) const () <1794>;
|
||||
(__vcnt.2142 var=453) __sint__pl___sint___sint (__fch_ptr_fir_lms_coeffs_buffer_len.819 __ct_m1.2141) <1796>;
|
||||
(__ct_1.2144 var=455) const () <1798>;
|
||||
(__vcnt.2145 var=453) __sint__pl___sint___sint (__vcnt.2440 __ct_1.2144) <1800>;
|
||||
(__cv.2146 var=456) uint16__uint16____sint (__vcnt.2145) <1801>;
|
||||
(__ptr_ptr_fir_lms_coeffs__a8.2209 var=482) const () <1865>;
|
||||
(__rt.2333 var=485) __Pvoid__pl___Pvoid_int18_ (__ptr_ptr_fir_lms_delay_line.65 __ct_8.2415) <2049>;
|
||||
(__rt.2355 var=485) __Pvoid__mi___Pvoid_int18_ (__rt.2333 __ct_4.2414) <2077>;
|
||||
(__rt.2377 var=485) __Pvoid__mi___Pvoid_int18_ (__rt.2355 __ct_4.2414) <2105>;
|
||||
(__rt.2399 var=485) __Pvoid__pl___Pvoid_int18_ (__ptr_ptr_fir_lms_coeffs.67 __ct_4.2414) <2133>;
|
||||
(__ct_4.2414 var=515) const () <2180>;
|
||||
(__ct_8.2415 var=516) const () <2182>;
|
||||
(__tmp.2429 var=537) int72__shift_int72__int72__uint2_ (__fch_ptr_fir_lms_delay_line_buffer_len.814 __ct_2.242 __ct_2.2418) <2204>;
|
||||
(__ct_1.2433 var=527) const () <2211>;
|
||||
(__tmp.2439 var=532) int72__shift_int72__int72__uint2_ (__vcnt.2142 __ct_1.2144 __ct_1.2433) <2220>;
|
||||
(__vcnt.2440 var=453) int32__extract_high_int72_ (__tmp.2439) <2221>;
|
||||
(__trgt.2448 var=547) const () <2312>;
|
||||
() void_doloop_uint16__uint16_ (__cv.2146 __trgt.2448) <2313>;
|
||||
(__vcnt.2449 var=548) undefined () <2314>;
|
||||
for {
|
||||
{
|
||||
(__inl_p_x0.883 var=97) entry (__inl_p_x0.1052 __fch_ptr_fir_lms_delay_line_ptr_current.799) <706>;
|
||||
(__inl_p_h.885 var=99) entry (__inl_p_h.1056 __fch_ptr_fir_lms_coeffs_ptr_current.809) <708>;
|
||||
(__inl_acc1_A.888 var=540) entry (__inl_acc1_A.1062 __ct_0.761) <711>;
|
||||
(__inl_acc1_B.889 var=541) entry (__inl_acc1_B.1064 __ct_0.761) <712>;
|
||||
} #17
|
||||
{
|
||||
(__fchtmp.924 var=237) load (__M_WDMB.10 __inl_p_x0.883 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <747>;
|
||||
(__fchtmp.925 var=238) load (__M_WDMA.9 __inl_p_h.885 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <748>;
|
||||
(__fchtmp.935 var=248) load (__M_WDMB.10 __inl_p_x0.2019 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <758>;
|
||||
(__fchtmp.936 var=249) load (__M_WDMA.9 __rt.2267 _ZL2mu.770 __extDM_int32_.776 ptr_fir_lms_coeffs_buffer_len.782 ptr_fir_lms_delay_line_buffer_len.786) <759>;
|
||||
(__inl_acc1_A.947 var=102) accum_t__pl_accum_t_accum_t (__inl_acc1_A.888 __tmp.2032) <770>;
|
||||
(__inl_acc1_B.949 var=103) accum_t__pl_accum_t_accum_t (__inl_acc1_B.889 __tmp.2037) <772>;
|
||||
(__tmp.950 var=263) __sint_rnd_saturate_accum_t (__inl_acc1_A.947) <773>;
|
||||
(__tmp.952 var=265) __sint_rnd_saturate_accum_t (__inl_acc1_B.949) <775>;
|
||||
(__inl_p_x0.2019 var=97) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.883 __ct_m4.2080 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2429) <1628>;
|
||||
(__inl_p_x0.2027 var=97) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.2019 __ct_m4.2080 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2429) <1639>;
|
||||
(__tmp.2032 var=259) int72__multss_int32__int32__uint1_ (__fchtmp.924 __fchtmp.925 __ct_0.75) <1647>;
|
||||
(__tmp.2037 var=261) int72__multss_int32__int32__uint1_ (__fchtmp.935 __fchtmp.936 __ct_0.75) <1655>;
|
||||
(__rt.2267 var=485) __Pvoid__pl___Pvoid_int18_ (__inl_p_h.885 __ct_4.2414) <1965>;
|
||||
(__rt.2289 var=485) __Pvoid__pl___Pvoid_int18_ (__rt.2267 __ct_4.2414) <1993>;
|
||||
} #412 off=3
|
||||
{
|
||||
() for_count (__vcnt.2449) <781>;
|
||||
(__inl_p_x0.1052 var=97 __inl_p_x0.1053 var=97) exit (__inl_p_x0.2027) <829>;
|
||||
(__inl_p_h.1056 var=99 __inl_p_h.1057 var=99) exit (__rt.2289) <831>;
|
||||
(__inl_acc1_A.1062 var=540 __inl_acc1_A.1063 var=540) exit (__tmp.950) <834>;
|
||||
(__inl_acc1_B.1064 var=541 __inl_acc1_B.1065 var=541) exit (__tmp.952) <835>;
|
||||
} #19
|
||||
} #16 rng=[1,65535]
|
||||
#103 off=4
|
||||
(__ptr_acc_block_filt.69 var=72) const () <93>;
|
||||
(__ptr_out_32.71 var=74) const () <95>;
|
||||
(__ptr_mu.73 var=76) const () <97>;
|
||||
(__inl_acc1_C.1134 var=111) accum_t__pl_accum_t_accum_t (__inl_acc1_A.1063 __inl_acc1_B.1065) <870>;
|
||||
(__tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1135 var=92) __sint_rnd_saturate_accum_t (__inl_acc1_C.1134) <871>;
|
||||
(__M_WDMB.1139 var=12 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.1140 var=43) store (__tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1135 __ptr_acc_block_filt.69 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.41) <875>;
|
||||
(__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.1144 var=279) load (__M_WDMA.9 __ptr_c_block_pre.61 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564) <879>;
|
||||
(__tmp.1149 var=284) __sint__mi___sint___sint (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.1144 __tmpb0_F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_.1135) <884>;
|
||||
(__M_WDMB.1153 var=12 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1154 var=44) store (__tmp.1149 __ptr_out_32.71 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.42) <888>;
|
||||
(__fch_ptr_fir_lms_coeffs_ptr_start.1170 var=295) load (__M_WDMA.9 __rt.2399 ptr_fir_lms_coeffs_ptr_start.784) <904>;
|
||||
(__fch__ZL2mu.1218 var=332) load (__M_WDMA.9 __ptr_mu.73 _ZL2mu.770) <952>;
|
||||
(__inl_prod.1220 var=125) __sint_rnd_saturate_accum_t (__inl_acc_C.2050) <954>;
|
||||
(__inl_p_x1.2045 var=120) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch_ptr_fir_lms_delay_line_ptr_current.799 __ct_m4.2080 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2429) <1666>;
|
||||
(__inl_acc_C.2050 var=124) int72__multss_int32__int32__uint1_ (__fch__ZL2mu.1218 __tmp.1149 __ct_0.75) <1674>;
|
||||
(__ct_m8.2081 var=429) const () <1744>;
|
||||
(__trgt.2450 var=549) const () <2315>;
|
||||
() void_doloop_uint16__uint16_ (__cv.2146 __trgt.2450) <2316>;
|
||||
(__vcnt.2451 var=550) undefined () <2317>;
|
||||
for {
|
||||
{
|
||||
(_ZL2mu.1240 var=45) entry (_ZL2mu.1385 _ZL2mu.770) <974>;
|
||||
(__extDM_int32_.1241 var=46) entry (__extDM_int32_.1387 __extDM_int32_.776) <975>;
|
||||
(ptr_fir_lms_delay_line_buffer_len.1249 var=54) entry (ptr_fir_lms_delay_line_buffer_len.1403 ptr_fir_lms_delay_line_buffer_len.786) <983>;
|
||||
(ptr_fir_lms_coeffs_buffer_len.1250 var=55) entry (ptr_fir_lms_coeffs_buffer_len.1405 ptr_fir_lms_coeffs_buffer_len.782) <984>;
|
||||
(__extDM_int64_.1252 var=57) entry (__extDM_int64_.1409 __extDM_int64_.777) <986>;
|
||||
(__inl_p_h0.1294 var=118) entry (__inl_p_h0.1493 __fch_ptr_fir_lms_coeffs_ptr_start.1170) <1028>;
|
||||
(__inl_p_x0.1295 var=119) entry (__inl_p_x0.1495 __fch_ptr_fir_lms_delay_line_ptr_current.799) <1029>;
|
||||
(__inl_p_x1.1296 var=120) entry (__inl_p_x1.1497 __inl_p_x1.2045) <1030>;
|
||||
} #22
|
||||
{
|
||||
(__fchtmp.1312 var=337) load (__M_LDMA.12 __inl_p_h0.1294 _ZL2mu.1240 __extDM_int32_.1241 __extDM_int64_.1252 ptr_fir_lms_coeffs_buffer_len.1250 ptr_fir_lms_delay_line_buffer_len.1249) <1046>;
|
||||
(__inl_h0.1314 var=127 __inl_h1.1315 var=128) void_lldecompose___ulonglong___sint___sint (__fchtmp.1312) <1048>;
|
||||
(__fchtmp.1318 var=343) load (__M_WDMB.10 __inl_p_x0.1295 _ZL2mu.1240 __extDM_int32_.1241 ptr_fir_lms_coeffs_buffer_len.1250 ptr_fir_lms_delay_line_buffer_len.1249) <1051>;
|
||||
(__inl_acc_A.1320 var=129) accum_t__pl_accum_t_accum_t (__inl_h0.1314 __tmp.2055) <1053>;
|
||||
(__fchtmp.1321 var=346) load (__M_WDMB.10 __inl_p_x1.1296 _ZL2mu.1240 __extDM_int32_.1241 ptr_fir_lms_coeffs_buffer_len.1250 ptr_fir_lms_delay_line_buffer_len.1249) <1054>;
|
||||
(__inl_acc_B.1323 var=130) accum_t__pl_accum_t_accum_t (__inl_h1.1315 __tmp.2060) <1056>;
|
||||
(__tmp.1336 var=361) __sint_rnd_saturate_accum_t (__inl_acc_A.1320) <1069>;
|
||||
(__tmp.1337 var=362) __sint_rnd_saturate_accum_t (__inl_acc_B.1323) <1070>;
|
||||
(__tmp.1338 var=363) __ulonglong_llcompose___sint___sint (__tmp.1336 __tmp.1337) <1071>;
|
||||
(__M_LDMA.1340 var=14 _ZL2mu.1341 var=45 __extDM_int32_.1342 var=46 __extDM_int64_.1343 var=57 ptr_fir_lms_coeffs_buffer_len.1344 var=55 ptr_fir_lms_delay_line_buffer_len.1345 var=54) store (__tmp.1338 __inl_p_h0.1294 _ZL2mu.1240 __extDM_int32_.1241 __extDM_int64_.1252 ptr_fir_lms_coeffs_buffer_len.1250 ptr_fir_lms_delay_line_buffer_len.1249) <1073>;
|
||||
(__tmp.2055 var=344) int72__multss_int32__int32__uint1_ (__inl_prod.1220 __fchtmp.1318 __ct_0.75) <1682>;
|
||||
(__tmp.2060 var=347) int72__multss_int32__int32__uint1_ (__inl_prod.1220 __fchtmp.1321 __ct_0.75) <1690>;
|
||||
(__inl_p_x0.2068 var=119) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x0.1295 __ct_m8.2081 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2429) <1701>;
|
||||
(__inl_p_x1.2076 var=120) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__inl_p_x1.1296 __ct_m8.2081 __fch_ptr_fir_lms_delay_line_ptr_start.804 __tmp.2429) <1712>;
|
||||
(__rt.2311 var=485) __Pvoid__pl___Pvoid_int18_ (__inl_p_h0.1294 __ct_8.2415) <2021>;
|
||||
} #482 off=5
|
||||
{
|
||||
() for_count (__vcnt.2451) <1081>;
|
||||
(_ZL2mu.1385 var=45 _ZL2mu.1386 var=45) exit (_ZL2mu.1341) <1098>;
|
||||
(__extDM_int32_.1387 var=46 __extDM_int32_.1388 var=46) exit (__extDM_int32_.1342) <1099>;
|
||||
(ptr_fir_lms_delay_line_buffer_len.1403 var=54 ptr_fir_lms_delay_line_buffer_len.1404 var=54) exit (ptr_fir_lms_delay_line_buffer_len.1345) <1107>;
|
||||
(ptr_fir_lms_coeffs_buffer_len.1405 var=55 ptr_fir_lms_coeffs_buffer_len.1406 var=55) exit (ptr_fir_lms_coeffs_buffer_len.1344) <1108>;
|
||||
(__extDM_int64_.1409 var=57 __extDM_int64_.1410 var=57) exit (__extDM_int64_.1343) <1110>;
|
||||
(__inl_p_h0.1493 var=118 __inl_p_h0.1494 var=118) exit (__rt.2311) <1152>;
|
||||
(__inl_p_x0.1495 var=119 __inl_p_x0.1496 var=119) exit (__inl_p_x0.2068) <1153>;
|
||||
(__inl_p_x1.1497 var=120 __inl_p_x1.1498 var=120) exit (__inl_p_x1.2076) <1154>;
|
||||
} #24
|
||||
} #21 rng=[1,65535]
|
||||
#36 off=6 nxt=-2
|
||||
(__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1716 var=382) load (__M_WDMB.10 __ptr_out_32.71 _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1154) <1359>;
|
||||
(__tmp.1721 var=387) __sint_rnd_saturate_accum_t (__tmp.2434) <1364>;
|
||||
(__tmp.1722 var=388) __sshort___sshort___sint (__tmp.1721) <1365>;
|
||||
(__M_SDMB.1728 var=8 __extDM_int16_.1729 var=47 __vola.1730 var=29) store (__tmp.1722 out_16.96 __extDM_int16_.775 __vola.789) <1371>;
|
||||
(__rd___sp.1917 var=58) rd_res_reg (__R_SP.24 __sp.103) <1471>;
|
||||
(__R_SP.1921 var=26 __sp.1922 var=34) wr_res_reg (__rt.2245 __sp.103) <1475>;
|
||||
() void_ret_dmaddr_ (__la.78) <1476>;
|
||||
() sink (__vola.1730) <1477>;
|
||||
() sink (__extDM.771) <1480>;
|
||||
() sink (__extPM.779) <1481>;
|
||||
() sink (__sp.1922) <1482>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32.259) <1483>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32.278) <1484>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre.564) <1485>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre.577) <1486>;
|
||||
() sink (ptr_fir_lms_delay_line.785) <1487>;
|
||||
() sink (__extDM_BufferPtrDMB.773) <1488>;
|
||||
() sink (ptr_fir_lms_coeffs.781) <1489>;
|
||||
() sink (__extDM_BufferPtr.772) <1490>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt.1140) <1491>;
|
||||
() sink (_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1154) <1492>;
|
||||
() sink (_ZL2mu.1386) <1493>;
|
||||
() sink (__extDM_int32_.1388) <1494>;
|
||||
() sink (__extDM_int16_.1729) <1495>;
|
||||
() sink (__extDM_void.778) <1496>;
|
||||
() sink (__extPM_void.780) <1497>;
|
||||
() sink (ptr_fir_lms_delay_line_ptr_current.787) <1498>;
|
||||
() sink (__extDM___PDMint32_.774) <1499>;
|
||||
() sink (ptr_fir_lms_delay_line_ptr_start.788) <1500>;
|
||||
() sink (ptr_fir_lms_coeffs_ptr_current.783) <1501>;
|
||||
() sink (ptr_fir_lms_delay_line_buffer_len.1404) <1502>;
|
||||
() sink (ptr_fir_lms_coeffs_buffer_len.1406) <1503>;
|
||||
() sink (ptr_fir_lms_coeffs_ptr_start.784) <1504>;
|
||||
() sink (__extDM_int64_.1410) <1505>;
|
||||
() sink (__ct_0.75) <1506>;
|
||||
(__rt.2245 var=485) __Pvoid__pl___Pvoid_int18_ (__rd___sp.1917 __ct_0s0.2413) <1937>;
|
||||
(__ct_0s0.2413 var=514) const () <2178>;
|
||||
(__tmp.2434 var=386) int72__shift_int72__int72__uint2_ (__fch__ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32.1716 __ct_16.250 __ct_1.2433) <2212>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,348:0,0);
|
||||
14 : (0,383:4,26);
|
||||
16 : (0,385:23,43);
|
||||
21 : (0,389:4,87);
|
||||
36 : (0,397:0,115);
|
||||
103 : (0,389:4,85);
|
||||
412 : (0,385:23,61);
|
||||
482 : (0,389:4,0);
|
||||
602 : (0,383:4,26);
|
||||
624 : (0,385:23,43);
|
||||
----------
|
||||
85 : (0,387:16,0);
|
||||
87 : (0,383:67,0);
|
||||
89 : (0,385:23,0);
|
||||
91 : (0,385:23,0);
|
||||
93 : (0,385:4,0);
|
||||
95 : (0,387:4,0);
|
||||
122 : (0,348:5,0);
|
||||
126 : (0,348:5,0);
|
||||
266 : (0,371:39,0);
|
||||
270 : (0,371:39,11);
|
||||
272 : (0,371:47,0);
|
||||
280 : (0,371:18,11);
|
||||
286 : (0,372:42,12);
|
||||
296 : (0,372:20,12);
|
||||
494 : (0,377:20,19);
|
||||
506 : (0,378:22,20);
|
||||
602 : (0,383:42,0);
|
||||
603 : (0,383:81,0);
|
||||
607 : (0,383:80,0);
|
||||
610 : (0,383:4,26);
|
||||
611 : (0,383:4,0);
|
||||
612 : (0,383:4,26);
|
||||
622 : (0,385:23,33);
|
||||
627 : (0,385:23,34);
|
||||
632 : (0,385:23,35);
|
||||
637 : (0,385:23,36);
|
||||
642 : (0,385:23,37);
|
||||
706 : (0,385:23,43);
|
||||
708 : (0,385:23,43);
|
||||
711 : (0,385:23,43);
|
||||
712 : (0,385:23,43);
|
||||
747 : (0,385:23,43);
|
||||
748 : (0,385:23,44);
|
||||
758 : (0,385:23,49);
|
||||
759 : (0,385:23,50);
|
||||
770 : (0,385:23,55);
|
||||
772 : (0,385:23,56);
|
||||
773 : (0,385:23,57);
|
||||
775 : (0,385:23,58);
|
||||
781 : (0,385:23,61);
|
||||
829 : (0,385:23,61);
|
||||
831 : (0,385:23,61);
|
||||
834 : (0,385:23,61);
|
||||
835 : (0,385:23,61);
|
||||
870 : (0,385:23,62);
|
||||
871 : (0,385:23,63);
|
||||
875 : (0,385:18,66);
|
||||
879 : (0,387:27,67);
|
||||
884 : (0,387:31,67);
|
||||
888 : (0,387:10,67);
|
||||
904 : (0,389:4,75);
|
||||
952 : (0,389:4,84);
|
||||
954 : (0,389:4,85);
|
||||
974 : (0,389:4,87);
|
||||
975 : (0,389:4,87);
|
||||
983 : (0,389:4,87);
|
||||
984 : (0,389:4,87);
|
||||
986 : (0,389:4,87);
|
||||
1028 : (0,389:4,87);
|
||||
1029 : (0,389:4,87);
|
||||
1030 : (0,389:4,87);
|
||||
1046 : (0,389:4,87);
|
||||
1048 : (0,389:4,87);
|
||||
1051 : (0,389:4,90);
|
||||
1053 : (0,389:4,90);
|
||||
1054 : (0,389:4,91);
|
||||
1056 : (0,389:4,91);
|
||||
1069 : (0,389:4,94);
|
||||
1070 : (0,389:4,94);
|
||||
1071 : (0,389:4,94);
|
||||
1073 : (0,389:4,94);
|
||||
1081 : (0,389:4,98);
|
||||
1098 : (0,389:4,98);
|
||||
1099 : (0,389:4,98);
|
||||
1107 : (0,389:4,98);
|
||||
1108 : (0,389:4,98);
|
||||
1110 : (0,389:4,98);
|
||||
1152 : (0,389:4,98);
|
||||
1153 : (0,389:4,98);
|
||||
1154 : (0,389:4,98);
|
||||
1359 : (0,394:48,105);
|
||||
1364 : (0,394:20,105);
|
||||
1365 : (0,394:18,105);
|
||||
1371 : (0,394:14,105);
|
||||
1471 : (0,397:0,0);
|
||||
1475 : (0,397:0,115);
|
||||
1476 : (0,397:0,115);
|
||||
1628 : (0,385:23,48);
|
||||
1639 : (0,385:23,54);
|
||||
1647 : (0,385:23,55);
|
||||
1655 : (0,385:23,56);
|
||||
1666 : (0,389:4,78);
|
||||
1674 : (0,389:4,84);
|
||||
1682 : (0,389:4,90);
|
||||
1690 : (0,389:4,91);
|
||||
1701 : (0,389:4,92);
|
||||
1712 : (0,389:4,93);
|
||||
1742 : (0,385:23,0);
|
||||
1744 : (0,389:4,0);
|
||||
1865 : (0,385:23,0);
|
||||
1909 : (0,348:5,0);
|
||||
1937 : (0,397:0,0);
|
||||
1965 : (0,385:23,0);
|
||||
1993 : (0,385:23,0);
|
||||
2021 : (0,389:4,0);
|
||||
2049 : (0,385:23,0);
|
||||
2077 : (0,385:23,0);
|
||||
2105 : (0,385:23,0);
|
||||
2133 : (0,389:4,0);
|
||||
2176 : (0,348:5,0);
|
||||
2178 : (0,397:0,0);
|
||||
2180 : (0,385:23,0);
|
||||
2182 : (0,389:4,0);
|
||||
2187 : (0,371:44,0);
|
||||
2188 : (0,371:44,11);
|
||||
2196 : (0,372:47,12);
|
||||
2204 : (0,385:23,48);
|
||||
2211 : (0,394:53,0);
|
||||
2212 : (0,394:53,105);
|
||||
2313 : (0,385:23,61);
|
||||
2316 : (0,389:4,98);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-154f66.#
Normal file
8
simulation/Release/chesswork/signal_path-154f66.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
454cbf759dc179bab963eec74c3b7ec9f827cdcb
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
cef764f6402a6eeb549cc520677fd8828baab91e
|
||||
71
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-154f66.o
Normal file
BIN
simulation/Release/chesswork/signal_path-154f66.o
Normal file
Binary file not shown.
216
simulation/Release/chesswork/signal_path-154f66.sfg
Normal file
216
simulation/Release/chesswork/signal_path-154f66.sfg
Normal file
@@ -0,0 +1,216 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_init_buffer(BufferPtr *, int *, int, int)
|
||||
F_Z15sig_init_bufferP9BufferPtrPiii : user_defined, called {
|
||||
fnm : "sig_init_buffer" 'int sig_init_buffer(BufferPtr *, int *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z15sig_init_bufferP9BufferPtrPiii typ=uint20_ bnd=e stl=PM tref=__sint_____PBufferPtr___P__sint___sint___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
37 : __extDM_BufferPtr_buffer_len typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtr_ptr_start typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_BufferPtr_ptr_current typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
45 : buffer typ=dmaddr_ bnd=p tref=__PBufferPtr__
|
||||
46 : buffer_start_add typ=dmaddr_ bnd=p tref=__P__sint__
|
||||
47 : length typ=int32_ bnd=p tref=__sint__
|
||||
48 : max_buffer_len typ=int32_ bnd=p tref=__sint__
|
||||
54 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
65 : __tmp typ=bool bnd=m
|
||||
72 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
76 : __tmp typ=bool bnd=m
|
||||
92 : __iv1_i typ=dmaddr_ bnd=m
|
||||
95 : __cv typ=uint16_ bnd=m
|
||||
103 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
127 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
128 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
129 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
133 : __tmp typ=uint3_ bnd=m
|
||||
138 : __tmp typ=uint3_ bnd=m
|
||||
148 : __either typ=bool bnd=m
|
||||
149 : __trgt typ=int10_ val=0j bnd=m
|
||||
150 : __trgt typ=int10_ val=0j bnd=m
|
||||
151 : __trgt typ=int10_ val=0j bnd=m
|
||||
152 : __trgt typ=int10_ val=0j bnd=m
|
||||
153 : __trgt typ=uint16_ val=0j bnd=m
|
||||
154 : __vcnt typ=uint16_ bnd=m
|
||||
]
|
||||
F_Z15sig_init_bufferP9BufferPtrPiii {
|
||||
#239 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_int32_.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtr_buffer_len.35 var=37) source () <59>;
|
||||
(__extDM_BufferPtr_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtr_ptr_current.38 var=40) source () <62>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.46 var=45 stl=A off=0) inp () <70>;
|
||||
(buffer.47 var=45) deassign (buffer.46) <71>;
|
||||
(buffer_start_add.49 var=46 stl=A off=1) inp () <73>;
|
||||
(buffer_start_add.50 var=46) deassign (buffer_start_add.49) <74>;
|
||||
(length.52 var=47 stl=RA off=1) inp () <76>;
|
||||
(length.53 var=47) deassign (length.52) <77>;
|
||||
(max_buffer_len.55 var=48 stl=RB off=0) inp () <79>;
|
||||
(max_buffer_len.56 var=48) deassign (max_buffer_len.55) <80>;
|
||||
(__rd___sp.58 var=41) rd_res_reg (__R_SP.24 __sp.32) <82>;
|
||||
(__R_SP.62 var=26 __sp.63 var=34) wr_res_reg (__rt.274 __sp.32) <86>;
|
||||
(__ct_0.66 var=54) const () <90>;
|
||||
(__M_WDMA.69 var=11 __extDM_BufferPtr_buffer_len.70 var=37) store (length.53 buffer.47 __extDM_BufferPtr_buffer_len.35) <93>;
|
||||
(__M_WDMA.74 var=11 __extDM_BufferPtr_ptr_start.75 var=38) store (buffer_start_add.50 __rt.340 __extDM_BufferPtr_ptr_start.36) <97>;
|
||||
(__M_WDMA.79 var=11 __extDM_BufferPtr_ptr_current.80 var=40) store (buffer_start_add.50 __rt.362 __extDM_BufferPtr_ptr_current.38) <101>;
|
||||
(__rt.274 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.58 __ct_0S0.375) <320>;
|
||||
(__rt.340 var=103) __Pvoid__pl___Pvoid_int18_ (buffer.47 __ct_4.377) <404>;
|
||||
(__rt.362 var=103) __Pvoid__pl___Pvoid_int18_ (__rt.340 __ct_4.377) <432>;
|
||||
(__ct_0S0.375 var=127) const () <457>;
|
||||
(__ct_4.377 var=129) const () <461>;
|
||||
(__tmp.380 var=133) uint3__cmp_int72__int72_ (length.53 __ct_0.66) <466>;
|
||||
(__tmp.393 var=65) bool_nplus_uint3_ (__tmp.380) <500>;
|
||||
(__trgt.396 var=149) const () <511>;
|
||||
() void_jump_bool_int10_ (__tmp.393 __trgt.396) <512>;
|
||||
(__either.397 var=148) undefined () <513>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.397) <126>;
|
||||
() chess_frequent_else () <127>;
|
||||
() chess_rear_then () <514>;
|
||||
} #5
|
||||
{
|
||||
(__trgt.398 var=150) const () <515>;
|
||||
() void_jump_int10_ (__trgt.398) <516>;
|
||||
} #11 off=4
|
||||
{
|
||||
#30 off=1
|
||||
(__cv.254 var=95) uint16__uint16____sint (length.53) <288>;
|
||||
(__trgt.402 var=153) const () <522>;
|
||||
() void_doloop_uint16__uint16_ (__cv.254 __trgt.402) <523>;
|
||||
(__vcnt.403 var=154) undefined () <524>;
|
||||
for {
|
||||
{
|
||||
(__extDM_int32_.112 var=36) entry (__extDM_int32_.152 __extDM_int32_.34) <135>;
|
||||
(__extDM_BufferPtr_buffer_len.113 var=37) entry (__extDM_BufferPtr_buffer_len.154 __extDM_BufferPtr_buffer_len.70) <136>;
|
||||
(__iv1_i.245 var=92) entry (__iv1_i.246 buffer_start_add.50) <279>;
|
||||
} #8
|
||||
{
|
||||
(__M_WDMA.131 var=11 __extDM_BufferPtr_buffer_len.132 var=37 __extDM_int32_.133 var=36) store (__ct_0.66 __iv1_i.245 __extDM_BufferPtr_buffer_len.113 __extDM_int32_.112) <154>;
|
||||
(__rt.318 var=103) __Pvoid__pl___Pvoid_int18_ (__iv1_i.245 __ct_4.377) <376>;
|
||||
} #173 off=2
|
||||
{
|
||||
() for_count (__vcnt.403) <159>;
|
||||
(__extDM_int32_.152 var=36 __extDM_int32_.153 var=36) exit (__extDM_int32_.133) <167>;
|
||||
(__extDM_BufferPtr_buffer_len.154 var=37 __extDM_BufferPtr_buffer_len.155 var=37) exit (__extDM_BufferPtr_buffer_len.132) <168>;
|
||||
(__iv1_i.246 var=92 __iv1_i.247 var=92) exit (__rt.318) <280>;
|
||||
} #10
|
||||
} #7 rng=[1,65535]
|
||||
} #6
|
||||
{
|
||||
(__extDM_int32_.178 var=36) merge (__extDM_int32_.34 __extDM_int32_.153) <180>;
|
||||
(__extDM_BufferPtr_buffer_len.179 var=37) merge (__extDM_BufferPtr_buffer_len.70 __extDM_BufferPtr_buffer_len.155) <181>;
|
||||
} #12
|
||||
} #4
|
||||
#242 off=5
|
||||
(__tmp.385 var=138) uint3__cmp_int72__int72_ (length.53 max_buffer_len.56) <474>;
|
||||
(__tmp.386 var=76) bool_neg_uint3_ (__tmp.385) <475>;
|
||||
(__trgt.399 var=151) const () <517>;
|
||||
() void_jump_bool_int10_ (__tmp.386 __trgt.399) <518>;
|
||||
(__either.400 var=148) undefined () <519>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.400) <205>;
|
||||
} #15
|
||||
{
|
||||
} #16 off=7
|
||||
{
|
||||
(__ct_1.134 var=72) const () <155>;
|
||||
(__trgt.401 var=152) const () <520>;
|
||||
() void_jump_int10_ (__trgt.401) <521>;
|
||||
} #17 off=6
|
||||
{
|
||||
(__rt.207 var=44) merge (__ct_0.66 __ct_1.134) <210>;
|
||||
} #18
|
||||
} #14
|
||||
#20 off=8 nxt=-2
|
||||
(__rd___sp.208 var=41) rd_res_reg (__R_SP.24 __sp.63) <211>;
|
||||
(__R_SP.212 var=26 __sp.213 var=34) wr_res_reg (__rt.296 __sp.63) <215>;
|
||||
() void_ret_dmaddr_ (__la.43) <216>;
|
||||
(__rt.214 var=44 stl=RA off=0) assign (__rt.207) <217>;
|
||||
() out (__rt.214) <218>;
|
||||
() sink (__sp.213) <224>;
|
||||
() sink (__extDM_int32_.178) <226>;
|
||||
() sink (__extDM_BufferPtr_buffer_len.179) <227>;
|
||||
() sink (__extDM_BufferPtr_ptr_start.75) <228>;
|
||||
() sink (__extDM_BufferPtr_ptr_current.80) <230>;
|
||||
() sink (__ct_0.40) <231>;
|
||||
(__rt.296 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.208 __ct_0s0.376) <348>;
|
||||
(__ct_0s0.376 var=128) const () <459>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,71:0,0);
|
||||
4 : (0,76:4,5);
|
||||
6 : (0,76:4,6);
|
||||
7 : (0,76:4,6);
|
||||
11 : (0,76:4,13);
|
||||
14 : (0,79:4,16);
|
||||
16 : (0,83:8,17);
|
||||
17 : (0,80:8,21);
|
||||
20 : (0,79:4,26);
|
||||
173 : (0,76:37,6);
|
||||
239 : (0,76:4,5);
|
||||
242 : (0,79:14,16);
|
||||
----------
|
||||
82 : (0,71:4,0);
|
||||
86 : (0,71:4,0);
|
||||
90 : (0,72:10,0);
|
||||
93 : (0,72:10,1);
|
||||
97 : (0,73:10,2);
|
||||
101 : (0,74:10,3);
|
||||
126 : (0,76:4,5);
|
||||
135 : (0,76:4,6);
|
||||
136 : (0,76:4,6);
|
||||
154 : (0,77:24,6);
|
||||
155 : (0,76:33,0);
|
||||
159 : (0,76:4,11);
|
||||
167 : (0,76:4,11);
|
||||
168 : (0,76:4,11);
|
||||
180 : (0,76:4,15);
|
||||
181 : (0,76:4,15);
|
||||
205 : (0,79:4,16);
|
||||
210 : (0,79:4,25);
|
||||
211 : (0,79:4,0);
|
||||
215 : (0,79:4,26);
|
||||
216 : (0,79:4,26);
|
||||
217 : (0,79:4,0);
|
||||
320 : (0,71:4,0);
|
||||
348 : (0,79:4,0);
|
||||
404 : (0,73:10,0);
|
||||
432 : (0,74:10,0);
|
||||
457 : (0,71:4,0);
|
||||
459 : (0,79:4,0);
|
||||
466 : (0,76:4,5);
|
||||
474 : (0,79:14,16);
|
||||
475 : (0,79:14,16);
|
||||
500 : (0,76:4,5);
|
||||
512 : (0,76:4,5);
|
||||
518 : (0,79:4,16);
|
||||
523 : (0,76:4,11);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-352f49.#
Normal file
8
simulation/Release/chesswork/signal_path-352f49.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
ad94f23a9ebcbc49d7cf7e855204645158988be1
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
b6139837f6ca35c36b0c65fc4fb39c9f43e36de9
|
||||
109
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-352f49.o
Normal file
BIN
simulation/Release/chesswork/signal_path-352f49.o
Normal file
Binary file not shown.
115
simulation/Release/chesswork/signal_path-352f49.sfg
Normal file
115
simulation/Release/chesswork/signal_path-352f49.sfg
Normal file
@@ -0,0 +1,115 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_cirular_buffer_ptr_increment_DMB(BufferPtrDMB *, int)
|
||||
F_Z36sig_cirular_buffer_ptr_increment_DMBP12BufferPtrDMBi : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_increment_DMB" 'void sig_cirular_buffer_ptr_increment_DMB(BufferPtrDMB *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z36sig_cirular_buffer_ptr_increment_DMBP12BufferPtrDMBi typ=uint20_ bnd=e stl=PM tref=void_____PBufferPtrDMB___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_BufferPtrDMB_ptr_current typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtrDMB_ptr_start typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_BufferPtrDMB_buffer_len typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : buffer typ=dmaddr_ bnd=p tref=__PBufferPtrDMB__
|
||||
45 : i_incr typ=int32_ bnd=p tref=__sint__
|
||||
52 : __fch___extDM_BufferPtrDMB_ptr_current typ=dmaddr_ bnd=m
|
||||
59 : __fch___extDM_BufferPtrDMB_ptr_start typ=dmaddr_ bnd=m
|
||||
63 : __fch___extDM_BufferPtrDMB_buffer_len typ=int32_ bnd=m
|
||||
67 : __tmp typ=dmaddr_ bnd=m
|
||||
90 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
93 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
118 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
119 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
122 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
124 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
128 : __ct_2 typ=uint2_ val=2f bnd=m
|
||||
133 : __tmp typ=int18_ bnd=m
|
||||
134 : __tmp typ=int18_ bnd=m
|
||||
]
|
||||
F_Z36sig_cirular_buffer_ptr_increment_DMBP12BufferPtrDMBi {
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_BufferPtrDMB_ptr_current.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtrDMB_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.37 var=39) source () <61>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.45 var=44 stl=A off=0) inp () <69>;
|
||||
(buffer.46 var=44) deassign (buffer.45) <70>;
|
||||
(i_incr.48 var=45 stl=RA off=0) inp () <72>;
|
||||
(i_incr.49 var=45) deassign (i_incr.48) <73>;
|
||||
(__rd___sp.51 var=41) rd_res_reg (__R_SP.24 __sp.32) <75>;
|
||||
(__R_SP.55 var=26 __sp.56 var=34) wr_res_reg (__rt.133 __sp.32) <79>;
|
||||
(__fch___extDM_BufferPtrDMB_ptr_current.60 var=52) load (__M_WDMA.9 __rt.155 __extDM_BufferPtrDMB_ptr_current.34) <84>;
|
||||
(__fch___extDM_BufferPtrDMB_ptr_start.67 var=59) load (__M_WDMA.9 __rt.199 __extDM_BufferPtrDMB_ptr_start.36) <91>;
|
||||
(__fch___extDM_BufferPtrDMB_buffer_len.71 var=63) load (__M_WDMA.9 __rt.221 __extDM_BufferPtrDMB_buffer_len.37) <95>;
|
||||
(__M_WDMA.79 var=11 __extDM_BufferPtrDMB_ptr_current.80 var=36) store (__tmp.110 __rt.243 __extDM_BufferPtrDMB_ptr_current.34) <103>;
|
||||
(__rd___sp.81 var=41) rd_res_reg (__R_SP.24 __sp.56) <104>;
|
||||
(__R_SP.85 var=26 __sp.86 var=34) wr_res_reg (__rt.177 __sp.56) <108>;
|
||||
() void_ret_dmaddr_ (__la.43) <109>;
|
||||
() sink (__sp.86) <115>;
|
||||
() sink (__extDM_BufferPtrDMB_ptr_current.80) <117>;
|
||||
() sink (__ct_0.40) <122>;
|
||||
(__tmp.110 var=67) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch___extDM_BufferPtrDMB_ptr_current.60 __tmp.266 __fch___extDM_BufferPtrDMB_ptr_start.67 __tmp.271) <155>;
|
||||
(__ct_2.119 var=90) const () <175>;
|
||||
(__rt.133 var=93) __Pvoid__pl___Pvoid_int18_ (__rd___sp.51 __ct_0S0.256) <201>;
|
||||
(__rt.155 var=93) __Pvoid__pl___Pvoid_int18_ (buffer.46 __ct_8.257) <229>;
|
||||
(__rt.177 var=93) __Pvoid__pl___Pvoid_int18_ (__rd___sp.81 __ct_0s0.260) <257>;
|
||||
(__rt.199 var=93) __Pvoid__mi___Pvoid_int18_ (__rt.155 __ct_4.262) <285>;
|
||||
(__rt.221 var=93) __Pvoid__mi___Pvoid_int18_ (__rt.199 __ct_4.262) <313>;
|
||||
(__rt.243 var=93) __Pvoid__pl___Pvoid_int18_ (__rt.221 __ct_8.257) <341>;
|
||||
(__ct_0S0.256 var=118) const () <367>;
|
||||
(__ct_8.257 var=119) const () <369>;
|
||||
(__ct_0s0.260 var=122) const () <375>;
|
||||
(__ct_4.262 var=124) const () <379>;
|
||||
(__ct_2.265 var=128) const () <384>;
|
||||
(__tmp.266 var=133) int72__shift_int72__int72__uint2_ (i_incr.49 __ct_2.119 __ct_2.265) <385>;
|
||||
(__tmp.271 var=134) int72__shift_int72__int72__uint2_ (__fch___extDM_BufferPtrDMB_buffer_len.71 __ct_2.119 __ct_2.265) <393>;
|
||||
} #5 off=0 nxt=-2
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
5 : (0,109:0,2);
|
||||
----------
|
||||
75 : (0,107:5,0);
|
||||
79 : (0,107:5,0);
|
||||
84 : (0,108:43,1);
|
||||
91 : (0,108:72,1);
|
||||
95 : (0,108:91,1);
|
||||
103 : (0,108:10,1);
|
||||
104 : (0,109:0,0);
|
||||
108 : (0,109:0,2);
|
||||
109 : (0,109:0,2);
|
||||
155 : (0,108:26,1);
|
||||
175 : (0,108:58,0);
|
||||
201 : (0,107:5,0);
|
||||
229 : (0,108:43,1);
|
||||
257 : (0,109:0,0);
|
||||
285 : (0,108:72,0);
|
||||
341 : (0,108:43,0);
|
||||
367 : (0,107:5,0);
|
||||
369 : (0,108:43,0);
|
||||
375 : (0,109:0,0);
|
||||
379 : (0,108:72,0);
|
||||
384 : (0,108:58,0);
|
||||
385 : (0,108:58,1);
|
||||
393 : (0,108:91,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-530a42.#
Normal file
8
simulation/Release/chesswork/signal_path-530a42.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
d5b4d9c0123aad702011823a9e5239cc1db9d199
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
4bb732fadaeebe782ad161865c598024b80ec94c
|
||||
204
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-530a42.o
Normal file
BIN
simulation/Release/chesswork/signal_path-530a42.o
Normal file
Binary file not shown.
137
simulation/Release/chesswork/signal_path-530a42.sfg
Normal file
137
simulation/Release/chesswork/signal_path-530a42.sfg
Normal file
@@ -0,0 +1,137 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_calc_weight(SingleSignalPath *, int)
|
||||
F_Z15sig_calc_weightP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_calc_weight" 'int sig_calc_weight(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z15sig_calc_weightP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___3
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_SingleSignalPath_weight_actived typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath_weight typ=int8_ bnd=b stl=DM
|
||||
39 : __rd___sp typ=dmaddr_ bnd=m
|
||||
40 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
41 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
42 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
44 : x typ=int32_ bnd=p tref=__sint__
|
||||
48 : acc typ=int72_ bnd=m lscp=144 tref=accum_t__
|
||||
52 : __fch___extDM_SingleSignalPath_weight_actived typ=int32_ bnd=m
|
||||
53 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
55 : __tmp typ=bool bnd=m
|
||||
59 : __fch___extDM_SingleSignalPath_weight typ=int32_ bnd=m
|
||||
77 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
100 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
101 : __ct_132 typ=int18_ val=132f bnd=m
|
||||
104 : __ct_136 typ=int18_ val=136f bnd=m
|
||||
107 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
111 : __tmp typ=uint3_ bnd=m
|
||||
121 : __either typ=bool bnd=m
|
||||
122 : __trgt typ=int10_ val=0j bnd=m
|
||||
123 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z15sig_calc_weightP16SingleSignalPathi {
|
||||
#194 off=0
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath_weight_actived.34 var=36) source () <58>;
|
||||
(__extDM_SingleSignalPath_weight.36 var=38) source () <60>;
|
||||
(__ct_0.38 var=40) const () <62>;
|
||||
(__la.40 var=41 stl=LR off=0) inp () <64>;
|
||||
(__la.41 var=41) deassign (__la.40) <65>;
|
||||
(signal.44 var=43 stl=A off=0) inp () <68>;
|
||||
(signal.45 var=43) deassign (signal.44) <69>;
|
||||
(x.47 var=44 stl=RA off=1) inp () <71>;
|
||||
(x.48 var=44) deassign (x.47) <72>;
|
||||
(__rd___sp.50 var=39) rd_res_reg (__R_SP.24 __sp.32) <74>;
|
||||
(__R_SP.54 var=26 __sp.55 var=34) wr_res_reg (__rt.133 __sp.32) <78>;
|
||||
(__fch___extDM_SingleSignalPath_weight_actived.60 var=52) load (__M_WDMA.9 __rt.155 __extDM_SingleSignalPath_weight_actived.34) <84>;
|
||||
(__ct_0.61 var=53) const () <85>;
|
||||
(__rt.133 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.50 __ct_0S0.212) <200>;
|
||||
(__rt.155 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_132.213) <228>;
|
||||
(__ct_0S0.212 var=100) const () <309>;
|
||||
(__ct_132.213 var=101) const () <311>;
|
||||
(__tmp.222 var=111) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_weight_actived.60 __ct_0.61) <328>;
|
||||
(__tmp.223 var=55) bool_equal_uint3_ (__tmp.222) <329>;
|
||||
(__trgt.231 var=122) const () <363>;
|
||||
() void_jump_bool_int10_ (__tmp.223 __trgt.231) <364>;
|
||||
(__either.232 var=121) undefined () <365>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.232) <103>;
|
||||
} #5
|
||||
{
|
||||
} #6 off=2
|
||||
{
|
||||
(__fch___extDM_SingleSignalPath_weight.83 var=59) load (__M_WDMA.9 __rt.177 __extDM_SingleSignalPath_weight.36) <108>;
|
||||
(__rt.85 var=42) __sint_rnd_saturate_accum_t (acc.115) <110>;
|
||||
(acc.115 var=48) int72__multss_int32__int32__uint1_ (x.48 __fch___extDM_SingleSignalPath_weight.83 __ct_0.38) <161>;
|
||||
(__rt.177 var=77) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_136.216) <256>;
|
||||
(__ct_136.216 var=104) const () <317>;
|
||||
(__trgt.233 var=123) const () <366>;
|
||||
() void_jump_int10_ (__trgt.233) <367>;
|
||||
} #144 off=1
|
||||
{
|
||||
(__rt.86 var=42) merge (x.48 __rt.85) <111>;
|
||||
} #8
|
||||
} #4
|
||||
#10 off=3 nxt=-2
|
||||
(__rd___sp.88 var=39) rd_res_reg (__R_SP.24 __sp.55) <113>;
|
||||
(__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.199 __sp.55) <117>;
|
||||
() void_ret_dmaddr_ (__la.41) <118>;
|
||||
(__rt.94 var=42 stl=RA off=0) assign (__rt.86) <119>;
|
||||
() out (__rt.94) <120>;
|
||||
() sink (__sp.93) <126>;
|
||||
() sink (__ct_0.38) <131>;
|
||||
(__rt.199 var=77) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.219) <284>;
|
||||
(__ct_0s0.219 var=107) const () <323>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,204:0,0);
|
||||
4 : (0,205:4,1);
|
||||
6 : (0,205:37,2);
|
||||
10 : (0,210:4,11);
|
||||
144 : (0,210:11,7);
|
||||
194 : (0,205:31,1);
|
||||
----------
|
||||
74 : (0,204:4,0);
|
||||
78 : (0,204:4,0);
|
||||
84 : (0,205:14,1);
|
||||
85 : (0,205:34,0);
|
||||
103 : (0,205:4,1);
|
||||
108 : (0,208:38,6);
|
||||
110 : (0,210:11,7);
|
||||
111 : (0,205:4,10);
|
||||
113 : (0,210:4,0);
|
||||
117 : (0,210:4,11);
|
||||
118 : (0,210:4,11);
|
||||
119 : (0,210:4,0);
|
||||
161 : (0,208:18,6);
|
||||
200 : (0,204:4,0);
|
||||
228 : (0,205:14,1);
|
||||
256 : (0,208:38,6);
|
||||
284 : (0,210:4,0);
|
||||
309 : (0,204:4,0);
|
||||
311 : (0,205:14,0);
|
||||
317 : (0,208:38,0);
|
||||
323 : (0,210:4,0);
|
||||
328 : (0,205:31,1);
|
||||
329 : (0,205:31,1);
|
||||
364 : (0,205:4,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-6fcf7f.#
Normal file
8
simulation/Release/chesswork/signal_path-6fcf7f.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
57cf3fdd8d7def6492095f180e9539315d131531
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
da7a8c19e98dc87d8274bee4a21dcd27ad1cbf24
|
||||
152
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-6fcf7f.o
Normal file
BIN
simulation/Release/chesswork/signal_path-6fcf7f.o
Normal file
Binary file not shown.
148
simulation/Release/chesswork/signal_path-6fcf7f.sfg
Normal file
148
simulation/Release/chesswork/signal_path-6fcf7f.sfg
Normal file
@@ -0,0 +1,148 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_init_delay(SingleSignalPath *, int)
|
||||
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! int sig_init_buffer(BufferPtr *, int *, int, int)
|
||||
F_Z15sig_init_bufferP9BufferPtrPiii : user_defined, called {
|
||||
fnm : "sig_init_buffer" 'int sig_init_buffer(BufferPtr *, int *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z14sig_init_delayP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint__
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
|
||||
36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
|
||||
37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath__delay_buffer typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
41 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
42 : __rd___sp typ=dmaddr_ bnd=m
|
||||
43 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
44 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
45 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
46 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
47 : n_delay typ=int32_ bnd=p tref=__sint__
|
||||
53 : __tmp typ=dmaddr_ bnd=m
|
||||
56 : __tmp typ=dmaddr_ bnd=m
|
||||
57 : __ct_16 typ=int32_ val=16f bnd=m
|
||||
58 : __ct typ=int32_ bnd=m
|
||||
59 : _Z15sig_init_bufferP9BufferPtrPiii typ=dmaddr_ val=0r bnd=m
|
||||
62 : __tmp typ=int32_ bnd=m
|
||||
76 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
99 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
100 : __ct_116 typ=int18_ val=116f bnd=m
|
||||
103 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
105 : __ct_64 typ=int18_ val=64f bnd=m
|
||||
]
|
||||
F_Z14sig_init_delayP16SingleSignalPathi {
|
||||
#142 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath.33 var=35) source () <57>;
|
||||
(__extDM_SingleSignalPath_delay_buffer.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtr.35 var=37) source () <59>;
|
||||
(__extDM_SingleSignalPath__delay_buffer.36 var=38) source () <60>;
|
||||
(__extDM_int32_.37 var=39) source () <61>;
|
||||
(__extDM_void.38 var=40) source () <62>;
|
||||
(__extPM_void.39 var=41) source () <63>;
|
||||
(__ct_0.41 var=43) const () <65>;
|
||||
(__la.43 var=44 stl=LR off=0) inp () <67>;
|
||||
(__la.44 var=44) deassign (__la.43) <68>;
|
||||
(signal.47 var=46 stl=A off=0) inp () <71>;
|
||||
(signal.48 var=46) deassign (signal.47) <72>;
|
||||
(n_delay.50 var=47 stl=RA off=1) inp () <74>;
|
||||
(n_delay.51 var=47) deassign (n_delay.50) <75>;
|
||||
(__rd___sp.53 var=42) rd_res_reg (__R_SP.24 __sp.32) <77>;
|
||||
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.132 __sp.32) <81>;
|
||||
(__ct_16.68 var=57) const () <92>;
|
||||
(_Z15sig_init_bufferP9BufferPtrPiii.71 var=59) const () <95>;
|
||||
(__rd___sp.88 var=42) rd_res_reg (__R_SP.24 __sp.58) <102>;
|
||||
(__R_SP.92 var=26 __sp.93 var=34) wr_res_reg (__rt.176 __sp.58) <106>;
|
||||
(__rt.132 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.211) <192>;
|
||||
(__rt.154 var=76) __Pvoid__pl___Pvoid_int18_ (signal.48 __ct_116.212) <220>;
|
||||
(__rt.176 var=76) __Pvoid__pl___Pvoid_int18_ (__rd___sp.88 __ct_0s0.215) <248>;
|
||||
(__rt.198 var=76) __Pvoid__mi___Pvoid_int18_ (__rt.154 __ct_64.217) <276>;
|
||||
(__ct_0S0.211 var=99) const () <303>;
|
||||
(__ct_116.212 var=100) const () <305>;
|
||||
(__ct_0s0.215 var=103) const () <311>;
|
||||
(__ct_64.217 var=105) const () <315>;
|
||||
() void_jump_dmaddr_ (_Z15sig_init_bufferP9BufferPtrPiii.71) <339>;
|
||||
call {
|
||||
(__tmp.62 var=53 stl=A off=0) assign (__rt.154) <86>;
|
||||
(__tmp.66 var=56 stl=A off=1) assign (__rt.198) <90>;
|
||||
(n_delay.67 var=47 stl=RA off=1) assign (n_delay.51) <91>;
|
||||
(__ct.70 var=58 stl=RB off=0) assign (__ct_16.68) <94>;
|
||||
(__la.74 var=44 stl=LR off=0) assign (__la.44) <98>;
|
||||
(__tmp.75 var=62 stl=RA off=0 __extDM.78 var=32 __extDM_BufferPtr.79 var=37 __extDM_SingleSignalPath.80 var=35 __extDM_SingleSignalPath__delay_buffer.81 var=38 __extDM_SingleSignalPath_delay_buffer.82 var=36 __extDM_int32_.83 var=39 __extDM_void.84 var=40 __extPM.85 var=33 __extPM_void.86 var=41 __vola.87 var=29) F_Z15sig_init_bufferP9BufferPtrPiii (__la.74 __tmp.62 __tmp.66 n_delay.67 __ct.70 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath__delay_buffer.36 __extDM_SingleSignalPath_delay_buffer.34 __extDM_int32_.37 __extDM_void.38 __extPM.31 __extPM_void.39 __vola.27) <99>;
|
||||
(__tmp.76 var=62) deassign (__tmp.75) <100>;
|
||||
} #4 off=1
|
||||
#6 off=2 nxt=-2
|
||||
(__rt.94 var=45 stl=RA off=0) assign (__tmp.76) <108>;
|
||||
() out (__rt.94) <109>;
|
||||
() sink (__vola.87) <110>;
|
||||
() sink (__extDM.78) <113>;
|
||||
() sink (__extPM.85) <114>;
|
||||
() sink (__sp.93) <115>;
|
||||
() sink (__extDM_SingleSignalPath.80) <116>;
|
||||
() sink (__extDM_SingleSignalPath_delay_buffer.82) <117>;
|
||||
() sink (__extDM_BufferPtr.79) <118>;
|
||||
() sink (__extDM_SingleSignalPath__delay_buffer.81) <119>;
|
||||
() sink (__extDM_int32_.83) <120>;
|
||||
() sink (__extDM_void.84) <121>;
|
||||
() sink (__extPM_void.86) <122>;
|
||||
() sink (__ct_0.41) <123>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,152:0,0);
|
||||
4 : (0,153:11,1);
|
||||
6 : (0,153:4,1);
|
||||
142 : (0,153:4,1);
|
||||
----------
|
||||
77 : (0,152:4,0);
|
||||
81 : (0,152:4,0);
|
||||
86 : (0,153:34,0);
|
||||
90 : (0,153:56,0);
|
||||
91 : (0,153:73,0);
|
||||
92 : (0,153:82,0);
|
||||
94 : (0,153:82,0);
|
||||
98 : (0,153:11,0);
|
||||
99 : (0,153:11,1);
|
||||
102 : (0,153:4,0);
|
||||
106 : (0,153:4,1);
|
||||
108 : (0,153:26,0);
|
||||
192 : (0,152:4,0);
|
||||
220 : (0,153:34,1);
|
||||
248 : (0,153:4,0);
|
||||
276 : (0,153:56,0);
|
||||
303 : (0,152:4,0);
|
||||
305 : (0,153:34,0);
|
||||
311 : (0,153:4,0);
|
||||
315 : (0,153:56,0);
|
||||
339 : (0,153:11,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-9c02ae.#
Normal file
8
simulation/Release/chesswork/signal_path-9c02ae.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
48e27357cf6b74d9a9ddfe61cbe4d757b31f02a7
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
4002b21ff0f8102d02854cc902593f4f886be97b
|
||||
309
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-9c02ae.o
Normal file
BIN
simulation/Release/chesswork/signal_path-9c02ae.o
Normal file
Binary file not shown.
617
simulation/Release/chesswork/signal_path-9c02ae.sfg
Normal file
617
simulation/Release/chesswork/signal_path-9c02ae.sfg
Normal file
@@ -0,0 +1,617 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
|
||||
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
|
||||
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( b=8 );
|
||||
}
|
||||
****
|
||||
!! void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
|
||||
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
|
||||
fnm : "sig_init_preemph_coef" 'void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int sig_init_delay(SingleSignalPath *, int)
|
||||
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! void sig_init_weight(SingleSignalPath *, double, int)
|
||||
F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
|
||||
fnm : "sig_init_weight" 'void sig_init_weight(SingleSignalPath *, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
|
||||
F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii : user_defined, called {
|
||||
fnm : "sig_init_buffer_DMB" 'int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[4] A[5] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int sig_init_buffer(BufferPtr *, int *, int, int)
|
||||
F_Z15sig_init_bufferP9BufferPtrPiii : user_defined, called {
|
||||
fnm : "sig_init_buffer" 'int sig_init_buffer(BufferPtr *, int *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_mul(float64, float64)
|
||||
F_Z11float64_mulyy : user_defined, called {
|
||||
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! int float64_to_int32_round_to_zero(float64)
|
||||
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
|
||||
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z4initP16SingleSignalPathS0_PdS1_iidddi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___PSingleSignalPath___P__fdouble___P__fdouble___sint___sint___fdouble___fdouble___fdouble___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
|
||||
14 : __M_LDMA typ=int64_ bnd=d stl=LDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : _ZL2mu typ=int8_ bnd=i sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
37 : ptr_fir_lms_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
|
||||
38 : __extDM_BufferPtrDMB typ=int8_ bnd=b stl=DM
|
||||
39 : fir_lms_delay_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
|
||||
40 : ptr_fir_lms_coeffs typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
|
||||
41 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
|
||||
42 : fir_lms_coeffs typ=int8_ bnd=e sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
|
||||
43 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
|
||||
44 : __extDM_int64_ typ=int8_ bnd=b stl=DM
|
||||
45 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
46 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
47 : ptr_fir_lms_delay_line_ptr_start typ=int8_ bnd=b stl=DM
|
||||
48 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
|
||||
49 : ptr_fir_lms_coeffs_ptr_start typ=int8_ bnd=b stl=DM
|
||||
50 : __rd___sp typ=dmaddr_ bnd=m
|
||||
52 : __ptr_mu typ=dmaddr_ val=0a bnd=m adro=35
|
||||
53 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ bnd=m
|
||||
54 : __ptr_ptr_fir_lms_delay_line typ=dmaddr_ val=0a bnd=m adro=37
|
||||
55 : __ptr_fir_lms_delay_line typ=dmaddr_ bnd=m
|
||||
56 : __ptr_fir_lms_delay_line typ=dmaddr_ val=0a bnd=m adro=39
|
||||
57 : __ptr_ptr_fir_lms_coeffs typ=dmaddr_ bnd=m
|
||||
58 : __ptr_ptr_fir_lms_coeffs typ=dmaddr_ val=0a bnd=m adro=40
|
||||
59 : __ptr_fir_lms_coeffs typ=dmaddr_ bnd=m
|
||||
60 : __ptr_fir_lms_coeffs typ=dmaddr_ val=0a bnd=m adro=42
|
||||
61 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
62 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
63 : cSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
64 : accSensorSignal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
65 : b_c typ=dmaddr_ bnd=p tref=__P__fdouble__
|
||||
66 : b_acc typ=dmaddr_ bnd=p tref=__P__fdouble__
|
||||
67 : delay_c typ=int32_ bnd=p tref=__sint__
|
||||
68 : delay_acc typ=int32_ bnd=p tref=__sint__
|
||||
69 : weight_c typ=int64_ bnd=p tref=__fdouble__
|
||||
70 : weight_acc typ=int64_ bnd=p tref=__fdouble__
|
||||
71 : lms_mu typ=int64_ bnd=p tref=__fdouble__
|
||||
72 : lms_fir_num_coeffs typ=int32_ bnd=p tref=__sint__
|
||||
78 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
81 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
85 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
89 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
93 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
97 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
98 : __ct_31 typ=int32_ val=31f bnd=m
|
||||
99 : __ct typ=int32_ bnd=m
|
||||
100 : _Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=dmaddr_ val=0r bnd=m
|
||||
102 : __link typ=dmaddr_ bnd=m
|
||||
103 : _Z14sig_init_delayP16SingleSignalPathi typ=dmaddr_ val=0r bnd=m
|
||||
105 : __link typ=dmaddr_ bnd=m
|
||||
106 : __tmp typ=int32_ bnd=m
|
||||
108 : __ct typ=int32_ bnd=m
|
||||
109 : _Z15sig_init_weightP16SingleSignalPathdi typ=dmaddr_ val=0r bnd=m
|
||||
111 : __link typ=dmaddr_ bnd=m
|
||||
115 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
119 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
123 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
127 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
131 : __fch___extDM_int64_ typ=int64_ bnd=m
|
||||
133 : __ct typ=int32_ bnd=m
|
||||
136 : __link typ=dmaddr_ bnd=m
|
||||
139 : __link typ=dmaddr_ bnd=m
|
||||
140 : __tmp typ=int32_ bnd=m
|
||||
142 : __ct typ=int32_ bnd=m
|
||||
145 : __link typ=dmaddr_ bnd=m
|
||||
146 : __ct_4746794007244308480 typ=int64_ val=4746794007244308480f bnd=m
|
||||
148 : __tmp typ=int64_ bnd=m
|
||||
149 : __tmp typ=int32_ bnd=m
|
||||
150 : __ct_64 typ=int32_ val=64f bnd=m
|
||||
151 : __ct typ=int32_ bnd=m
|
||||
152 : _Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii typ=dmaddr_ val=0r bnd=m
|
||||
154 : __link typ=dmaddr_ bnd=m
|
||||
155 : __tmp typ=int32_ bnd=m
|
||||
157 : __ct typ=int32_ bnd=m
|
||||
158 : _Z15sig_init_bufferP9BufferPtrPiii typ=dmaddr_ val=0r bnd=m
|
||||
160 : __link typ=dmaddr_ bnd=m
|
||||
161 : __tmp typ=int32_ bnd=m
|
||||
164 : __tmp typ=bool bnd=m
|
||||
170 : __fch_ptr_fir_lms_delay_line_ptr_start typ=dmaddr_ bnd=m
|
||||
180 : __fch_ptr_fir_lms_coeffs_ptr_start typ=dmaddr_ bnd=m
|
||||
201 : __iv1_i typ=dmaddr_ bnd=m
|
||||
202 : __iv2_i typ=dmaddr_ bnd=m
|
||||
205 : __cv typ=uint16_ bnd=m
|
||||
213 : __ptr_ptr_fir_lms_delay_line__a4 typ=dmaddr_ val=4a bnd=m adro=37
|
||||
214 : __ptr_ptr_fir_lms_coeffs__a4 typ=dmaddr_ val=4a bnd=m adro=40
|
||||
217 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
248 : __ct_0S0 typ=int18_ val=-8S0 bnd=m
|
||||
249 : __ct_0s0 typ=int18_ val=8s0 bnd=m
|
||||
250 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
251 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
262 : __tmp typ=uint3_ bnd=m
|
||||
267 : __a1 typ=int64_ bnd=m tref=__atp1___10
|
||||
268 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
|
||||
269 : __link typ=dmaddr_ bnd=m
|
||||
271 : __tmp typ=int64_ bnd=m
|
||||
273 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
|
||||
274 : __link typ=dmaddr_ bnd=m
|
||||
285 : __either typ=bool bnd=m
|
||||
286 : __trgt typ=int10_ val=0j bnd=m
|
||||
287 : __trgt typ=int10_ val=0j bnd=m
|
||||
288 : __trgt typ=uint16_ val=0j bnd=m
|
||||
289 : __vcnt typ=uint16_ bnd=m
|
||||
]
|
||||
F_Z4initP16SingleSignalPathS0_PdS1_iidddi {
|
||||
#276 off=0
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__M_WDMB.10 var=12) st_def () <20>;
|
||||
(__M_LDMA.12 var=14) st_def () <24>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(_ZL2mu.33 var=35) source () <57>;
|
||||
(__extDM_int32_.34 var=36) source () <58>;
|
||||
(ptr_fir_lms_delay_line.35 var=37) source () <59>;
|
||||
(__extDM_BufferPtrDMB.36 var=38) source () <60>;
|
||||
(fir_lms_delay_line.37 var=39) source () <61>;
|
||||
(ptr_fir_lms_coeffs.38 var=40) source () <62>;
|
||||
(__extDM_BufferPtr.39 var=41) source () <63>;
|
||||
(fir_lms_coeffs.40 var=42) source () <64>;
|
||||
(__extDM_SingleSignalPath.41 var=43) source () <65>;
|
||||
(__extDM_int64_.42 var=44) source () <66>;
|
||||
(__extDM_void.43 var=45) source () <67>;
|
||||
(__extPM_void.44 var=46) source () <68>;
|
||||
(ptr_fir_lms_delay_line_ptr_start.45 var=47) source () <69>;
|
||||
(__extDM___PDMint32_.46 var=48) source () <70>;
|
||||
(ptr_fir_lms_coeffs_ptr_start.47 var=49) source () <71>;
|
||||
(__ct_0.59 var=61) const () <83>;
|
||||
(__la.61 var=62 stl=LR off=0) inp () <85>;
|
||||
(__la.62 var=62) deassign (__la.61) <86>;
|
||||
(cSensorSignal.64 var=63 stl=A off=0) inp () <88>;
|
||||
(cSensorSignal.65 var=63) deassign (cSensorSignal.64) <89>;
|
||||
(accSensorSignal.67 var=64 stl=A off=1) inp () <91>;
|
||||
(accSensorSignal.68 var=64) deassign (accSensorSignal.67) <92>;
|
||||
(b_c.70 var=65 stl=A off=2) inp () <94>;
|
||||
(b_c.71 var=65) deassign (b_c.70) <95>;
|
||||
(b_acc.73 var=66 stl=A off=3) inp () <97>;
|
||||
(b_acc.74 var=66) deassign (b_acc.73) <98>;
|
||||
(delay_c.76 var=67 stl=RA off=0) inp () <100>;
|
||||
(delay_c.77 var=67) deassign (delay_c.76) <101>;
|
||||
(delay_acc.79 var=68 stl=RA off=1) inp () <103>;
|
||||
(delay_acc.80 var=68) deassign (delay_acc.79) <104>;
|
||||
(weight_c.82 var=69 stl=AX off=0) inp () <106>;
|
||||
(weight_c.83 var=69) deassign (weight_c.82) <107>;
|
||||
(weight_acc.85 var=70 stl=AX off=1) inp () <109>;
|
||||
(weight_acc.86 var=70) deassign (weight_acc.85) <110>;
|
||||
(lms_mu.88 var=71 stl=BX off=0) inp () <112>;
|
||||
(lms_mu.89 var=71) deassign (lms_mu.88) <113>;
|
||||
(lms_fir_num_coeffs.91 var=72 stl=RB off=0) inp () <115>;
|
||||
(lms_fir_num_coeffs.92 var=72) deassign (lms_fir_num_coeffs.91) <116>;
|
||||
(__rd___sp.94 var=50) rd_res_reg (__R_SP.24 __sp.32) <118>;
|
||||
(__R_SP.98 var=26 __sp.99 var=34) wr_res_reg (__rt.679 __sp.32) <122>;
|
||||
(__fch___extDM_int64_.106 var=81) load (__M_LDMA.12 b_c.71 __extDM_int64_.42) <130>;
|
||||
(__fch___extDM_int64_.111 var=85) load (__M_LDMA.12 __rt.767 __extDM_int64_.42) <135>;
|
||||
(__fch___extDM_int64_.116 var=89) load (__M_LDMA.12 __rt.789 __extDM_int64_.42) <140>;
|
||||
(__fch___extDM_int64_.121 var=93) load (__M_LDMA.12 __rt.811 __extDM_int64_.42) <145>;
|
||||
(__fch___extDM_int64_.126 var=97) load (__M_LDMA.12 __rt.833 __extDM_int64_.42) <150>;
|
||||
(__ct_31.128 var=98) const () <152>;
|
||||
(_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131 var=100) const () <155>;
|
||||
(__link.133 var=102) dmaddr__call_dmaddr_ (_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131) <157>;
|
||||
(__rt.679 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.94 __ct_0S0.934) <617>;
|
||||
(__rt.767 var=217) __Pvoid__pl___Pvoid_int18_ (b_c.71 __ct_8.937) <729>;
|
||||
(__rt.789 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.767 __ct_8.937) <757>;
|
||||
(__rt.811 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.789 __ct_8.937) <785>;
|
||||
(__rt.833 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.811 __ct_8.937) <813>;
|
||||
(__ct_0S0.934 var=248) const () <965>;
|
||||
(__ct_8.937 var=251) const () <971>;
|
||||
call {
|
||||
(cSensorSignal.102 var=63 stl=A off=0) assign (cSensorSignal.65) <126>;
|
||||
(__fch___extDM_int64_.107 var=81 stl=AX off=0) assign (__fch___extDM_int64_.106) <131>;
|
||||
(__fch___extDM_int64_.112 var=85 stl=AX off=1) assign (__fch___extDM_int64_.111) <136>;
|
||||
(__fch___extDM_int64_.117 var=89 stl=BX off=0) assign (__fch___extDM_int64_.116) <141>;
|
||||
(__fch___extDM_int64_.122 var=93 stl=BX off=1) assign (__fch___extDM_int64_.121) <146>;
|
||||
(__fch___extDM_int64_.127 var=97 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.126) <151>;
|
||||
(__ct.130 var=99 stl=RA off=0) assign (__ct_31.128) <154>;
|
||||
(__link.134 var=102 stl=LR off=0) assign (__link.133) <158>;
|
||||
(_ZL2mu.135 var=35 __extDM.136 var=32 __extDM_BufferPtr.137 var=41 __extDM_BufferPtrDMB.138 var=38 __extDM_SingleSignalPath.139 var=43 __extDM___PDMint32_.140 var=48 __extDM_int32_.141 var=36 __extDM_int64_.142 var=44 __extDM_void.143 var=45 __extPM.144 var=33 __extPM_void.145 var=46 fir_lms_coeffs.146 var=42 fir_lms_delay_line.147 var=39 ptr_fir_lms_coeffs.148 var=40 ptr_fir_lms_coeffs_ptr_start.149 var=49 ptr_fir_lms_delay_line.150 var=37 ptr_fir_lms_delay_line_ptr_start.151 var=47 __vola.152 var=29) F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi (__link.134 cSensorSignal.102 __fch___extDM_int64_.107 __fch___extDM_int64_.112 __fch___extDM_int64_.117 __fch___extDM_int64_.122 __fch___extDM_int64_.127 __ct.130 _ZL2mu.33 __extDM.30 __extDM_BufferPtr.39 __extDM_BufferPtrDMB.36 __extDM_SingleSignalPath.41 __extDM___PDMint32_.46 __extDM_int32_.34 __extDM_int64_.42 __extDM_void.43 __extPM.31 __extPM_void.44 fir_lms_coeffs.40 fir_lms_delay_line.37 ptr_fir_lms_coeffs.38 ptr_fir_lms_coeffs_ptr_start.47 ptr_fir_lms_delay_line.35 ptr_fir_lms_delay_line_ptr_start.45 __vola.27) <159>;
|
||||
} #4 off=1
|
||||
#5 off=2
|
||||
(_Z14sig_init_delayP16SingleSignalPathi.155 var=103) const () <162>;
|
||||
(__link.157 var=105) dmaddr__call_dmaddr_ (_Z14sig_init_delayP16SingleSignalPathi.155) <164>;
|
||||
call {
|
||||
(cSensorSignal.153 var=63 stl=A off=0) assign (cSensorSignal.65) <160>;
|
||||
(delay_c.154 var=67 stl=RA off=1) assign (delay_c.77) <161>;
|
||||
(__link.158 var=105 stl=LR off=0) assign (__link.157) <165>;
|
||||
(__tmp.159 var=106 stl=RA off=0 _ZL2mu.162 var=35 __extDM.163 var=32 __extDM_BufferPtr.164 var=41 __extDM_BufferPtrDMB.165 var=38 __extDM_SingleSignalPath.166 var=43 __extDM___PDMint32_.167 var=48 __extDM_int32_.168 var=36 __extDM_int64_.169 var=44 __extDM_void.170 var=45 __extPM.171 var=33 __extPM_void.172 var=46 fir_lms_coeffs.173 var=42 fir_lms_delay_line.174 var=39 ptr_fir_lms_coeffs.175 var=40 ptr_fir_lms_coeffs_ptr_start.176 var=49 ptr_fir_lms_delay_line.177 var=37 ptr_fir_lms_delay_line_ptr_start.178 var=47 __vola.179 var=29) F_Z14sig_init_delayP16SingleSignalPathi (__link.158 cSensorSignal.153 delay_c.154 _ZL2mu.135 __extDM.136 __extDM_BufferPtr.137 __extDM_BufferPtrDMB.138 __extDM_SingleSignalPath.139 __extDM___PDMint32_.140 __extDM_int32_.141 __extDM_int64_.142 __extDM_void.143 __extPM.144 __extPM_void.145 fir_lms_coeffs.146 fir_lms_delay_line.147 ptr_fir_lms_coeffs.148 ptr_fir_lms_coeffs_ptr_start.149 ptr_fir_lms_delay_line.150 ptr_fir_lms_delay_line_ptr_start.151 __vola.152) <166>;
|
||||
} #6 off=3
|
||||
#7 off=4
|
||||
(_Z15sig_init_weightP16SingleSignalPathdi.185 var=109) const () <174>;
|
||||
(__link.187 var=111) dmaddr__call_dmaddr_ (_Z15sig_init_weightP16SingleSignalPathdi.185) <176>;
|
||||
call {
|
||||
(cSensorSignal.180 var=63 stl=A off=0) assign (cSensorSignal.65) <169>;
|
||||
(weight_c.181 var=69 stl=AX off=0) assign (weight_c.83) <170>;
|
||||
(__ct.184 var=108 stl=RA off=0) assign (__ct_31.128) <173>;
|
||||
(__link.188 var=111 stl=LR off=0) assign (__link.187) <177>;
|
||||
(_ZL2mu.189 var=35 __extDM.190 var=32 __extDM_BufferPtr.191 var=41 __extDM_BufferPtrDMB.192 var=38 __extDM_SingleSignalPath.193 var=43 __extDM___PDMint32_.194 var=48 __extDM_int32_.195 var=36 __extDM_int64_.196 var=44 __extDM_void.197 var=45 __extPM.198 var=33 __extPM_void.199 var=46 fir_lms_coeffs.200 var=42 fir_lms_delay_line.201 var=39 ptr_fir_lms_coeffs.202 var=40 ptr_fir_lms_coeffs_ptr_start.203 var=49 ptr_fir_lms_delay_line.204 var=37 ptr_fir_lms_delay_line_ptr_start.205 var=47 __vola.206 var=29) F_Z15sig_init_weightP16SingleSignalPathdi (__link.188 cSensorSignal.180 weight_c.181 __ct.184 _ZL2mu.162 __extDM.163 __extDM_BufferPtr.164 __extDM_BufferPtrDMB.165 __extDM_SingleSignalPath.166 __extDM___PDMint32_.167 __extDM_int32_.168 __extDM_int64_.169 __extDM_void.170 __extPM.171 __extPM_void.172 fir_lms_coeffs.173 fir_lms_delay_line.174 ptr_fir_lms_coeffs.175 ptr_fir_lms_coeffs_ptr_start.176 ptr_fir_lms_delay_line.177 ptr_fir_lms_delay_line_ptr_start.178 __vola.179) <178>;
|
||||
} #8 off=5
|
||||
#370 off=6
|
||||
(__fch___extDM_int64_.211 var=115) load (__M_LDMA.12 b_acc.74 __extDM_int64_.196) <183>;
|
||||
(__fch___extDM_int64_.216 var=119) load (__M_LDMA.12 __rt.855 __extDM_int64_.196) <188>;
|
||||
(__fch___extDM_int64_.221 var=123) load (__M_LDMA.12 __rt.877 __extDM_int64_.196) <193>;
|
||||
(__fch___extDM_int64_.226 var=127) load (__M_LDMA.12 __rt.899 __extDM_int64_.196) <198>;
|
||||
(__fch___extDM_int64_.231 var=131) load (__M_LDMA.12 __rt.921 __extDM_int64_.196) <203>;
|
||||
(__link.238 var=136) dmaddr__call_dmaddr_ (_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.131) <210>;
|
||||
(__rt.855 var=217) __Pvoid__pl___Pvoid_int18_ (b_acc.74 __ct_8.937) <841>;
|
||||
(__rt.877 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.855 __ct_8.937) <869>;
|
||||
(__rt.899 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.877 __ct_8.937) <897>;
|
||||
(__rt.921 var=217) __Pvoid__pl___Pvoid_int18_ (__rt.899 __ct_8.937) <925>;
|
||||
call {
|
||||
(accSensorSignal.207 var=64 stl=A off=0) assign (accSensorSignal.68) <179>;
|
||||
(__fch___extDM_int64_.212 var=115 stl=AX off=0) assign (__fch___extDM_int64_.211) <184>;
|
||||
(__fch___extDM_int64_.217 var=119 stl=AX off=1) assign (__fch___extDM_int64_.216) <189>;
|
||||
(__fch___extDM_int64_.222 var=123 stl=BX off=0) assign (__fch___extDM_int64_.221) <194>;
|
||||
(__fch___extDM_int64_.227 var=127 stl=BX off=1) assign (__fch___extDM_int64_.226) <199>;
|
||||
(__fch___extDM_int64_.232 var=131 stl=__spill_LDMA off=0) assign (__fch___extDM_int64_.231) <204>;
|
||||
(__ct.235 var=133 stl=RA off=0) assign (__ct_31.128) <207>;
|
||||
(__link.239 var=136 stl=LR off=0) assign (__link.238) <211>;
|
||||
(_ZL2mu.240 var=35 __extDM.241 var=32 __extDM_BufferPtr.242 var=41 __extDM_BufferPtrDMB.243 var=38 __extDM_SingleSignalPath.244 var=43 __extDM___PDMint32_.245 var=48 __extDM_int32_.246 var=36 __extDM_int64_.247 var=44 __extDM_void.248 var=45 __extPM.249 var=33 __extPM_void.250 var=46 fir_lms_coeffs.251 var=42 fir_lms_delay_line.252 var=39 ptr_fir_lms_coeffs.253 var=40 ptr_fir_lms_coeffs_ptr_start.254 var=49 ptr_fir_lms_delay_line.255 var=37 ptr_fir_lms_delay_line_ptr_start.256 var=47 __vola.257 var=29) F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi (__link.239 accSensorSignal.207 __fch___extDM_int64_.212 __fch___extDM_int64_.217 __fch___extDM_int64_.222 __fch___extDM_int64_.227 __fch___extDM_int64_.232 __ct.235 _ZL2mu.189 __extDM.190 __extDM_BufferPtr.191 __extDM_BufferPtrDMB.192 __extDM_SingleSignalPath.193 __extDM___PDMint32_.194 __extDM_int32_.195 __extDM_int64_.196 __extDM_void.197 __extPM.198 __extPM_void.199 fir_lms_coeffs.200 fir_lms_delay_line.201 ptr_fir_lms_coeffs.202 ptr_fir_lms_coeffs_ptr_start.203 ptr_fir_lms_delay_line.204 ptr_fir_lms_delay_line_ptr_start.205 __vola.206) <212>;
|
||||
} #10 off=7
|
||||
#11 off=8
|
||||
(__link.262 var=139) dmaddr__call_dmaddr_ (_Z14sig_init_delayP16SingleSignalPathi.155) <217>;
|
||||
call {
|
||||
(accSensorSignal.258 var=64 stl=A off=0) assign (accSensorSignal.68) <213>;
|
||||
(delay_acc.259 var=68 stl=RA off=1) assign (delay_acc.80) <214>;
|
||||
(__link.263 var=139 stl=LR off=0) assign (__link.262) <218>;
|
||||
(__tmp.264 var=140 stl=RA off=0 _ZL2mu.267 var=35 __extDM.268 var=32 __extDM_BufferPtr.269 var=41 __extDM_BufferPtrDMB.270 var=38 __extDM_SingleSignalPath.271 var=43 __extDM___PDMint32_.272 var=48 __extDM_int32_.273 var=36 __extDM_int64_.274 var=44 __extDM_void.275 var=45 __extPM.276 var=33 __extPM_void.277 var=46 fir_lms_coeffs.278 var=42 fir_lms_delay_line.279 var=39 ptr_fir_lms_coeffs.280 var=40 ptr_fir_lms_coeffs_ptr_start.281 var=49 ptr_fir_lms_delay_line.282 var=37 ptr_fir_lms_delay_line_ptr_start.283 var=47 __vola.284 var=29) F_Z14sig_init_delayP16SingleSignalPathi (__link.263 accSensorSignal.258 delay_acc.259 _ZL2mu.240 __extDM.241 __extDM_BufferPtr.242 __extDM_BufferPtrDMB.243 __extDM_SingleSignalPath.244 __extDM___PDMint32_.245 __extDM_int32_.246 __extDM_int64_.247 __extDM_void.248 __extPM.249 __extPM_void.250 fir_lms_coeffs.251 fir_lms_delay_line.252 ptr_fir_lms_coeffs.253 ptr_fir_lms_coeffs_ptr_start.254 ptr_fir_lms_delay_line.255 ptr_fir_lms_delay_line_ptr_start.256 __vola.257) <219>;
|
||||
} #12 off=9
|
||||
#13 off=10
|
||||
(__link.292 var=145) dmaddr__call_dmaddr_ (_Z15sig_init_weightP16SingleSignalPathdi.185) <229>;
|
||||
call {
|
||||
(accSensorSignal.285 var=64 stl=A off=0) assign (accSensorSignal.68) <222>;
|
||||
(weight_acc.286 var=70 stl=AX off=0) assign (weight_acc.86) <223>;
|
||||
(__ct.289 var=142 stl=RA off=0) assign (__ct_31.128) <226>;
|
||||
(__link.293 var=145 stl=LR off=0) assign (__link.292) <230>;
|
||||
(_ZL2mu.294 var=35 __extDM.295 var=32 __extDM_BufferPtr.296 var=41 __extDM_BufferPtrDMB.297 var=38 __extDM_SingleSignalPath.298 var=43 __extDM___PDMint32_.299 var=48 __extDM_int32_.300 var=36 __extDM_int64_.301 var=44 __extDM_void.302 var=45 __extPM.303 var=33 __extPM_void.304 var=46 fir_lms_coeffs.305 var=42 fir_lms_delay_line.306 var=39 ptr_fir_lms_coeffs.307 var=40 ptr_fir_lms_coeffs_ptr_start.308 var=49 ptr_fir_lms_delay_line.309 var=37 ptr_fir_lms_delay_line_ptr_start.310 var=47 __vola.311 var=29) F_Z15sig_init_weightP16SingleSignalPathdi (__link.293 accSensorSignal.285 weight_acc.286 __ct.289 _ZL2mu.267 __extDM.268 __extDM_BufferPtr.269 __extDM_BufferPtrDMB.270 __extDM_SingleSignalPath.271 __extDM___PDMint32_.272 __extDM_int32_.273 __extDM_int64_.274 __extDM_void.275 __extPM.276 __extPM_void.277 fir_lms_coeffs.278 fir_lms_delay_line.279 ptr_fir_lms_coeffs.280 ptr_fir_lms_coeffs_ptr_start.281 ptr_fir_lms_delay_line.282 ptr_fir_lms_delay_line_ptr_start.283 __vola.284) <231>;
|
||||
} #14 off=11
|
||||
#474 off=12
|
||||
(__ct_4746794007244308480.312 var=146) const () <232>;
|
||||
(_Z11float64_mulyy.954 var=268) const () <1022>;
|
||||
(__link.955 var=269) dmaddr__call_dmaddr_ (_Z11float64_mulyy.954) <1023>;
|
||||
call {
|
||||
(lms_mu.956 var=71 stl=AX off=1) assign (lms_mu.89) <1024>;
|
||||
(__a1.957 var=267 stl=BX off=0) assign (__ct_4746794007244308480.312) <1025>;
|
||||
(__link.958 var=269 stl=LR off=0) assign (__link.955) <1026>;
|
||||
(__tmp.959 var=271 stl=AX off=0) F_Z11float64_mulyy (__link.958 lms_mu.956 __a1.957) <1027>;
|
||||
(__tmp.960 var=148) deassign (__tmp.959) <1028>;
|
||||
} #475 off=13
|
||||
#480 off=14
|
||||
(_Z30float64_to_int32_round_to_zeroy.963 var=273) const () <1034>;
|
||||
(__link.964 var=274) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.963) <1035>;
|
||||
call {
|
||||
(__tmp.965 var=148 stl=AX off=0) assign (__tmp.960) <1036>;
|
||||
(__link.966 var=274 stl=LR off=0) assign (__link.964) <1037>;
|
||||
(__tmp.967 var=149 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.966 __tmp.965) <1038>;
|
||||
(__tmp.968 var=149) deassign (__tmp.967) <1039>;
|
||||
} #481 off=15
|
||||
#471 off=16
|
||||
(__ptr_mu.49 var=52) const () <73>;
|
||||
(__ptr_ptr_fir_lms_delay_line.51 var=54) const () <75>;
|
||||
(__ptr_fir_lms_delay_line.53 var=56) const () <77>;
|
||||
(__M_WDMA.316 var=11 _ZL2mu.317 var=35) store (__tmp.968 __ptr_mu.49 _ZL2mu.294) <236>;
|
||||
(__ct_64.321 var=150) const () <240>;
|
||||
(_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324 var=152) const () <243>;
|
||||
(__link.326 var=154) dmaddr__call_dmaddr_ (_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii.324) <245>;
|
||||
call {
|
||||
(__ptr_ptr_fir_lms_delay_line.318 var=53 stl=A off=4) assign (__ptr_ptr_fir_lms_delay_line.51) <237>;
|
||||
(__ptr_fir_lms_delay_line.319 var=55 stl=A off=5) assign (__ptr_fir_lms_delay_line.53) <238>;
|
||||
(lms_fir_num_coeffs.320 var=72 stl=RA off=1) assign (lms_fir_num_coeffs.92) <239>;
|
||||
(__ct.323 var=151 stl=RB off=0) assign (__ct_64.321) <242>;
|
||||
(__link.327 var=154 stl=LR off=0) assign (__link.326) <246>;
|
||||
(__tmp.328 var=155 stl=RA off=0 _ZL2mu.331 var=35 __extDM.332 var=32 __extDM_BufferPtr.333 var=41 __extDM_BufferPtrDMB.334 var=38 __extDM_SingleSignalPath.335 var=43 __extDM___PDMint32_.336 var=48 __extDM_int32_.337 var=36 __extDM_int64_.338 var=44 __extDM_void.339 var=45 __extPM.340 var=33 __extPM_void.341 var=46 fir_lms_coeffs.342 var=42 fir_lms_delay_line.343 var=39 ptr_fir_lms_coeffs.344 var=40 ptr_fir_lms_coeffs_ptr_start.345 var=49 ptr_fir_lms_delay_line.346 var=37 ptr_fir_lms_delay_line_ptr_start.347 var=47 __vola.348 var=29) F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii (__link.327 __ptr_ptr_fir_lms_delay_line.318 __ptr_fir_lms_delay_line.319 lms_fir_num_coeffs.320 __ct.323 _ZL2mu.317 __extDM.295 __extDM_BufferPtr.296 __extDM_BufferPtrDMB.297 __extDM_SingleSignalPath.298 __extDM___PDMint32_.299 __extDM_int32_.300 __extDM_int64_.301 __extDM_void.302 __extPM.303 __extPM_void.304 fir_lms_coeffs.305 fir_lms_delay_line.306 ptr_fir_lms_coeffs.307 ptr_fir_lms_coeffs_ptr_start.308 ptr_fir_lms_delay_line.309 ptr_fir_lms_delay_line_ptr_start.310 __vola.311) <247>;
|
||||
} #16 off=17
|
||||
#17 off=18
|
||||
(__ptr_ptr_fir_lms_coeffs.55 var=58) const () <79>;
|
||||
(__ptr_fir_lms_coeffs.57 var=60) const () <81>;
|
||||
(_Z15sig_init_bufferP9BufferPtrPiii.355 var=158) const () <256>;
|
||||
(__link.357 var=160) dmaddr__call_dmaddr_ (_Z15sig_init_bufferP9BufferPtrPiii.355) <258>;
|
||||
call {
|
||||
(__ptr_ptr_fir_lms_coeffs.349 var=57 stl=A off=0) assign (__ptr_ptr_fir_lms_coeffs.55) <250>;
|
||||
(__ptr_fir_lms_coeffs.350 var=59 stl=A off=1) assign (__ptr_fir_lms_coeffs.57) <251>;
|
||||
(lms_fir_num_coeffs.351 var=72 stl=RA off=1) assign (lms_fir_num_coeffs.92) <252>;
|
||||
(__ct.354 var=157 stl=RB off=0) assign (__ct_64.321) <255>;
|
||||
(__link.358 var=160 stl=LR off=0) assign (__link.357) <259>;
|
||||
(__tmp.359 var=161 stl=RA off=0 _ZL2mu.362 var=35 __extDM.363 var=32 __extDM_BufferPtr.364 var=41 __extDM_BufferPtrDMB.365 var=38 __extDM_SingleSignalPath.366 var=43 __extDM___PDMint32_.367 var=48 __extDM_int32_.368 var=36 __extDM_int64_.369 var=44 __extDM_void.370 var=45 __extPM.371 var=33 __extPM_void.372 var=46 fir_lms_coeffs.373 var=42 fir_lms_delay_line.374 var=39 ptr_fir_lms_coeffs.375 var=40 ptr_fir_lms_coeffs_ptr_start.376 var=49 ptr_fir_lms_delay_line.377 var=37 ptr_fir_lms_delay_line_ptr_start.378 var=47 __vola.379 var=29) F_Z15sig_init_bufferP9BufferPtrPiii (__link.358 __ptr_ptr_fir_lms_coeffs.349 __ptr_fir_lms_coeffs.350 lms_fir_num_coeffs.351 __ct.354 _ZL2mu.331 __extDM.332 __extDM_BufferPtr.333 __extDM_BufferPtrDMB.334 __extDM_SingleSignalPath.335 __extDM___PDMint32_.336 __extDM_int32_.337 __extDM_int64_.338 __extDM_void.339 __extPM.340 __extPM_void.341 fir_lms_coeffs.342 fir_lms_delay_line.343 ptr_fir_lms_coeffs.344 ptr_fir_lms_coeffs_ptr_start.345 ptr_fir_lms_delay_line.346 ptr_fir_lms_delay_line_ptr_start.347 __vola.348) <260>;
|
||||
} #18 off=19
|
||||
#466 off=20
|
||||
(__ct_0.103 var=78) const () <127>;
|
||||
(__tmp.947 var=262) uint3__cmp_int72__int72_ (lms_fir_num_coeffs.92 __ct_0.103) <989>;
|
||||
(__tmp.975 var=164) bool_nplus_uint3_ (__tmp.947) <1098>;
|
||||
(__trgt.978 var=286) const () <1126>;
|
||||
() void_jump_bool_int10_ (__tmp.975 __trgt.978) <1127>;
|
||||
(__either.979 var=285) undefined () <1128>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.979) <306>;
|
||||
() chess_frequent_else () <307>;
|
||||
() chess_rear_then () <1129>;
|
||||
} #21
|
||||
{
|
||||
(__trgt.980 var=287) const () <1130>;
|
||||
() void_jump_int10_ (__trgt.980) <1131>;
|
||||
} #27 off=24
|
||||
{
|
||||
#34 off=21
|
||||
(__fch_ptr_fir_lms_delay_line_ptr_start.467 var=170) load (__M_WDMB.10 __ptr_ptr_fir_lms_delay_line__a4.664 ptr_fir_lms_delay_line_ptr_start.378) <352>;
|
||||
(__fch_ptr_fir_lms_coeffs_ptr_start.482 var=180) load (__M_WDMA.9 __ptr_ptr_fir_lms_coeffs__a4.665 ptr_fir_lms_coeffs_ptr_start.376) <363>;
|
||||
(__cv.649 var=205) uint16__uint16____sint (lms_fir_num_coeffs.92) <558>;
|
||||
(__ptr_ptr_fir_lms_delay_line__a4.664 var=213) const () <574>;
|
||||
(__ptr_ptr_fir_lms_coeffs__a4.665 var=214) const () <576>;
|
||||
(__ct_4.936 var=250) const () <969>;
|
||||
(__trgt.981 var=288) const () <1132>;
|
||||
() void_doloop_uint16__uint16_ (__cv.649 __trgt.981) <1133>;
|
||||
(__vcnt.982 var=289) undefined () <1134>;
|
||||
for {
|
||||
{
|
||||
(_ZL2mu.429 var=35) entry (_ZL2mu.508 _ZL2mu.362) <314>;
|
||||
(__extDM_int32_.430 var=36) entry (__extDM_int32_.510 __extDM_int32_.368) <315>;
|
||||
(fir_lms_delay_line.433 var=39) entry (fir_lms_delay_line.516 fir_lms_delay_line.374) <318>;
|
||||
(fir_lms_coeffs.436 var=42) entry (fir_lms_coeffs.522 fir_lms_coeffs.373) <321>;
|
||||
(__iv1_i.635 var=201) entry (__iv1_i.636 __fch_ptr_fir_lms_delay_line_ptr_start.467) <545>;
|
||||
(__iv2_i.640 var=202) entry (__iv2_i.641 __fch_ptr_fir_lms_coeffs_ptr_start.482) <549>;
|
||||
} #24
|
||||
{
|
||||
(__M_WDMB.472 var=12 _ZL2mu.473 var=35 __extDM_int32_.474 var=36 fir_lms_coeffs.475 var=42 fir_lms_delay_line.476 var=39) store (__ct_0.103 __iv1_i.635 _ZL2mu.429 __extDM_int32_.430 fir_lms_coeffs.436 fir_lms_delay_line.433) <357>;
|
||||
(__M_WDMA.487 var=11 _ZL2mu.488 var=35 __extDM_int32_.489 var=36 fir_lms_coeffs.490 var=42 fir_lms_delay_line.491 var=39) store (__ct_0.103 __iv2_i.640 _ZL2mu.473 __extDM_int32_.474 fir_lms_coeffs.475 fir_lms_delay_line.476) <368>;
|
||||
(__rt.723 var=217) __Pvoid__pl___Pvoid_int18_ (__iv1_i.635 __ct_4.936) <673>;
|
||||
(__rt.745 var=217) __Pvoid__pl___Pvoid_int18_ (__iv2_i.640 __ct_4.936) <701>;
|
||||
} #256 off=22
|
||||
{
|
||||
() for_count (__vcnt.982) <373>;
|
||||
(_ZL2mu.508 var=35 _ZL2mu.509 var=35) exit (_ZL2mu.488) <380>;
|
||||
(__extDM_int32_.510 var=36 __extDM_int32_.511 var=36) exit (__extDM_int32_.489) <381>;
|
||||
(fir_lms_delay_line.516 var=39 fir_lms_delay_line.517 var=39) exit (fir_lms_delay_line.491) <384>;
|
||||
(fir_lms_coeffs.522 var=42 fir_lms_coeffs.523 var=42) exit (fir_lms_coeffs.490) <387>;
|
||||
(__iv1_i.636 var=201 __iv1_i.637 var=201) exit (__rt.723) <546>;
|
||||
(__iv2_i.641 var=202 __iv2_i.642 var=202) exit (__rt.745) <550>;
|
||||
} #26
|
||||
} #23 rng=[1,65535]
|
||||
} #22
|
||||
{
|
||||
(_ZL2mu.574 var=35) merge (_ZL2mu.362 _ZL2mu.509) <413>;
|
||||
(__extDM_int32_.575 var=36) merge (__extDM_int32_.368 __extDM_int32_.511) <414>;
|
||||
(fir_lms_delay_line.576 var=39) merge (fir_lms_delay_line.374 fir_lms_delay_line.517) <415>;
|
||||
(fir_lms_coeffs.577 var=42) merge (fir_lms_coeffs.373 fir_lms_coeffs.523) <416>;
|
||||
} #28
|
||||
} #20
|
||||
#30 off=25 nxt=-2
|
||||
(__rd___sp.580 var=50) rd_res_reg (__R_SP.24 __sp.99) <419>;
|
||||
(__R_SP.584 var=26 __sp.585 var=34) wr_res_reg (__rt.701 __sp.99) <423>;
|
||||
() void_ret_dmaddr_ (__la.62) <424>;
|
||||
() sink (__vola.379) <425>;
|
||||
() sink (__extDM.363) <428>;
|
||||
() sink (__extPM.371) <429>;
|
||||
() sink (__sp.585) <430>;
|
||||
() sink (_ZL2mu.574) <431>;
|
||||
() sink (__extDM_int32_.575) <432>;
|
||||
() sink (ptr_fir_lms_delay_line.377) <433>;
|
||||
() sink (__extDM_BufferPtrDMB.365) <434>;
|
||||
() sink (fir_lms_delay_line.576) <435>;
|
||||
() sink (ptr_fir_lms_coeffs.375) <436>;
|
||||
() sink (__extDM_BufferPtr.364) <437>;
|
||||
() sink (fir_lms_coeffs.577) <438>;
|
||||
() sink (__extDM_SingleSignalPath.366) <439>;
|
||||
() sink (__extDM_int64_.369) <440>;
|
||||
() sink (__extDM_void.370) <441>;
|
||||
() sink (__extPM_void.372) <442>;
|
||||
() sink (ptr_fir_lms_delay_line_ptr_start.378) <443>;
|
||||
() sink (__extDM___PDMint32_.367) <444>;
|
||||
() sink (ptr_fir_lms_coeffs_ptr_start.376) <445>;
|
||||
() sink (__ct_0.59) <446>;
|
||||
(__rt.701 var=217) __Pvoid__pl___Pvoid_int18_ (__rd___sp.580 __ct_0s0.935) <645>;
|
||||
(__ct_0s0.935 var=249) const () <967>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,309:0,0);
|
||||
4 : (0,324:4,2);
|
||||
5 : (0,325:34,3);
|
||||
6 : (0,325:4,3);
|
||||
7 : (0,326:45,4);
|
||||
8 : (0,326:4,4);
|
||||
10 : (0,329:4,5);
|
||||
11 : (0,330:36,6);
|
||||
12 : (0,330:4,6);
|
||||
13 : (0,331:49,7);
|
||||
14 : (0,331:4,7);
|
||||
16 : (0,337:4,10);
|
||||
17 : (0,338:77,11);
|
||||
18 : (0,338:4,11);
|
||||
20 : (0,340:4,13);
|
||||
22 : (0,340:4,14);
|
||||
23 : (0,340:4,14);
|
||||
27 : (0,340:4,22);
|
||||
30 : (0,344:0,25);
|
||||
256 : (0,340:49,14);
|
||||
276 : (0,324:4,2);
|
||||
370 : (0,329:4,5);
|
||||
466 : (0,340:4,13);
|
||||
471 : (0,337:4,10);
|
||||
474 : (0,335:16,9);
|
||||
475 : (0,335:16,9);
|
||||
480 : (0,335:7,9);
|
||||
481 : (0,335:7,9);
|
||||
----------
|
||||
77 : (0,337:49,0);
|
||||
81 : (0,338:41,0);
|
||||
118 : (0,309:5,0);
|
||||
122 : (0,309:5,0);
|
||||
126 : (0,324:26,0);
|
||||
127 : (0,324:45,0);
|
||||
130 : (0,324:44,2);
|
||||
131 : (0,324:44,0);
|
||||
135 : (0,324:52,2);
|
||||
136 : (0,324:52,0);
|
||||
140 : (0,324:60,2);
|
||||
141 : (0,324:60,0);
|
||||
145 : (0,324:68,2);
|
||||
146 : (0,324:68,0);
|
||||
150 : (0,324:76,2);
|
||||
151 : (0,324:76,0);
|
||||
152 : (0,324:81,0);
|
||||
154 : (0,324:81,0);
|
||||
157 : (0,324:4,2);
|
||||
158 : (0,324:4,0);
|
||||
159 : (0,324:4,2);
|
||||
160 : (0,325:19,0);
|
||||
161 : (0,325:34,0);
|
||||
164 : (0,325:4,3);
|
||||
165 : (0,325:4,0);
|
||||
166 : (0,325:4,3);
|
||||
169 : (0,326:20,0);
|
||||
170 : (0,326:35,0);
|
||||
173 : (0,326:45,0);
|
||||
176 : (0,326:4,4);
|
||||
177 : (0,326:4,0);
|
||||
178 : (0,326:4,4);
|
||||
179 : (0,329:26,0);
|
||||
183 : (0,329:48,5);
|
||||
184 : (0,329:48,0);
|
||||
188 : (0,329:58,5);
|
||||
189 : (0,329:58,0);
|
||||
193 : (0,329:68,5);
|
||||
194 : (0,329:68,0);
|
||||
198 : (0,329:78,5);
|
||||
199 : (0,329:78,0);
|
||||
203 : (0,329:88,5);
|
||||
204 : (0,329:88,0);
|
||||
207 : (0,329:93,0);
|
||||
210 : (0,329:4,5);
|
||||
211 : (0,329:4,0);
|
||||
212 : (0,329:4,5);
|
||||
213 : (0,330:19,0);
|
||||
214 : (0,330:36,0);
|
||||
217 : (0,330:4,6);
|
||||
218 : (0,330:4,0);
|
||||
219 : (0,330:4,6);
|
||||
222 : (0,331:20,0);
|
||||
223 : (0,331:37,0);
|
||||
226 : (0,331:49,0);
|
||||
229 : (0,331:4,7);
|
||||
230 : (0,331:4,0);
|
||||
231 : (0,331:4,7);
|
||||
232 : (0,335:16,0);
|
||||
236 : (0,335:4,9);
|
||||
237 : (0,337:24,0);
|
||||
238 : (0,337:49,0);
|
||||
239 : (0,337:69,0);
|
||||
240 : (0,337:89,0);
|
||||
242 : (0,337:89,0);
|
||||
245 : (0,337:4,10);
|
||||
246 : (0,337:4,0);
|
||||
247 : (0,337:4,10);
|
||||
250 : (0,338:20,0);
|
||||
251 : (0,338:41,0);
|
||||
252 : (0,338:57,0);
|
||||
255 : (0,338:77,0);
|
||||
258 : (0,338:4,11);
|
||||
259 : (0,338:4,0);
|
||||
260 : (0,338:4,11);
|
||||
306 : (0,340:4,13);
|
||||
314 : (0,340:4,14);
|
||||
315 : (0,340:4,14);
|
||||
318 : (0,340:4,14);
|
||||
321 : (0,340:4,14);
|
||||
352 : (0,341:30,14);
|
||||
357 : (0,341:40,14);
|
||||
363 : (0,342:26,15);
|
||||
368 : (0,342:36,15);
|
||||
373 : (0,340:4,20);
|
||||
380 : (0,340:4,20);
|
||||
381 : (0,340:4,20);
|
||||
384 : (0,340:4,20);
|
||||
387 : (0,340:4,20);
|
||||
413 : (0,340:4,24);
|
||||
414 : (0,340:4,24);
|
||||
415 : (0,340:4,24);
|
||||
416 : (0,340:4,24);
|
||||
419 : (0,344:0,0);
|
||||
423 : (0,344:0,25);
|
||||
424 : (0,344:0,25);
|
||||
574 : (0,341:30,0);
|
||||
576 : (0,342:26,0);
|
||||
617 : (0,309:5,0);
|
||||
645 : (0,344:0,0);
|
||||
729 : (0,324:52,0);
|
||||
757 : (0,324:60,0);
|
||||
785 : (0,324:68,0);
|
||||
813 : (0,324:76,0);
|
||||
841 : (0,329:58,0);
|
||||
869 : (0,329:68,0);
|
||||
897 : (0,329:78,0);
|
||||
925 : (0,329:88,0);
|
||||
965 : (0,309:5,0);
|
||||
967 : (0,344:0,0);
|
||||
971 : (0,324:52,0);
|
||||
989 : (0,340:4,13);
|
||||
1022 : (0,335:16,0);
|
||||
1023 : (0,335:16,9);
|
||||
1024 : (0,335:16,9);
|
||||
1025 : (0,335:16,9);
|
||||
1026 : (0,335:16,9);
|
||||
1027 : (0,335:16,9);
|
||||
1028 : (0,335:16,9);
|
||||
1034 : (0,335:7,0);
|
||||
1035 : (0,335:7,9);
|
||||
1036 : (0,335:7,9);
|
||||
1037 : (0,335:7,9);
|
||||
1038 : (0,335:7,9);
|
||||
1039 : (0,335:7,9);
|
||||
1098 : (0,340:4,13);
|
||||
1127 : (0,340:4,13);
|
||||
1133 : (0,340:4,20);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-a30375.#
Normal file
8
simulation/Release/chesswork/signal_path-a30375.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
cd3d7a324e5803ca379119c6ac3a521de85c2d58
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
02bb82ee2ad0a49c939022d10fb51d620f2409d2
|
||||
194
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-a30375.o
Normal file
BIN
simulation/Release/chesswork/signal_path-a30375.o
Normal file
Binary file not shown.
226
simulation/Release/chesswork/signal_path-a30375.sfg
Normal file
226
simulation/Release/chesswork/signal_path-a30375.sfg
Normal file
@@ -0,0 +1,226 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
|
||||
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_delay_buffer_load_and_get" 'int sig_delay_buffer_load_and_get(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! void sig_cirular_buffer_ptr_increment(BufferPtr *, int)
|
||||
F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_increment" 'void sig_cirular_buffer_ptr_increment(BufferPtr *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z29sig_delay_buffer_load_and_getP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___2
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
29 : __vola typ=uint20_ bnd=b stl=PM
|
||||
32 : __extDM typ=int8_ bnd=b stl=DM
|
||||
33 : __extPM typ=uint20_ bnd=b stl=PM
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
|
||||
36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
|
||||
37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath_delay_buffer_buffer_len typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_SingleSignalPath_delay_buffer_ptr_current typ=int8_ bnd=b stl=DM
|
||||
41 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
|
||||
42 : __extDM_void typ=int8_ bnd=b stl=DM
|
||||
43 : __extPM_void typ=uint20_ bnd=b stl=PM
|
||||
44 : __rd___sp typ=dmaddr_ bnd=m
|
||||
45 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
46 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
47 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
48 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
49 : x typ=int32_ bnd=p tref=__sint__
|
||||
57 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
60 : __fch___extDM_SingleSignalPath_delay_buffer_buffer_len typ=int32_ bnd=m
|
||||
63 : __tmp typ=bool bnd=m
|
||||
70 : __fch___extDM_SingleSignalPath_delay_buffer_ptr_current typ=dmaddr_ bnd=m
|
||||
81 : __tmp typ=dmaddr_ bnd=m
|
||||
82 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
83 : __ct typ=int32_ bnd=m
|
||||
84 : _Z32sig_cirular_buffer_ptr_incrementP9BufferPtri typ=dmaddr_ val=0r bnd=m
|
||||
86 : __link typ=dmaddr_ bnd=m
|
||||
100 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
124 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
125 : __ct_116 typ=int18_ val=116f bnd=m
|
||||
128 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
130 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
134 : __tmp typ=uint3_ bnd=m
|
||||
144 : __either typ=bool bnd=m
|
||||
145 : __trgt typ=int10_ val=0j bnd=m
|
||||
146 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi {
|
||||
#228 off=0
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__vola.27 var=29) source () <51>;
|
||||
(__extDM.30 var=32) source () <54>;
|
||||
(__extPM.31 var=33) source () <55>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath.33 var=35) source () <57>;
|
||||
(__extDM_SingleSignalPath_delay_buffer.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtr.35 var=37) source () <59>;
|
||||
(__extDM_SingleSignalPath_delay_buffer_buffer_len.36 var=38) source () <60>;
|
||||
(__extDM_int32_.37 var=39) source () <61>;
|
||||
(__extDM_SingleSignalPath_delay_buffer_ptr_current.38 var=40) source () <62>;
|
||||
(__extDM___PDMint32_.39 var=41) source () <63>;
|
||||
(__extDM_void.40 var=42) source () <64>;
|
||||
(__extPM_void.41 var=43) source () <65>;
|
||||
(__ct_0.43 var=45) const () <67>;
|
||||
(__la.45 var=46 stl=LR off=0) inp () <69>;
|
||||
(__la.46 var=46) deassign (__la.45) <70>;
|
||||
(signal.49 var=48 stl=A off=0) inp () <73>;
|
||||
(signal.50 var=48) deassign (signal.49) <74>;
|
||||
(x.52 var=49 stl=RA off=1) inp () <76>;
|
||||
(x.53 var=49) deassign (x.52) <77>;
|
||||
(__rd___sp.55 var=44) rd_res_reg (__R_SP.24 __sp.32) <79>;
|
||||
(__R_SP.59 var=26 __sp.60 var=34) wr_res_reg (__rt.195 __sp.32) <83>;
|
||||
(__ct_0.65 var=57) const () <89>;
|
||||
(__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 var=60) load (__M_WDMA.9 __rt.217 __extDM_SingleSignalPath_delay_buffer_buffer_len.36) <92>;
|
||||
(__rt.195 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.55 __ct_0S0.296) <259>;
|
||||
(__rt.217 var=100) __Pvoid__pl___Pvoid_int18_ (signal.50 __ct_116.297) <287>;
|
||||
(__ct_0S0.296 var=124) const () <399>;
|
||||
(__ct_116.297 var=125) const () <401>;
|
||||
(__tmp.305 var=134) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 __ct_0.65) <416>;
|
||||
(__tmp.306 var=63) bool_equal_uint3_ (__tmp.305) <417>;
|
||||
(__trgt.314 var=145) const () <457>;
|
||||
() void_jump_bool_int10_ (__tmp.306 __trgt.314) <458>;
|
||||
(__either.315 var=144) undefined () <459>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.315) <116>;
|
||||
} #5
|
||||
{
|
||||
} #6 off=4
|
||||
{
|
||||
#157 off=1
|
||||
(__fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 var=70) load (__M_WDMA.9 __rt.239 __extDM_SingleSignalPath_delay_buffer_ptr_current.38) <124>;
|
||||
(__rt.100 var=47) load (__M_WDMA.9 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37) <125>;
|
||||
(__M_WDMA.108 var=11 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 var=38 __extDM_int32_.110 var=39) store (x.53 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37) <133>;
|
||||
(__ct_1.115 var=82) const () <138>;
|
||||
(_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri.118 var=84) const () <141>;
|
||||
(__link.120 var=86) dmaddr__call_dmaddr_ (_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri.118) <143>;
|
||||
(__rt.239 var=100) __Pvoid__pl___Pvoid_int18_ (__rt.217 __ct_8.300) <315>;
|
||||
(__rt.283 var=100) __Pvoid__mi___Pvoid_int18_ (__rt.239 __ct_8.300) <371>;
|
||||
(__ct_8.300 var=128) const () <407>;
|
||||
call {
|
||||
(__tmp.114 var=81 stl=A off=0) assign (__rt.283) <137>;
|
||||
(__ct.117 var=83 stl=RA off=0) assign (__ct_1.115) <140>;
|
||||
(__link.121 var=86 stl=LR off=0) assign (__link.120) <144>;
|
||||
(__extDM.122 var=32 __extDM_BufferPtr.123 var=37 __extDM_SingleSignalPath.124 var=35 __extDM_SingleSignalPath_delay_buffer.125 var=36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126 var=38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127 var=40 __extDM___PDMint32_.128 var=41 __extDM_int32_.129 var=39 __extDM_void.130 var=42 __extPM.131 var=33 __extPM_void.132 var=43 __vola.133 var=29) F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri (__link.121 __tmp.114 __ct.117 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 __extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM___PDMint32_.39 __extDM_int32_.110 __extDM_void.40 __extPM.31 __extPM_void.41 __vola.27) <145>;
|
||||
} #9 off=2
|
||||
#231 off=3
|
||||
(__trgt.316 var=146) const () <460>;
|
||||
() void_jump_int10_ (__trgt.316) <461>;
|
||||
} #7
|
||||
{
|
||||
(__vola.134 var=29) merge (__vola.27 __vola.133) <146>;
|
||||
(__extDM.135 var=32) merge (__extDM.30 __extDM.122) <147>;
|
||||
(__extPM.136 var=33) merge (__extPM.31 __extPM.131) <148>;
|
||||
(__extDM_SingleSignalPath.137 var=35) merge (__extDM_SingleSignalPath.33 __extDM_SingleSignalPath.124) <149>;
|
||||
(__extDM_SingleSignalPath_delay_buffer.138 var=36) merge (__extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer.125) <150>;
|
||||
(__extDM_BufferPtr.139 var=37) merge (__extDM_BufferPtr.35 __extDM_BufferPtr.123) <151>;
|
||||
(__extDM_SingleSignalPath_delay_buffer_buffer_len.140 var=38) merge (__extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126) <152>;
|
||||
(__extDM_int32_.141 var=39) merge (__extDM_int32_.37 __extDM_int32_.129) <153>;
|
||||
(__extDM_SingleSignalPath_delay_buffer_ptr_current.142 var=40) merge (__extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127) <154>;
|
||||
(__extDM___PDMint32_.143 var=41) merge (__extDM___PDMint32_.39 __extDM___PDMint32_.128) <155>;
|
||||
(__extDM_void.144 var=42) merge (__extDM_void.40 __extDM_void.130) <156>;
|
||||
(__extPM_void.145 var=43) merge (__extPM_void.41 __extPM_void.132) <157>;
|
||||
(__rt.146 var=47) merge (x.53 __rt.100) <158>;
|
||||
} #10
|
||||
} #4
|
||||
#12 off=5 nxt=-2
|
||||
(__rd___sp.148 var=44) rd_res_reg (__R_SP.24 __sp.60) <160>;
|
||||
(__R_SP.152 var=26 __sp.153 var=34) wr_res_reg (__rt.261 __sp.60) <164>;
|
||||
() void_ret_dmaddr_ (__la.46) <165>;
|
||||
(__rt.154 var=47 stl=RA off=0) assign (__rt.146) <166>;
|
||||
() out (__rt.154) <167>;
|
||||
() sink (__vola.134) <168>;
|
||||
() sink (__extDM.135) <171>;
|
||||
() sink (__extPM.136) <172>;
|
||||
() sink (__sp.153) <173>;
|
||||
() sink (__extDM_SingleSignalPath.137) <174>;
|
||||
() sink (__extDM_SingleSignalPath_delay_buffer.138) <175>;
|
||||
() sink (__extDM_BufferPtr.139) <176>;
|
||||
() sink (__extDM_SingleSignalPath_delay_buffer_buffer_len.140) <177>;
|
||||
() sink (__extDM_int32_.141) <178>;
|
||||
() sink (__extDM_SingleSignalPath_delay_buffer_ptr_current.142) <179>;
|
||||
() sink (__extDM___PDMint32_.143) <180>;
|
||||
() sink (__extDM_void.144) <181>;
|
||||
() sink (__extPM_void.145) <182>;
|
||||
() sink (__ct_0.43) <183>;
|
||||
(__rt.261 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.148 __ct_0s0.302) <343>;
|
||||
(__ct_0s0.302 var=130) const () <411>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,194:0,0);
|
||||
4 : (0,195:4,1);
|
||||
6 : (0,195:46,2);
|
||||
7 : (0,196:8,5);
|
||||
9 : (0,200:4,8);
|
||||
12 : (0,201:4,13);
|
||||
157 : (0,200:4,8);
|
||||
228 : (0,195:40,1);
|
||||
----------
|
||||
79 : (0,194:4,0);
|
||||
83 : (0,194:4,0);
|
||||
89 : (0,195:28,0);
|
||||
92 : (0,195:28,1);
|
||||
116 : (0,195:4,1);
|
||||
124 : (0,198:35,6);
|
||||
125 : (0,198:14,6);
|
||||
133 : (0,199:4,7);
|
||||
137 : (0,200:44,0);
|
||||
138 : (0,200:60,0);
|
||||
140 : (0,200:60,0);
|
||||
143 : (0,200:4,8);
|
||||
144 : (0,200:4,0);
|
||||
145 : (0,200:4,8);
|
||||
146 : (0,195:4,12);
|
||||
147 : (0,195:4,12);
|
||||
148 : (0,195:4,12);
|
||||
149 : (0,195:4,12);
|
||||
150 : (0,195:4,12);
|
||||
151 : (0,195:4,12);
|
||||
152 : (0,195:4,12);
|
||||
153 : (0,195:4,12);
|
||||
154 : (0,195:4,12);
|
||||
155 : (0,195:4,12);
|
||||
156 : (0,195:4,12);
|
||||
157 : (0,195:4,12);
|
||||
158 : (0,195:4,12);
|
||||
160 : (0,201:4,0);
|
||||
164 : (0,201:4,13);
|
||||
165 : (0,201:4,13);
|
||||
166 : (0,201:4,0);
|
||||
259 : (0,194:4,0);
|
||||
287 : (0,195:14,1);
|
||||
315 : (0,198:35,6);
|
||||
343 : (0,201:4,0);
|
||||
371 : (0,195:14,0);
|
||||
399 : (0,194:4,0);
|
||||
401 : (0,195:14,0);
|
||||
407 : (0,198:35,0);
|
||||
411 : (0,201:4,0);
|
||||
416 : (0,195:40,1);
|
||||
417 : (0,195:40,1);
|
||||
458 : (0,195:4,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-d6dbe4.#
Normal file
8
simulation/Release/chesswork/signal_path-d6dbe4.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
ab6f52618a5136888eb86a044b33767c8d77620c
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
340d9ea84ad046dfee07a971bcee354e65107347
|
||||
173
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-d6dbe4.o
Normal file
BIN
simulation/Release/chesswork/signal_path-d6dbe4.o
Normal file
Binary file not shown.
245
simulation/Release/chesswork/signal_path-d6dbe4.sfg
Normal file
245
simulation/Release/chesswork/signal_path-d6dbe4.sfg
Normal file
@@ -0,0 +1,245 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_calc_biquad(SingleSignalPath *, int)
|
||||
F_Z15sig_calc_biquadP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_calc_biquad" 'int sig_calc_biquad(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z15sig_calc_biquadP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___1
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_SingleSignalPath_preemph_activated typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath_b_preemph typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_SingleSignalPath__xd typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_SingleSignalPath__yd typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
45 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
46 : x typ=int32_ bnd=p tref=__sint__
|
||||
50 : sum typ=int72_ bnd=m lscp=591 tref=accum_t__
|
||||
55 : __fch___extDM_SingleSignalPath_preemph_activated typ=int32_ bnd=m
|
||||
56 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
58 : __tmp typ=bool bnd=m
|
||||
65 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m
|
||||
66 : __tmp typ=int72_ bnd=m
|
||||
73 : __fch___extDM_SingleSignalPath__xd typ=int32_ bnd=m
|
||||
80 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m
|
||||
81 : __tmp typ=int72_ bnd=m
|
||||
82 : __tmp typ=int72_ bnd=m
|
||||
89 : __fch___extDM_SingleSignalPath__xd typ=int32_ bnd=m
|
||||
96 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m
|
||||
97 : __tmp typ=int72_ bnd=m
|
||||
98 : __tmp typ=int72_ bnd=m
|
||||
105 : __fch___extDM_SingleSignalPath__yd typ=int32_ bnd=m
|
||||
112 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m
|
||||
113 : __tmp typ=int72_ bnd=m
|
||||
114 : __tmp typ=int72_ bnd=m
|
||||
121 : __fch___extDM_SingleSignalPath__yd typ=int32_ bnd=m
|
||||
128 : __fch___extDM_SingleSignalPath_b_preemph typ=int32_ bnd=m
|
||||
129 : __tmp typ=int72_ bnd=m
|
||||
131 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
133 : __tmp typ=int72_ bnd=m
|
||||
197 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
232 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
233 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
236 : __ct_12 typ=int18_ val=12f bnd=m
|
||||
239 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
240 : __ct_24 typ=int18_ val=24f bnd=m
|
||||
242 : __ct_20 typ=int18_ val=20f bnd=m
|
||||
244 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
248 : __tmp typ=uint3_ bnd=m
|
||||
253 : __ct_0 typ=uint2_ val=0f bnd=m
|
||||
263 : __either typ=bool bnd=m
|
||||
264 : __trgt typ=int10_ val=0j bnd=m
|
||||
265 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z15sig_calc_biquadP16SingleSignalPathi {
|
||||
#553 off=0
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath_preemph_activated.34 var=36) source () <58>;
|
||||
(__extDM_SingleSignalPath_b_preemph.36 var=38) source () <60>;
|
||||
(__extDM_SingleSignalPath__xd.37 var=39) source () <61>;
|
||||
(__extDM_SingleSignalPath__yd.38 var=40) source () <62>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(signal.46 var=45 stl=A off=0) inp () <70>;
|
||||
(signal.47 var=45) deassign (signal.46) <71>;
|
||||
(x.49 var=46 stl=RA off=1) inp () <73>;
|
||||
(x.50 var=46) deassign (x.49) <74>;
|
||||
(__rd___sp.52 var=41) rd_res_reg (__R_SP.24 __sp.32) <76>;
|
||||
(__R_SP.56 var=26 __sp.57 var=34) wr_res_reg (__rt.297 __sp.32) <80>;
|
||||
(__fch___extDM_SingleSignalPath_preemph_activated.63 var=55) load (__M_WDMA.9 __rt.319 __extDM_SingleSignalPath_preemph_activated.34) <87>;
|
||||
(__ct_0.64 var=56) const () <88>;
|
||||
(__rt.297 var=197) __Pvoid__pl___Pvoid_int18_ (__rd___sp.52 __ct_0S0.640) <391>;
|
||||
(__rt.319 var=197) __Pvoid__pl___Pvoid_int18_ (signal.47 __ct_8.641) <419>;
|
||||
(__ct_0S0.640 var=232) const () <840>;
|
||||
(__ct_8.641 var=233) const () <842>;
|
||||
(__tmp.655 var=248) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_preemph_activated.63 __ct_0.64) <869>;
|
||||
(__tmp.656 var=58) bool_equal_uint3_ (__tmp.655) <870>;
|
||||
(__trgt.669 var=264) const () <927>;
|
||||
() void_jump_bool_int10_ (__tmp.656 __trgt.669) <928>;
|
||||
(__either.670 var=263) undefined () <929>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.670) <109>;
|
||||
} #5
|
||||
{
|
||||
} #6 off=2
|
||||
{
|
||||
(__fch___extDM_SingleSignalPath_b_preemph.92 var=65) load (__M_WDMA.9 __rt.341 __extDM_SingleSignalPath_b_preemph.36) <117>;
|
||||
(__fch___extDM_SingleSignalPath__xd.100 var=73) load (__M_WDMA.9 __rt.385 __extDM_SingleSignalPath__xd.37) <125>;
|
||||
(__fch___extDM_SingleSignalPath_b_preemph.107 var=80) load (__M_WDMA.9 __rt.407 __extDM_SingleSignalPath_b_preemph.36) <132>;
|
||||
(__tmp.109 var=82) accum_t__pl_accum_t_accum_t (__tmp.244 __tmp.249) <134>;
|
||||
(__fch___extDM_SingleSignalPath__xd.116 var=89) load (__M_WDMA.9 __rt.429 __extDM_SingleSignalPath__xd.37) <141>;
|
||||
(__fch___extDM_SingleSignalPath_b_preemph.123 var=96) load (__M_WDMA.9 __rt.451 __extDM_SingleSignalPath_b_preemph.36) <148>;
|
||||
(__tmp.125 var=98) accum_t__pl_accum_t_accum_t (__tmp.109 __tmp.254) <150>;
|
||||
(__fch___extDM_SingleSignalPath__yd.132 var=105) load (__M_WDMA.9 __rt.473 __extDM_SingleSignalPath__yd.38) <157>;
|
||||
(__fch___extDM_SingleSignalPath_b_preemph.139 var=112) load (__M_WDMA.9 __rt.495 __extDM_SingleSignalPath_b_preemph.36) <164>;
|
||||
(__tmp.141 var=114) accum_t__pl_accum_t_accum_t (__tmp.125 __tmp.259) <166>;
|
||||
(__fch___extDM_SingleSignalPath__yd.148 var=121) load (__M_WDMA.9 __rt.517 __extDM_SingleSignalPath__yd.38) <173>;
|
||||
(__fch___extDM_SingleSignalPath_b_preemph.155 var=128) load (__M_WDMA.9 __rt.539 __extDM_SingleSignalPath_b_preemph.36) <180>;
|
||||
(sum.157 var=50) accum_t__pl_accum_t_accum_t (__tmp.141 __tmp.264) <182>;
|
||||
(__ct_1.159 var=131) const () <184>;
|
||||
(__rt.162 var=44) __sint_rnd_saturate_accum_t (__tmp.661) <187>;
|
||||
(__M_WDMA.176 var=11 __extDM_SingleSignalPath__xd.177 var=39) store (__fch___extDM_SingleSignalPath__xd.100 __rt.561 __extDM_SingleSignalPath__xd.37) <201>;
|
||||
(__M_WDMA.184 var=11 __extDM_SingleSignalPath__xd.185 var=39) store (x.50 __rt.583 __extDM_SingleSignalPath__xd.177) <208>;
|
||||
(__M_WDMA.199 var=11 __extDM_SingleSignalPath__yd.200 var=40) store (__fch___extDM_SingleSignalPath__yd.132 __rt.605 __extDM_SingleSignalPath__yd.38) <222>;
|
||||
(__M_WDMA.207 var=11 __extDM_SingleSignalPath__yd.208 var=40) store (__rt.162 __rt.627 __extDM_SingleSignalPath__yd.200) <229>;
|
||||
(__tmp.244 var=66) int72__multss_int32__int32__uint1_ (x.50 __fch___extDM_SingleSignalPath_b_preemph.92 __ct_0.40) <293>;
|
||||
(__tmp.249 var=81) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__xd.100 __fch___extDM_SingleSignalPath_b_preemph.107 __ct_0.40) <301>;
|
||||
(__tmp.254 var=97) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__xd.116 __fch___extDM_SingleSignalPath_b_preemph.123 __ct_0.40) <309>;
|
||||
(__tmp.259 var=113) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__yd.132 __fch___extDM_SingleSignalPath_b_preemph.139 __ct_0.40) <317>;
|
||||
(__tmp.264 var=129) int72__multss_int32__int32__uint1_ (__fch___extDM_SingleSignalPath__yd.148 __fch___extDM_SingleSignalPath_b_preemph.155 __ct_0.40) <325>;
|
||||
(__rt.341 var=197) __Pvoid__pl___Pvoid_int18_ (signal.47 __ct_12.644) <447>;
|
||||
(__rt.385 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.341 __ct_24.648) <503>;
|
||||
(__rt.407 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.385 __ct_20.650) <531>;
|
||||
(__rt.429 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.407 __ct_24.648) <559>;
|
||||
(__rt.451 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.429 __ct_20.650) <587>;
|
||||
(__rt.473 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.451 __ct_24.648) <615>;
|
||||
(__rt.495 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.473 __ct_20.650) <643>;
|
||||
(__rt.517 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.495 __ct_24.648) <671>;
|
||||
(__rt.539 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.517 __ct_20.650) <699>;
|
||||
(__rt.561 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.539 __ct_12.644) <727>;
|
||||
(__rt.583 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.561 __ct_4.652) <755>;
|
||||
(__rt.605 var=197) __Pvoid__pl___Pvoid_int18_ (__rt.583 __ct_12.644) <783>;
|
||||
(__rt.627 var=197) __Pvoid__mi___Pvoid_int18_ (__rt.605 __ct_4.652) <811>;
|
||||
(__ct_12.644 var=236) const () <848>;
|
||||
(__ct_24.648 var=240) const () <856>;
|
||||
(__ct_20.650 var=242) const () <860>;
|
||||
(__ct_4.652 var=244) const () <864>;
|
||||
(__ct_0.660 var=253) const () <877>;
|
||||
(__tmp.661 var=133) int72__shift_int72__int72__uint2_ (sum.157 __ct_1.159 __ct_0.660) <878>;
|
||||
(__trgt.671 var=265) const () <930>;
|
||||
() void_jump_int10_ (__trgt.671) <931>;
|
||||
} #591 off=1
|
||||
{
|
||||
(__extDM_SingleSignalPath__xd.209 var=39) merge (__extDM_SingleSignalPath__xd.37 __extDM_SingleSignalPath__xd.185) <230>;
|
||||
(__extDM_SingleSignalPath__yd.210 var=40) merge (__extDM_SingleSignalPath__yd.38 __extDM_SingleSignalPath__yd.208) <231>;
|
||||
(__rt.211 var=44) merge (x.50 __rt.162) <232>;
|
||||
} #8
|
||||
} #4
|
||||
#10 off=3 nxt=-2
|
||||
(__rd___sp.214 var=41) rd_res_reg (__R_SP.24 __sp.57) <235>;
|
||||
(__R_SP.218 var=26 __sp.219 var=34) wr_res_reg (__rt.363 __sp.57) <239>;
|
||||
() void_ret_dmaddr_ (__la.43) <240>;
|
||||
(__rt.220 var=44 stl=RA off=0) assign (__rt.211) <241>;
|
||||
() out (__rt.220) <242>;
|
||||
() sink (__sp.219) <248>;
|
||||
() sink (__extDM_SingleSignalPath__xd.209) <253>;
|
||||
() sink (__extDM_SingleSignalPath__yd.210) <254>;
|
||||
() sink (__ct_0.40) <255>;
|
||||
(__rt.363 var=197) __Pvoid__pl___Pvoid_int18_ (__rd___sp.214 __ct_0s0.647) <475>;
|
||||
(__ct_0s0.647 var=239) const () <854>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,173:0,0);
|
||||
4 : (0,174:4,1);
|
||||
6 : (0,174:40,2);
|
||||
10 : (0,188:4,16);
|
||||
553 : (0,174:34,1);
|
||||
591 : (0,187:15,11);
|
||||
----------
|
||||
76 : (0,173:4,0);
|
||||
80 : (0,173:4,0);
|
||||
87 : (0,174:14,1);
|
||||
88 : (0,174:37,0);
|
||||
109 : (0,174:4,1);
|
||||
117 : (0,178:39,6);
|
||||
125 : (0,178:68,6);
|
||||
132 : (0,178:90,6);
|
||||
134 : (0,178:44,6);
|
||||
141 : (0,179:30,6);
|
||||
148 : (0,179:52,6);
|
||||
150 : (0,178:95,6);
|
||||
157 : (0,179:81,6);
|
||||
164 : (0,179:103,6);
|
||||
166 : (0,179:57,6);
|
||||
173 : (0,180:30,6);
|
||||
180 : (0,180:51,6);
|
||||
182 : (0,179:108,6);
|
||||
184 : (0,181:32,0);
|
||||
187 : (0,181:12,7);
|
||||
201 : (0,184:15,8);
|
||||
208 : (0,185:15,9);
|
||||
222 : (0,186:15,10);
|
||||
229 : (0,187:15,11);
|
||||
230 : (0,174:4,15);
|
||||
231 : (0,174:4,15);
|
||||
232 : (0,174:4,15);
|
||||
235 : (0,188:4,0);
|
||||
239 : (0,188:4,16);
|
||||
240 : (0,188:4,16);
|
||||
241 : (0,188:4,0);
|
||||
293 : (0,178:8,6);
|
||||
301 : (0,178:46,6);
|
||||
309 : (0,179:8,6);
|
||||
317 : (0,179:59,6);
|
||||
325 : (0,180:8,6);
|
||||
391 : (0,173:4,0);
|
||||
419 : (0,174:14,1);
|
||||
447 : (0,178:28,6);
|
||||
475 : (0,188:4,0);
|
||||
503 : (0,178:63,0);
|
||||
531 : (0,178:90,0);
|
||||
559 : (0,179:30,0);
|
||||
587 : (0,179:52,0);
|
||||
615 : (0,179:76,0);
|
||||
643 : (0,179:103,0);
|
||||
671 : (0,180:30,0);
|
||||
699 : (0,180:51,0);
|
||||
727 : (0,179:30,0);
|
||||
755 : (0,178:63,0);
|
||||
783 : (0,180:30,0);
|
||||
811 : (0,179:76,0);
|
||||
840 : (0,173:4,0);
|
||||
842 : (0,174:14,0);
|
||||
848 : (0,178:28,0);
|
||||
854 : (0,188:4,0);
|
||||
856 : (0,178:63,0);
|
||||
860 : (0,178:90,0);
|
||||
864 : (0,178:63,0);
|
||||
869 : (0,174:34,1);
|
||||
870 : (0,174:34,1);
|
||||
877 : (0,181:29,0);
|
||||
878 : (0,181:29,7);
|
||||
928 : (0,174:4,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-d74ce2.#
Normal file
8
simulation/Release/chesswork/signal_path-d74ce2.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
e2ded2b6178a19a31d3cb7b39f694325b2214d67
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
4647624aebdbf5e32824e242277d6279ea22a0eb
|
||||
157
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-d74ce2.o
Normal file
BIN
simulation/Release/chesswork/signal_path-d74ce2.o
Normal file
Binary file not shown.
369
simulation/Release/chesswork/signal_path-d74ce2.sfg
Normal file
369
simulation/Release/chesswork/signal_path-d74ce2.sfg
Normal file
@@ -0,0 +1,369 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_init_weight(SingleSignalPath *, double, int)
|
||||
F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
|
||||
fnm : "sig_init_weight" 'void sig_init_weight(SingleSignalPath *, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! extern double ff_pow(double, double)
|
||||
Fff_pow : user_defined, called {
|
||||
fnm : "ff_pow" 'double ff_pow(double, double)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int float64_eq(float64, float64)
|
||||
F_Z10float64_eqyy : user_defined, called {
|
||||
fnm : "float64_eq" 'int float64_eq(float64, float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] AX[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 int32_to_float64(int)
|
||||
F_Z16int32_to_float64i : user_defined, called {
|
||||
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
|
||||
arg : ( dmaddr_:i int64_:r int32_:i );
|
||||
loc : ( LR[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_sub(float64, float64)
|
||||
F_Z11float64_subyy : user_defined, called {
|
||||
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! int float64_to_int32_round_to_zero(float64)
|
||||
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
|
||||
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_mul(float64, float64)
|
||||
F_Z11float64_mulyy : user_defined, called {
|
||||
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z15sig_init_weightP16SingleSignalPathdi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___fdouble___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_SingleSignalPath_weight_actived typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath_weight typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_SingleSignalPath__weight_scale_nbits typ=int8_ bnd=b stl=DM
|
||||
40 : __rd___sp typ=dmaddr_ bnd=m
|
||||
41 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
42 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
44 : weight typ=int64_ bnd=p tref=__fdouble__
|
||||
45 : scale_nbits typ=int32_ bnd=p tref=__sint__
|
||||
49 : __tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi typ=int64_ bnd=m lscp=181 tref=__fdouble__
|
||||
50 : __tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi typ=int64_ bnd=m lscp=181 tref=__fdouble__
|
||||
52 : scale typ=int32_ bnd=m lscp=181 tref=__sint__
|
||||
53 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
|
||||
56 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
61 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
67 : __ct_4611686018427387904 typ=int64_ val=4611686018427387904f bnd=m
|
||||
72 : __tmp typ=int64_ bnd=m
|
||||
74 : __tmp typ=int64_ bnd=m
|
||||
75 : __tmp typ=int64_ bnd=m
|
||||
76 : __tmp typ=int32_ bnd=m
|
||||
96 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
117 : __tmp typ=int32_ bnd=m
|
||||
126 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
127 : __ct_132 typ=int18_ val=132f bnd=m
|
||||
130 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
131 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
135 : __tmp typ=bool bnd=m
|
||||
142 : __a0 typ=int64_ bnd=m tref=__atp0___48
|
||||
144 : ff_pow typ=dmaddr_ val=0r bnd=m
|
||||
145 : __link typ=dmaddr_ bnd=m
|
||||
162 : __a1 typ=int64_ bnd=m tref=__atp1___12
|
||||
163 : _Z10float64_eqyy typ=dmaddr_ val=0r bnd=m
|
||||
164 : __link typ=dmaddr_ bnd=m
|
||||
170 : __tmp typ=uint3_ bnd=m
|
||||
175 : _Z16int32_to_float64i typ=dmaddr_ val=0r bnd=m
|
||||
176 : __link typ=dmaddr_ bnd=m
|
||||
178 : __tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi typ=int64_ bnd=m
|
||||
180 : __a1 typ=int64_ bnd=m tref=__atp1___9
|
||||
181 : _Z11float64_subyy typ=dmaddr_ val=0r bnd=m
|
||||
182 : __link typ=dmaddr_ bnd=m
|
||||
184 : __tmp typ=int64_ bnd=m
|
||||
186 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
|
||||
187 : __link typ=dmaddr_ bnd=m
|
||||
190 : __tmp typ=int64_ bnd=m
|
||||
193 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
|
||||
194 : __link typ=dmaddr_ bnd=m
|
||||
196 : __tmp typ=int64_ bnd=m
|
||||
206 : __either typ=bool bnd=m
|
||||
207 : __trgt typ=int10_ val=0j bnd=m
|
||||
208 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z15sig_init_weightP16SingleSignalPathdi {
|
||||
#272 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath_weight_actived.34 var=36) source () <58>;
|
||||
(__extDM_SingleSignalPath_weight.36 var=38) source () <60>;
|
||||
(__extDM_SingleSignalPath__weight_scale_nbits.37 var=39) source () <61>;
|
||||
(__ct_0.39 var=41) const () <63>;
|
||||
(__la.41 var=42 stl=LR off=0) inp () <65>;
|
||||
(__la.42 var=42) deassign (__la.41) <66>;
|
||||
(signal.44 var=43 stl=A off=0) inp () <68>;
|
||||
(signal.45 var=43) deassign (signal.44) <69>;
|
||||
(weight.47 var=44 stl=AX off=0) inp () <71>;
|
||||
(weight.48 var=44) deassign (weight.47) <72>;
|
||||
(scale_nbits.50 var=45 stl=RA off=0) inp () <74>;
|
||||
(scale_nbits.51 var=45) deassign (scale_nbits.50) <75>;
|
||||
(__rd___sp.53 var=40) rd_res_reg (__R_SP.24 __sp.32) <77>;
|
||||
(__R_SP.57 var=26 __sp.58 var=34) wr_res_reg (__rt.177 __sp.32) <81>;
|
||||
(__ct_4607182418800017408.63 var=53) const () <87>;
|
||||
(__rt.177 var=96) __Pvoid__pl___Pvoid_int18_ (__rd___sp.53 __ct_0S0.284) <249>;
|
||||
(__ct_0S0.284 var=126) const () <398>;
|
||||
(_Z10float64_eqyy.329 var=163) const () <485>;
|
||||
(__link.330 var=164) dmaddr__call_dmaddr_ (_Z10float64_eqyy.329) <486>;
|
||||
call {
|
||||
(weight.331 var=44 stl=AX off=0) assign (weight.48) <487>;
|
||||
(__a1.332 var=162 stl=AX off=1) assign (__ct_4607182418800017408.63) <488>;
|
||||
(__link.333 var=164 stl=LR off=0) assign (__link.330) <489>;
|
||||
(__tmp.334 var=117 stl=RA off=0) F_Z10float64_eqyy (__link.333 weight.331 __a1.332) <490>;
|
||||
(__tmp.335 var=117) deassign (__tmp.334) <491>;
|
||||
} #273 off=1
|
||||
#269 off=2
|
||||
(__ct_0.85 var=56) const () <110>;
|
||||
(__rt.205 var=96) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_132.285) <286>;
|
||||
(__ct_132.285 var=127) const () <400>;
|
||||
(__tmp.339 var=170) uint3__cmp_int72__int72_ (__tmp.335 __ct_0.85) <498>;
|
||||
(__tmp.344 var=135) bool_nequal_uint3_ (__tmp.339) <518>;
|
||||
(__trgt.403 var=207) const () <646>;
|
||||
() void_jump_bool_int10_ (__tmp.344 __trgt.403) <647>;
|
||||
(__either.404 var=206) undefined () <648>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.404) <109>;
|
||||
} #5
|
||||
{
|
||||
(__M_WDMA.90 var=11 __extDM_SingleSignalPath_weight_actived.91 var=36) store (__ct_0.85 __rt.205 __extDM_SingleSignalPath_weight_actived.34) <115>;
|
||||
} #6 off=18
|
||||
{
|
||||
#285 off=3
|
||||
(__ct_1.92 var=61) const () <116>;
|
||||
(__M_WDMA.97 var=11 __extDM_SingleSignalPath_weight_actived.98 var=36) store (__ct_1.92 __rt.205 __extDM_SingleSignalPath_weight_actived.34) <121>;
|
||||
(__rt.249 var=96) __Pvoid__pl___Pvoid_int18_ (__rt.205 __ct_4.289) <342>;
|
||||
(__ct_4.289 var=131) const () <408>;
|
||||
(_Z16int32_to_float64i.346 var=175) const () <521>;
|
||||
(__link.347 var=176) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.346) <522>;
|
||||
call {
|
||||
(scale_nbits.348 var=45 stl=RA off=0) assign (scale_nbits.51) <523>;
|
||||
(__link.349 var=176 stl=LR off=0) assign (__link.347) <524>;
|
||||
(__tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.350 var=178 stl=AX off=0) F_Z16int32_to_float64i (__link.349 scale_nbits.348) <525>;
|
||||
(__tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.351 var=50) deassign (__tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.350) <526>;
|
||||
} #286 off=4
|
||||
#282 off=5
|
||||
(__ct_4611686018427387904.104 var=67) const () <127>;
|
||||
(ff_pow.302 var=144) const () <440>;
|
||||
(__link.303 var=145) dmaddr__call_dmaddr_ (ff_pow.302) <441>;
|
||||
call {
|
||||
(__a0.304 var=142 stl=AX off=1) assign (__ct_4611686018427387904.104) <442>;
|
||||
(__tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.305 var=50 stl=BX off=0) assign (__tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.351) <443>;
|
||||
(__link.306 var=145 stl=LR off=0) assign (__link.303) <444>;
|
||||
(__tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.307 var=49 stl=AX off=0) Fff_pow (__link.306 __a0.304 __tmpb2_F_Z15sig_init_weightP16SingleSignalPathdi.305) <445>;
|
||||
(__tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.308 var=49) deassign (__tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.307) <446>;
|
||||
} #248 off=6
|
||||
#299 off=7
|
||||
(_Z11float64_subyy.355 var=181) const () <533>;
|
||||
(__link.356 var=182) dmaddr__call_dmaddr_ (_Z11float64_subyy.355) <534>;
|
||||
call {
|
||||
(__tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.357 var=49 stl=AX off=1) assign (__tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.308) <535>;
|
||||
(__a1.358 var=180 stl=BX off=0) assign (__ct_4607182418800017408.63) <536>;
|
||||
(__link.359 var=182 stl=LR off=0) assign (__link.356) <537>;
|
||||
(__tmp.360 var=184 stl=AX off=0) F_Z11float64_subyy (__link.359 __tmpb0_F_Z15sig_init_weightP16SingleSignalPathdi.357 __a1.358) <538>;
|
||||
(__tmp.361 var=72) deassign (__tmp.360) <539>;
|
||||
} #300 off=8
|
||||
#305 off=9
|
||||
(_Z30float64_to_int32_round_to_zeroy.364 var=186) const () <545>;
|
||||
(__link.365 var=187) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.364) <546>;
|
||||
call {
|
||||
(__tmp.366 var=72 stl=AX off=0) assign (__tmp.361) <547>;
|
||||
(__link.367 var=187 stl=LR off=0) assign (__link.365) <548>;
|
||||
(scale.368 var=52 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.367 __tmp.366) <549>;
|
||||
(scale.369 var=52) deassign (scale.368) <550>;
|
||||
} #306 off=10
|
||||
#311 off=11
|
||||
(__link.373 var=176) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.346) <557>;
|
||||
call {
|
||||
(scale.374 var=52 stl=RA off=0) assign (scale.369) <558>;
|
||||
(__link.375 var=176 stl=LR off=0) assign (__link.373) <559>;
|
||||
(__tmp.376 var=190 stl=AX off=0) F_Z16int32_to_float64i (__link.375 scale.374) <560>;
|
||||
(__tmp.377 var=74) deassign (__tmp.376) <561>;
|
||||
} #312 off=12
|
||||
#317 off=13
|
||||
(_Z11float64_mulyy.381 var=193) const () <568>;
|
||||
(__link.382 var=194) dmaddr__call_dmaddr_ (_Z11float64_mulyy.381) <569>;
|
||||
call {
|
||||
(weight.383 var=44 stl=AX off=1) assign (weight.48) <570>;
|
||||
(__tmp.384 var=74 stl=BX off=0) assign (__tmp.377) <571>;
|
||||
(__link.385 var=194 stl=LR off=0) assign (__link.382) <572>;
|
||||
(__tmp.386 var=196 stl=AX off=0) F_Z11float64_mulyy (__link.385 weight.383 __tmp.384) <573>;
|
||||
(__tmp.387 var=75) deassign (__tmp.386) <574>;
|
||||
} #318 off=14
|
||||
#323 off=15
|
||||
(__link.391 var=187) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.364) <581>;
|
||||
call {
|
||||
(__tmp.392 var=75 stl=AX off=0) assign (__tmp.387) <582>;
|
||||
(__link.393 var=187 stl=LR off=0) assign (__link.391) <583>;
|
||||
(__tmp.394 var=76 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.393 __tmp.392) <584>;
|
||||
(__tmp.395 var=76) deassign (__tmp.394) <585>;
|
||||
} #324 off=16
|
||||
#296 off=17
|
||||
(__M_WDMA.117 var=11 __extDM_SingleSignalPath_weight.118 var=38) store (__tmp.395 __rt.249 __extDM_SingleSignalPath_weight.36) <140>;
|
||||
(__M_WDMA.122 var=11 __extDM_SingleSignalPath__weight_scale_nbits.123 var=39) store (scale_nbits.51 __rt.271 __extDM_SingleSignalPath__weight_scale_nbits.37) <144>;
|
||||
(__rt.271 var=96) __Pvoid__pl___Pvoid_int18_ (__rt.249 __ct_4.289) <370>;
|
||||
(__trgt.405 var=208) const () <649>;
|
||||
() void_jump_int10_ (__trgt.405) <650>;
|
||||
} #181
|
||||
{
|
||||
(__extDM_SingleSignalPath_weight_actived.124 var=36) merge (__extDM_SingleSignalPath_weight_actived.91 __extDM_SingleSignalPath_weight_actived.98) <145>;
|
||||
(__extDM_SingleSignalPath_weight.125 var=38) merge (__extDM_SingleSignalPath_weight.36 __extDM_SingleSignalPath_weight.118) <146>;
|
||||
(__extDM_SingleSignalPath__weight_scale_nbits.126 var=39) merge (__extDM_SingleSignalPath__weight_scale_nbits.37 __extDM_SingleSignalPath__weight_scale_nbits.123) <147>;
|
||||
} #8
|
||||
} #4
|
||||
#10 off=19 nxt=-2
|
||||
(__rd___sp.131 var=40) rd_res_reg (__R_SP.24 __sp.58) <152>;
|
||||
(__R_SP.135 var=26 __sp.136 var=34) wr_res_reg (__rt.227 __sp.58) <156>;
|
||||
() void_ret_dmaddr_ (__la.42) <157>;
|
||||
() sink (__sp.136) <163>;
|
||||
() sink (__extDM_SingleSignalPath_weight_actived.124) <165>;
|
||||
() sink (__extDM_SingleSignalPath_weight.125) <167>;
|
||||
() sink (__extDM_SingleSignalPath__weight_scale_nbits.126) <168>;
|
||||
() sink (__ct_0.39) <169>;
|
||||
(__rt.227 var=96) __Pvoid__pl___Pvoid_int18_ (__rd___sp.131 __ct_0s0.288) <314>;
|
||||
(__ct_0s0.288 var=130) const () <406>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,157:0,0);
|
||||
4 : (0,159:4,1);
|
||||
6 : (0,159:22,2);
|
||||
10 : (0,169:0,22);
|
||||
181 : (0,167:14,18);
|
||||
248 : (0,165:20,13);
|
||||
269 : (0,159:15,1);
|
||||
272 : (0,159:15,1);
|
||||
273 : (0,159:15,1);
|
||||
282 : (0,165:20,13);
|
||||
285 : (0,165:25,10);
|
||||
286 : (0,165:25,10);
|
||||
296 : (0,167:14,18);
|
||||
299 : (0,165:40,16);
|
||||
300 : (0,165:40,16);
|
||||
305 : (0,165:40,16);
|
||||
306 : (0,165:40,16);
|
||||
311 : (0,166:32,17);
|
||||
312 : (0,166:32,17);
|
||||
317 : (0,166:32,17);
|
||||
318 : (0,166:32,17);
|
||||
323 : (0,166:23,17);
|
||||
324 : (0,166:23,17);
|
||||
----------
|
||||
77 : (0,157:5,0);
|
||||
81 : (0,157:5,0);
|
||||
87 : (0,159:18,0);
|
||||
109 : (0,159:4,1);
|
||||
110 : (0,160:33,0);
|
||||
115 : (0,160:14,2);
|
||||
116 : (0,164:33,0);
|
||||
121 : (0,164:14,5);
|
||||
127 : (0,165:20,0);
|
||||
140 : (0,166:14,17);
|
||||
144 : (0,167:14,18);
|
||||
145 : (0,159:4,21);
|
||||
146 : (0,159:4,21);
|
||||
147 : (0,159:4,21);
|
||||
152 : (0,169:0,0);
|
||||
156 : (0,169:0,22);
|
||||
157 : (0,169:0,22);
|
||||
249 : (0,157:5,0);
|
||||
286 : (0,160:14,2);
|
||||
314 : (0,169:0,0);
|
||||
342 : (0,166:14,0);
|
||||
370 : (0,167:14,0);
|
||||
398 : (0,157:5,0);
|
||||
400 : (0,160:14,0);
|
||||
406 : (0,169:0,0);
|
||||
408 : (0,166:14,0);
|
||||
440 : (0,165:20,0);
|
||||
441 : (0,165:20,13);
|
||||
442 : (0,165:20,13);
|
||||
443 : (0,165:20,13);
|
||||
444 : (0,165:20,13);
|
||||
445 : (0,165:20,13);
|
||||
446 : (0,165:20,13);
|
||||
485 : (0,159:15,0);
|
||||
486 : (0,159:15,1);
|
||||
487 : (0,159:15,1);
|
||||
488 : (0,159:15,1);
|
||||
489 : (0,159:15,1);
|
||||
490 : (0,159:15,1);
|
||||
491 : (0,159:15,1);
|
||||
498 : (0,159:15,1);
|
||||
518 : (0,159:15,1);
|
||||
521 : (0,165:25,0);
|
||||
522 : (0,165:25,10);
|
||||
523 : (0,165:25,10);
|
||||
524 : (0,165:25,10);
|
||||
525 : (0,165:25,10);
|
||||
526 : (0,165:25,10);
|
||||
533 : (0,165:40,0);
|
||||
534 : (0,165:40,16);
|
||||
535 : (0,165:40,16);
|
||||
536 : (0,165:40,16);
|
||||
537 : (0,165:40,16);
|
||||
538 : (0,165:40,16);
|
||||
539 : (0,165:40,16);
|
||||
545 : (0,165:40,0);
|
||||
546 : (0,165:40,16);
|
||||
547 : (0,165:40,16);
|
||||
548 : (0,165:40,16);
|
||||
549 : (0,165:40,16);
|
||||
550 : (0,165:40,16);
|
||||
557 : (0,166:32,17);
|
||||
558 : (0,166:32,17);
|
||||
559 : (0,166:32,17);
|
||||
560 : (0,166:32,17);
|
||||
561 : (0,166:32,17);
|
||||
568 : (0,166:32,0);
|
||||
569 : (0,166:32,17);
|
||||
570 : (0,166:32,17);
|
||||
571 : (0,166:32,17);
|
||||
572 : (0,166:32,17);
|
||||
573 : (0,166:32,17);
|
||||
574 : (0,166:32,17);
|
||||
581 : (0,166:23,17);
|
||||
582 : (0,166:23,17);
|
||||
583 : (0,166:23,17);
|
||||
584 : (0,166:23,17);
|
||||
585 : (0,166:23,17);
|
||||
647 : (0,159:4,1);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-e110bc.#
Normal file
8
simulation/Release/chesswork/signal_path-e110bc.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
82c539e4dac9d70a3f1d40c2cee8fa60a9a786fd
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
db8ac96f746c20d8257c01deb0158ddbdd492022
|
||||
114
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-e110bc.o
Normal file
BIN
simulation/Release/chesswork/signal_path-e110bc.o
Normal file
Binary file not shown.
118
simulation/Release/chesswork/signal_path-e110bc.sfg
Normal file
118
simulation/Release/chesswork/signal_path-e110bc.sfg
Normal file
@@ -0,0 +1,118 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_cirular_buffer_ptr_put_sample(BufferPtr *, int)
|
||||
F_Z33sig_cirular_buffer_ptr_put_sampleP9BufferPtri : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_put_sample" 'void sig_cirular_buffer_ptr_put_sample(BufferPtr *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z33sig_cirular_buffer_ptr_put_sampleP9BufferPtri typ=uint20_ bnd=e stl=PM tref=void_____PBufferPtr___sint___1
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_BufferPtr_ptr_current typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtr_ptr_start typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_BufferPtr_buffer_len typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : buffer typ=dmaddr_ bnd=p tref=__PBufferPtr__
|
||||
45 : sample typ=int32_ bnd=p tref=__sint__
|
||||
52 : __fch___extDM_BufferPtr_ptr_current typ=dmaddr_ bnd=m
|
||||
62 : __fch___extDM_BufferPtr_ptr_start typ=dmaddr_ bnd=m
|
||||
66 : __fch___extDM_BufferPtr_buffer_len typ=int32_ bnd=m
|
||||
70 : __tmp typ=dmaddr_ bnd=m
|
||||
89 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
94 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
97 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
122 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
123 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
126 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
131 : __ct_2 typ=uint2_ val=2f bnd=m
|
||||
135 : __tmp typ=int18_ bnd=m
|
||||
]
|
||||
F_Z33sig_cirular_buffer_ptr_put_sampleP9BufferPtri {
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_BufferPtr_ptr_current.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtr_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtr_buffer_len.37 var=39) source () <61>;
|
||||
(__extDM_int32_.38 var=40) source () <62>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.45 var=44 stl=A off=0) inp () <69>;
|
||||
(buffer.46 var=44) deassign (buffer.45) <70>;
|
||||
(sample.48 var=45 stl=RA off=0) inp () <72>;
|
||||
(sample.49 var=45) deassign (sample.48) <73>;
|
||||
(__rd___sp.51 var=41) rd_res_reg (__R_SP.24 __sp.32) <75>;
|
||||
(__R_SP.55 var=26 __sp.56 var=34) wr_res_reg (__rt.140 __sp.32) <79>;
|
||||
(__fch___extDM_BufferPtr_ptr_current.60 var=52) load (__M_WDMA.9 __rt.162 __extDM_BufferPtr_ptr_current.34) <84>;
|
||||
(__M_WDMA.61 var=11 __extDM_BufferPtr_buffer_len.62 var=39 __extDM_int32_.63 var=40) store (sample.49 __fch___extDM_BufferPtr_ptr_current.60 __extDM_BufferPtr_buffer_len.37 __extDM_int32_.38) <85>;
|
||||
(__fch___extDM_BufferPtr_ptr_start.73 var=62) load (__M_WDMA.9 __rt.206 __extDM_BufferPtr_ptr_start.36) <95>;
|
||||
(__fch___extDM_BufferPtr_buffer_len.77 var=66) load (__M_WDMA.9 __rt.228 __extDM_BufferPtr_buffer_len.62) <99>;
|
||||
(__M_WDMA.85 var=11 __extDM_BufferPtr_ptr_current.86 var=36) store (__tmp.116 __rt.250 __extDM_BufferPtr_ptr_current.34) <107>;
|
||||
(__rd___sp.87 var=41) rd_res_reg (__R_SP.24 __sp.56) <108>;
|
||||
(__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.184 __sp.56) <112>;
|
||||
() void_ret_dmaddr_ (__la.43) <113>;
|
||||
() sink (__sp.92) <119>;
|
||||
() sink (__extDM_BufferPtr_ptr_current.86) <121>;
|
||||
() sink (__extDM_BufferPtr_buffer_len.62) <124>;
|
||||
() sink (__extDM_int32_.63) <125>;
|
||||
() sink (__ct_0.40) <126>;
|
||||
(__tmp.116 var=70) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch___extDM_BufferPtr_ptr_current.60 __ct_4.120 __fch___extDM_BufferPtr_ptr_start.73 __tmp.272) <159>;
|
||||
(__ct_4.120 var=89) const () <173>;
|
||||
(__ct_2.126 var=94) const () <181>;
|
||||
(__rt.140 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.51 __ct_0S0.263) <208>;
|
||||
(__rt.162 var=97) __Pvoid__pl___Pvoid_int18_ (buffer.46 __ct_8.264) <236>;
|
||||
(__rt.184 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_0s0.267) <264>;
|
||||
(__rt.206 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.162 __ct_4.120) <292>;
|
||||
(__rt.228 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.206 __ct_4.120) <320>;
|
||||
(__rt.250 var=97) __Pvoid__pl___Pvoid_int18_ (__rt.228 __ct_8.264) <348>;
|
||||
(__ct_0S0.263 var=122) const () <375>;
|
||||
(__ct_8.264 var=123) const () <377>;
|
||||
(__ct_0s0.267 var=126) const () <383>;
|
||||
(__ct_2.271 var=131) const () <390>;
|
||||
(__tmp.272 var=135) int72__shift_int72__int72__uint2_ (__fch___extDM_BufferPtr_buffer_len.77 __ct_2.126 __ct_2.271) <391>;
|
||||
} #5 off=0 nxt=-2
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
5 : (0,114:0,3);
|
||||
----------
|
||||
75 : (0,111:5,0);
|
||||
79 : (0,111:5,0);
|
||||
84 : (0,112:11,1);
|
||||
85 : (0,112:4,1);
|
||||
95 : (0,113:67,2);
|
||||
99 : (0,113:86,2);
|
||||
107 : (0,113:10,2);
|
||||
108 : (0,114:0,0);
|
||||
112 : (0,114:0,3);
|
||||
113 : (0,114:0,3);
|
||||
159 : (0,113:26,2);
|
||||
173 : (0,113:26,0);
|
||||
181 : (0,113:86,0);
|
||||
208 : (0,111:5,0);
|
||||
236 : (0,112:11,1);
|
||||
264 : (0,114:0,0);
|
||||
292 : (0,113:67,0);
|
||||
348 : (0,112:11,0);
|
||||
375 : (0,111:5,0);
|
||||
377 : (0,112:11,0);
|
||||
383 : (0,114:0,0);
|
||||
390 : (0,113:86,0);
|
||||
391 : (0,113:86,2);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-e7968f.#
Normal file
8
simulation/Release/chesswork/signal_path-e7968f.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
7f6e67d097bef17f42d1903822e2e079fd089c69
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
a930397de8fa3f7e26f75e262973f1cd15f811d0
|
||||
119
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-e7968f.o
Normal file
BIN
simulation/Release/chesswork/signal_path-e7968f.o
Normal file
Binary file not shown.
118
simulation/Release/chesswork/signal_path-e7968f.sfg
Normal file
118
simulation/Release/chesswork/signal_path-e7968f.sfg
Normal file
@@ -0,0 +1,118 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)
|
||||
F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_put_sample_DMB" 'void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[4] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi typ=uint20_ bnd=e stl=PM tref=void_____PDMBBufferPtrDMB___sint__
|
||||
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_BufferPtrDMB_ptr_current typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtrDMB_ptr_start typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_BufferPtrDMB_buffer_len typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : buffer typ=dmaddr_ bnd=p tref=__PDMBBufferPtrDMB__
|
||||
45 : sample typ=int32_ bnd=p tref=__sint__
|
||||
52 : __fch___extDM_BufferPtrDMB_ptr_current typ=dmaddr_ bnd=m
|
||||
62 : __fch___extDM_BufferPtrDMB_ptr_start typ=dmaddr_ bnd=m
|
||||
66 : __fch___extDM_BufferPtrDMB_buffer_len typ=int32_ bnd=m
|
||||
70 : __tmp typ=dmaddr_ bnd=m
|
||||
89 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
94 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
97 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
122 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
123 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
126 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
131 : __ct_2 typ=uint2_ val=2f bnd=m
|
||||
135 : __tmp typ=int18_ bnd=m
|
||||
]
|
||||
F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi {
|
||||
(__M_WDMB.10 var=12) st_def () <20>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_BufferPtrDMB_ptr_current.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtrDMB_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.37 var=39) source () <61>;
|
||||
(__extDM_int32_.38 var=40) source () <62>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.45 var=44 stl=A off=4) inp () <69>;
|
||||
(buffer.46 var=44) deassign (buffer.45) <70>;
|
||||
(sample.48 var=45 stl=RA off=0) inp () <72>;
|
||||
(sample.49 var=45) deassign (sample.48) <73>;
|
||||
(__rd___sp.51 var=41) rd_res_reg (__R_SP.24 __sp.32) <75>;
|
||||
(__R_SP.55 var=26 __sp.56 var=34) wr_res_reg (__rt.140 __sp.32) <79>;
|
||||
(__fch___extDM_BufferPtrDMB_ptr_current.60 var=52) load (__M_WDMB.10 __rt.162 __extDM_BufferPtrDMB_ptr_current.34) <84>;
|
||||
(__M_WDMB.61 var=12 __extDM_BufferPtrDMB_buffer_len.62 var=39 __extDM_int32_.63 var=40) store (sample.49 __fch___extDM_BufferPtrDMB_ptr_current.60 __extDM_BufferPtrDMB_buffer_len.37 __extDM_int32_.38) <85>;
|
||||
(__fch___extDM_BufferPtrDMB_ptr_start.73 var=62) load (__M_WDMB.10 __rt.206 __extDM_BufferPtrDMB_ptr_start.36) <95>;
|
||||
(__fch___extDM_BufferPtrDMB_buffer_len.77 var=66) load (__M_WDMB.10 __rt.228 __extDM_BufferPtrDMB_buffer_len.62) <99>;
|
||||
(__M_WDMB.85 var=12 __extDM_BufferPtrDMB_ptr_current.86 var=36) store (__tmp.116 __rt.250 __extDM_BufferPtrDMB_ptr_current.34) <107>;
|
||||
(__rd___sp.87 var=41) rd_res_reg (__R_SP.24 __sp.56) <108>;
|
||||
(__R_SP.91 var=26 __sp.92 var=34) wr_res_reg (__rt.184 __sp.56) <112>;
|
||||
() void_ret_dmaddr_ (__la.43) <113>;
|
||||
() sink (__sp.92) <119>;
|
||||
() sink (__extDM_BufferPtrDMB_ptr_current.86) <121>;
|
||||
() sink (__extDM_BufferPtrDMB_buffer_len.62) <124>;
|
||||
() sink (__extDM_int32_.63) <125>;
|
||||
() sink (__ct_0.40) <126>;
|
||||
(__tmp.116 var=70) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch___extDM_BufferPtrDMB_ptr_current.60 __ct_4.120 __fch___extDM_BufferPtrDMB_ptr_start.73 __tmp.272) <159>;
|
||||
(__ct_4.120 var=89) const () <173>;
|
||||
(__ct_2.126 var=94) const () <181>;
|
||||
(__rt.140 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.51 __ct_0S0.263) <208>;
|
||||
(__rt.162 var=97) __Pvoid__pl___Pvoid_int18_ (buffer.46 __ct_8.264) <236>;
|
||||
(__rt.184 var=97) __Pvoid__pl___Pvoid_int18_ (__rd___sp.87 __ct_0s0.267) <264>;
|
||||
(__rt.206 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.162 __ct_4.120) <292>;
|
||||
(__rt.228 var=97) __Pvoid__mi___Pvoid_int18_ (__rt.206 __ct_4.120) <320>;
|
||||
(__rt.250 var=97) __Pvoid__pl___Pvoid_int18_ (__rt.228 __ct_8.264) <348>;
|
||||
(__ct_0S0.263 var=122) const () <375>;
|
||||
(__ct_8.264 var=123) const () <377>;
|
||||
(__ct_0s0.267 var=126) const () <383>;
|
||||
(__ct_2.271 var=131) const () <390>;
|
||||
(__tmp.272 var=135) int72__shift_int72__int72__uint2_ (__fch___extDM_BufferPtrDMB_buffer_len.77 __ct_2.126 __ct_2.271) <391>;
|
||||
} #5 off=0 nxt=-2
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
5 : (0,119:0,3);
|
||||
----------
|
||||
75 : (0,116:5,0);
|
||||
79 : (0,116:5,0);
|
||||
84 : (0,117:11,1);
|
||||
85 : (0,117:4,1);
|
||||
95 : (0,118:67,2);
|
||||
99 : (0,118:86,2);
|
||||
107 : (0,118:10,2);
|
||||
108 : (0,119:0,0);
|
||||
112 : (0,119:0,3);
|
||||
113 : (0,119:0,3);
|
||||
159 : (0,118:26,2);
|
||||
173 : (0,118:26,0);
|
||||
181 : (0,118:86,0);
|
||||
208 : (0,116:5,0);
|
||||
236 : (0,117:11,1);
|
||||
264 : (0,119:0,0);
|
||||
292 : (0,118:67,0);
|
||||
348 : (0,117:11,0);
|
||||
375 : (0,116:5,0);
|
||||
377 : (0,117:11,0);
|
||||
383 : (0,119:0,0);
|
||||
390 : (0,118:86,0);
|
||||
391 : (0,118:86,2);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-f55921.#
Normal file
8
simulation/Release/chesswork/signal_path-f55921.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
bbef4f50b43757d842fa606817bbe8dce38a281e
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
ed333c6a3e8d1aafe83fb852bbcd140ff4272cff
|
||||
87
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-f55921.o
Normal file
BIN
simulation/Release/chesswork/signal_path-f55921.o
Normal file
Binary file not shown.
216
simulation/Release/chesswork/signal_path-f55921.sfg
Normal file
216
simulation/Release/chesswork/signal_path-f55921.sfg
Normal file
@@ -0,0 +1,216 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
|
||||
F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii : user_defined, called {
|
||||
fnm : "sig_init_buffer_DMB" 'int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[4] A[5] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii typ=uint20_ bnd=e stl=PM tref=__sint_____PDMBBufferPtrDMB___PDMB__sint___sint___sint__
|
||||
12 : __M_WDMB typ=int32_ bnd=d stl=WDMB
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_int32_ typ=int8_ bnd=b stl=DM
|
||||
37 : __extDM_BufferPtrDMB_buffer_len typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtrDMB_ptr_start typ=int8_ bnd=b stl=DM
|
||||
40 : __extDM_BufferPtrDMB_ptr_current typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : __rt typ=int32_ bnd=p tref=__sint__
|
||||
45 : buffer typ=dmaddr_ bnd=p tref=__PDMBBufferPtrDMB__
|
||||
46 : buffer_start_add typ=dmaddr_ bnd=p tref=__PDMB__sint__
|
||||
47 : length typ=int32_ bnd=p tref=__sint__
|
||||
48 : max_buffer_len typ=int32_ bnd=p tref=__sint__
|
||||
54 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
65 : __tmp typ=bool bnd=m
|
||||
72 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
76 : __tmp typ=bool bnd=m
|
||||
92 : __iv1_i typ=dmaddr_ bnd=m
|
||||
95 : __cv typ=uint16_ bnd=m
|
||||
103 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
127 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
128 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
129 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
133 : __tmp typ=uint3_ bnd=m
|
||||
138 : __tmp typ=uint3_ bnd=m
|
||||
148 : __either typ=bool bnd=m
|
||||
149 : __trgt typ=int10_ val=0j bnd=m
|
||||
150 : __trgt typ=int10_ val=0j bnd=m
|
||||
151 : __trgt typ=int10_ val=0j bnd=m
|
||||
152 : __trgt typ=int10_ val=0j bnd=m
|
||||
153 : __trgt typ=uint16_ val=0j bnd=m
|
||||
154 : __vcnt typ=uint16_ bnd=m
|
||||
]
|
||||
F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii {
|
||||
#239 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_int32_.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.35 var=37) source () <59>;
|
||||
(__extDM_BufferPtrDMB_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtrDMB_ptr_current.38 var=40) source () <62>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.46 var=45 stl=A off=4) inp () <70>;
|
||||
(buffer.47 var=45) deassign (buffer.46) <71>;
|
||||
(buffer_start_add.49 var=46 stl=A off=5) inp () <73>;
|
||||
(buffer_start_add.50 var=46) deassign (buffer_start_add.49) <74>;
|
||||
(length.52 var=47 stl=RA off=1) inp () <76>;
|
||||
(length.53 var=47) deassign (length.52) <77>;
|
||||
(max_buffer_len.55 var=48 stl=RB off=0) inp () <79>;
|
||||
(max_buffer_len.56 var=48) deassign (max_buffer_len.55) <80>;
|
||||
(__rd___sp.58 var=41) rd_res_reg (__R_SP.24 __sp.32) <82>;
|
||||
(__R_SP.62 var=26 __sp.63 var=34) wr_res_reg (__rt.274 __sp.32) <86>;
|
||||
(__ct_0.66 var=54) const () <90>;
|
||||
(__M_WDMB.69 var=12 __extDM_BufferPtrDMB_buffer_len.70 var=37) store (length.53 buffer.47 __extDM_BufferPtrDMB_buffer_len.35) <93>;
|
||||
(__M_WDMB.74 var=12 __extDM_BufferPtrDMB_ptr_start.75 var=38) store (buffer_start_add.50 __rt.340 __extDM_BufferPtrDMB_ptr_start.36) <97>;
|
||||
(__M_WDMB.79 var=12 __extDM_BufferPtrDMB_ptr_current.80 var=40) store (buffer_start_add.50 __rt.362 __extDM_BufferPtrDMB_ptr_current.38) <101>;
|
||||
(__rt.274 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.58 __ct_0S0.375) <320>;
|
||||
(__rt.340 var=103) __Pvoid__pl___Pvoid_int18_ (buffer.47 __ct_4.377) <404>;
|
||||
(__rt.362 var=103) __Pvoid__pl___Pvoid_int18_ (__rt.340 __ct_4.377) <432>;
|
||||
(__ct_0S0.375 var=127) const () <457>;
|
||||
(__ct_4.377 var=129) const () <461>;
|
||||
(__tmp.380 var=133) uint3__cmp_int72__int72_ (length.53 __ct_0.66) <466>;
|
||||
(__tmp.393 var=65) bool_nplus_uint3_ (__tmp.380) <500>;
|
||||
(__trgt.396 var=149) const () <511>;
|
||||
() void_jump_bool_int10_ (__tmp.393 __trgt.396) <512>;
|
||||
(__either.397 var=148) undefined () <513>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.397) <126>;
|
||||
() chess_frequent_else () <127>;
|
||||
() chess_rear_then () <514>;
|
||||
} #5
|
||||
{
|
||||
(__trgt.398 var=150) const () <515>;
|
||||
() void_jump_int10_ (__trgt.398) <516>;
|
||||
} #11 off=4
|
||||
{
|
||||
#30 off=1
|
||||
(__cv.254 var=95) uint16__uint16____sint (length.53) <288>;
|
||||
(__trgt.402 var=153) const () <522>;
|
||||
() void_doloop_uint16__uint16_ (__cv.254 __trgt.402) <523>;
|
||||
(__vcnt.403 var=154) undefined () <524>;
|
||||
for {
|
||||
{
|
||||
(__extDM_int32_.112 var=36) entry (__extDM_int32_.152 __extDM_int32_.34) <135>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.113 var=37) entry (__extDM_BufferPtrDMB_buffer_len.154 __extDM_BufferPtrDMB_buffer_len.70) <136>;
|
||||
(__iv1_i.245 var=92) entry (__iv1_i.246 buffer_start_add.50) <279>;
|
||||
} #8
|
||||
{
|
||||
(__M_WDMB.131 var=12 __extDM_BufferPtrDMB_buffer_len.132 var=37 __extDM_int32_.133 var=36) store (__ct_0.66 __iv1_i.245 __extDM_BufferPtrDMB_buffer_len.113 __extDM_int32_.112) <154>;
|
||||
(__rt.318 var=103) __Pvoid__pl___Pvoid_int18_ (__iv1_i.245 __ct_4.377) <376>;
|
||||
} #173 off=2
|
||||
{
|
||||
() for_count (__vcnt.403) <159>;
|
||||
(__extDM_int32_.152 var=36 __extDM_int32_.153 var=36) exit (__extDM_int32_.133) <167>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.154 var=37 __extDM_BufferPtrDMB_buffer_len.155 var=37) exit (__extDM_BufferPtrDMB_buffer_len.132) <168>;
|
||||
(__iv1_i.246 var=92 __iv1_i.247 var=92) exit (__rt.318) <280>;
|
||||
} #10
|
||||
} #7 rng=[1,65535]
|
||||
} #6
|
||||
{
|
||||
(__extDM_int32_.178 var=36) merge (__extDM_int32_.34 __extDM_int32_.153) <180>;
|
||||
(__extDM_BufferPtrDMB_buffer_len.179 var=37) merge (__extDM_BufferPtrDMB_buffer_len.70 __extDM_BufferPtrDMB_buffer_len.155) <181>;
|
||||
} #12
|
||||
} #4
|
||||
#242 off=5
|
||||
(__tmp.385 var=138) uint3__cmp_int72__int72_ (length.53 max_buffer_len.56) <474>;
|
||||
(__tmp.386 var=76) bool_neg_uint3_ (__tmp.385) <475>;
|
||||
(__trgt.399 var=151) const () <517>;
|
||||
() void_jump_bool_int10_ (__tmp.386 __trgt.399) <518>;
|
||||
(__either.400 var=148) undefined () <519>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.400) <205>;
|
||||
} #15
|
||||
{
|
||||
} #16 off=7
|
||||
{
|
||||
(__ct_1.134 var=72) const () <155>;
|
||||
(__trgt.401 var=152) const () <520>;
|
||||
() void_jump_int10_ (__trgt.401) <521>;
|
||||
} #17 off=6
|
||||
{
|
||||
(__rt.207 var=44) merge (__ct_0.66 __ct_1.134) <210>;
|
||||
} #18
|
||||
} #14
|
||||
#20 off=8 nxt=-2
|
||||
(__rd___sp.208 var=41) rd_res_reg (__R_SP.24 __sp.63) <211>;
|
||||
(__R_SP.212 var=26 __sp.213 var=34) wr_res_reg (__rt.296 __sp.63) <215>;
|
||||
() void_ret_dmaddr_ (__la.43) <216>;
|
||||
(__rt.214 var=44 stl=RA off=0) assign (__rt.207) <217>;
|
||||
() out (__rt.214) <218>;
|
||||
() sink (__sp.213) <224>;
|
||||
() sink (__extDM_int32_.178) <226>;
|
||||
() sink (__extDM_BufferPtrDMB_buffer_len.179) <227>;
|
||||
() sink (__extDM_BufferPtrDMB_ptr_start.75) <228>;
|
||||
() sink (__extDM_BufferPtrDMB_ptr_current.80) <230>;
|
||||
() sink (__ct_0.40) <231>;
|
||||
(__rt.296 var=103) __Pvoid__pl___Pvoid_int18_ (__rd___sp.208 __ct_0s0.376) <348>;
|
||||
(__ct_0s0.376 var=128) const () <459>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,87:0,0);
|
||||
4 : (0,92:4,5);
|
||||
6 : (0,92:4,6);
|
||||
7 : (0,92:4,6);
|
||||
11 : (0,92:4,13);
|
||||
14 : (0,95:4,16);
|
||||
16 : (0,99:8,17);
|
||||
17 : (0,96:8,21);
|
||||
20 : (0,95:4,26);
|
||||
173 : (0,92:37,6);
|
||||
239 : (0,92:4,5);
|
||||
242 : (0,95:14,16);
|
||||
----------
|
||||
82 : (0,87:4,0);
|
||||
86 : (0,87:4,0);
|
||||
90 : (0,88:10,0);
|
||||
93 : (0,88:10,1);
|
||||
97 : (0,89:10,2);
|
||||
101 : (0,90:10,3);
|
||||
126 : (0,92:4,5);
|
||||
135 : (0,92:4,6);
|
||||
136 : (0,92:4,6);
|
||||
154 : (0,93:24,6);
|
||||
155 : (0,92:33,0);
|
||||
159 : (0,92:4,11);
|
||||
167 : (0,92:4,11);
|
||||
168 : (0,92:4,11);
|
||||
180 : (0,92:4,15);
|
||||
181 : (0,92:4,15);
|
||||
205 : (0,95:4,16);
|
||||
210 : (0,95:4,25);
|
||||
211 : (0,95:4,0);
|
||||
215 : (0,95:4,26);
|
||||
216 : (0,95:4,26);
|
||||
217 : (0,95:4,0);
|
||||
320 : (0,87:4,0);
|
||||
348 : (0,95:4,0);
|
||||
404 : (0,89:10,0);
|
||||
432 : (0,90:10,0);
|
||||
457 : (0,87:4,0);
|
||||
459 : (0,95:4,0);
|
||||
466 : (0,92:4,5);
|
||||
474 : (0,95:14,16);
|
||||
475 : (0,95:14,16);
|
||||
500 : (0,92:4,5);
|
||||
512 : (0,92:4,5);
|
||||
518 : (0,95:4,16);
|
||||
523 : (0,92:4,11);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-f8ba01.#
Normal file
8
simulation/Release/chesswork/signal_path-f8ba01.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
f0a89ba4f0ffe4d6c35e3ba6a3fe720aafc74986
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
929c6065768a0037415bd30b60dc40028d4df14c
|
||||
133
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-f8ba01.o
Normal file
BIN
simulation/Release/chesswork/signal_path-f8ba01.o
Normal file
Binary file not shown.
736
simulation/Release/chesswork/signal_path-f8ba01.sfg
Normal file
736
simulation/Release/chesswork/signal_path-f8ba01.sfg
Normal file
@@ -0,0 +1,736 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
|
||||
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
|
||||
fnm : "sig_init_preemph_coef" 'void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
!! extern double ff_pow(double, double)
|
||||
Fff_pow : user_defined, called {
|
||||
fnm : "ff_pow" 'double ff_pow(double, double)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
!! int float64_eq(float64, float64)
|
||||
F_Z10float64_eqyy : user_defined, called {
|
||||
fnm : "float64_eq" 'int float64_eq(float64, float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] AX[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 int32_to_float64(int)
|
||||
F_Z16int32_to_float64i : user_defined, called {
|
||||
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
|
||||
arg : ( dmaddr_:i int64_:r int32_:i );
|
||||
loc : ( LR[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_sub(float64, float64)
|
||||
F_Z11float64_subyy : user_defined, called {
|
||||
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! int float64_to_int32_round_to_zero(float64)
|
||||
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
|
||||
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
!! float64 float64_mul(float64, float64)
|
||||
F_Z11float64_mulyy : user_defined, called {
|
||||
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=uint20_ bnd=e stl=PM tref=void_____PSingleSignalPath___fdouble___fdouble___fdouble___fdouble___fdouble___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_SingleSignalPath_preemph_activated typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_SingleSignalPath__preemph_scale_nbits typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_SingleSignalPath_b_preemph typ=int8_ bnd=b stl=DM
|
||||
40 : __rd___sp typ=dmaddr_ bnd=m
|
||||
41 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
42 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
43 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
|
||||
44 : b0 typ=int64_ bnd=p tref=__fdouble__
|
||||
45 : b1 typ=int64_ bnd=p tref=__fdouble__
|
||||
46 : b2 typ=int64_ bnd=p tref=__fdouble__
|
||||
47 : a1 typ=int64_ bnd=p tref=__fdouble__
|
||||
48 : a2 typ=int64_ bnd=p tref=__fdouble__
|
||||
49 : scale_bits typ=int32_ bnd=p tref=__sint__
|
||||
53 : __tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
|
||||
54 : __tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=int64_ bnd=m lscp=247 tref=__fdouble__
|
||||
56 : scale typ=int32_ bnd=m lscp=247 tref=__sint__
|
||||
57 : __ct_4607182418800017408 typ=int64_ val=4607182418800017408f bnd=m
|
||||
60 : __ct_0 typ=uint40_ val=0f bnd=m
|
||||
65 : __tmp typ=bool bnd=m
|
||||
71 : __tmp typ=bool bnd=m
|
||||
77 : __tmp typ=bool bnd=m
|
||||
83 : __tmp typ=bool bnd=m
|
||||
84 : __ct_0 typ=int32_ val=0f bnd=m
|
||||
89 : __ct_1 typ=int32_ val=1f bnd=m
|
||||
98 : __ct_4611686018427387904 typ=int64_ val=4611686018427387904f bnd=m
|
||||
103 : __tmp typ=int64_ bnd=m
|
||||
105 : __tmp typ=int64_ bnd=m
|
||||
106 : __tmp typ=int64_ bnd=m
|
||||
107 : __tmp typ=int32_ bnd=m
|
||||
115 : __tmp typ=int64_ bnd=m
|
||||
116 : __tmp typ=int32_ bnd=m
|
||||
124 : __tmp typ=int64_ bnd=m
|
||||
125 : __tmp typ=int32_ bnd=m
|
||||
133 : __tmp typ=int64_ bnd=m
|
||||
134 : __tmp typ=int32_ bnd=m
|
||||
142 : __tmp typ=int64_ bnd=m
|
||||
143 : __tmp typ=int32_ bnd=m
|
||||
164 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
185 : __tmp typ=int32_ bnd=m
|
||||
202 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
203 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
206 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
207 : __ct_24 typ=int18_ val=24f bnd=m
|
||||
209 : __ct_20 typ=int18_ val=20f bnd=m
|
||||
210 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
214 : __tmp typ=bool bnd=m
|
||||
225 : __a0 typ=int64_ bnd=m tref=__atp0___48
|
||||
227 : ff_pow typ=dmaddr_ val=0r bnd=m
|
||||
228 : __link typ=dmaddr_ bnd=m
|
||||
253 : __a1 typ=int64_ bnd=m tref=__atp1___12
|
||||
254 : _Z10float64_eqyy typ=dmaddr_ val=0r bnd=m
|
||||
255 : __link typ=dmaddr_ bnd=m
|
||||
265 : __tmp typ=uint3_ bnd=m
|
||||
274 : _Z16int32_to_float64i typ=dmaddr_ val=0r bnd=m
|
||||
275 : __link typ=dmaddr_ bnd=m
|
||||
277 : __tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi typ=int64_ bnd=m
|
||||
279 : __a1 typ=int64_ bnd=m tref=__atp1___9
|
||||
280 : _Z11float64_subyy typ=dmaddr_ val=0r bnd=m
|
||||
281 : __link typ=dmaddr_ bnd=m
|
||||
283 : __tmp typ=int64_ bnd=m
|
||||
285 : _Z30float64_to_int32_round_to_zeroy typ=dmaddr_ val=0r bnd=m
|
||||
286 : __link typ=dmaddr_ bnd=m
|
||||
289 : __tmp typ=int64_ bnd=m
|
||||
292 : _Z11float64_mulyy typ=dmaddr_ val=0r bnd=m
|
||||
293 : __link typ=dmaddr_ bnd=m
|
||||
295 : __tmp typ=int64_ bnd=m
|
||||
297 : __tmp typ=int64_ bnd=m
|
||||
299 : __tmp typ=int64_ bnd=m
|
||||
301 : __tmp typ=int64_ bnd=m
|
||||
303 : __tmp typ=int64_ bnd=m
|
||||
311 : __true typ=bool val=1f bnd=m
|
||||
312 : __false typ=bool val=0f bnd=m
|
||||
313 : __either typ=bool bnd=m
|
||||
314 : __trgt typ=int10_ val=0j bnd=m
|
||||
315 : __trgt typ=int10_ val=0j bnd=m
|
||||
316 : __trgt typ=int10_ val=0j bnd=m
|
||||
317 : __trgt typ=int10_ val=0j bnd=m
|
||||
318 : __trgt typ=int10_ val=0j bnd=m
|
||||
319 : __trgt typ=int10_ val=0j bnd=m
|
||||
]
|
||||
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi {
|
||||
#482 off=0
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_SingleSignalPath_preemph_activated.34 var=36) source () <58>;
|
||||
(__extDM_SingleSignalPath__preemph_scale_nbits.36 var=38) source () <60>;
|
||||
(__extDM_SingleSignalPath_b_preemph.37 var=39) source () <61>;
|
||||
(__ct_0.39 var=41) const () <63>;
|
||||
(__la.41 var=42 stl=LR off=0) inp () <65>;
|
||||
(__la.42 var=42) deassign (__la.41) <66>;
|
||||
(signal.44 var=43 stl=A off=0) inp () <68>;
|
||||
(signal.45 var=43) deassign (signal.44) <69>;
|
||||
(b0.47 var=44 stl=AX off=0) inp () <71>;
|
||||
(b0.48 var=44) deassign (b0.47) <72>;
|
||||
(b1.50 var=45 stl=AX off=1) inp () <74>;
|
||||
(b1.51 var=45) deassign (b1.50) <75>;
|
||||
(b2.53 var=46 stl=BX off=0) inp () <77>;
|
||||
(b2.54 var=46) deassign (b2.53) <78>;
|
||||
(a1.56 var=47 stl=BX off=1) inp () <80>;
|
||||
(a1.57 var=47) deassign (a1.56) <81>;
|
||||
(a2.59 var=48 stl=__spill_LDMA off=0) inp () <83>;
|
||||
(a2.60 var=48) deassign (a2.59) <84>;
|
||||
(scale_bits.62 var=49 stl=RA off=0) inp () <86>;
|
||||
(scale_bits.63 var=49) deassign (scale_bits.62) <87>;
|
||||
(__rd___sp.65 var=40) rd_res_reg (__R_SP.24 __sp.32) <89>;
|
||||
(__R_SP.69 var=26 __sp.70 var=34) wr_res_reg (__rt.365 __sp.32) <93>;
|
||||
(__ct_4607182418800017408.75 var=57) const () <99>;
|
||||
(__rt.365 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.65 __ct_0S0.584) <447>;
|
||||
(__ct_0S0.584 var=202) const () <747>;
|
||||
(_Z10float64_eqyy.680 var=254) const () <927>;
|
||||
(__link.681 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <928>;
|
||||
call {
|
||||
(b0.682 var=44 stl=AX off=0) assign (b0.48) <929>;
|
||||
(__a1.683 var=253 stl=AX off=1) assign (__ct_4607182418800017408.75) <930>;
|
||||
(__link.684 var=255 stl=LR off=0) assign (__link.681) <931>;
|
||||
(__tmp.685 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.684 b0.682 __a1.683) <932>;
|
||||
(__tmp.686 var=185) deassign (__tmp.685) <933>;
|
||||
} #483 off=1
|
||||
#479 off=2
|
||||
(__ct_0.101 var=60) const () <126>;
|
||||
(__ct_0.217 var=84) const () <246>;
|
||||
(__rt.417 var=164) __Pvoid__pl___Pvoid_int18_ (signal.45 __ct_8.585) <520>;
|
||||
(__ct_8.585 var=203) const () <749>;
|
||||
(__tmp.730 var=265) uint3__cmp_int72__int72_ (__tmp.686 __ct_0.217) <992>;
|
||||
(__tmp.888 var=214) bool_equal_uint3_ (__tmp.730) <1262>;
|
||||
(__trgt.897 var=314) const () <1291>;
|
||||
() void_jump_bool_int10_ (__tmp.888 __trgt.897) <1292>;
|
||||
(__either.898 var=313) undefined () <1293>;
|
||||
if {
|
||||
{
|
||||
() if_expr (__either.898) <125>;
|
||||
} #5
|
||||
{
|
||||
(__true.899 var=311) const () <1294>;
|
||||
} #7
|
||||
{
|
||||
#491 off=3
|
||||
(__link.691 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <941>;
|
||||
call {
|
||||
(b1.692 var=45 stl=AX off=0) assign (b1.51) <942>;
|
||||
(__a1.693 var=253 stl=AX off=1) assign (__ct_0.101) <943>;
|
||||
(__link.694 var=255 stl=LR off=0) assign (__link.691) <944>;
|
||||
(__tmp.695 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.694 b1.692 __a1.693) <945>;
|
||||
(__tmp.696 var=185) deassign (__tmp.695) <946>;
|
||||
} #492 off=4
|
||||
#488 off=5
|
||||
(__tmp.735 var=265) uint3__cmp_int72__int72_ (__tmp.696 __ct_0.217) <1000>;
|
||||
(__tmp.889 var=214) bool_equal_uint3_ (__tmp.735) <1263>;
|
||||
(__trgt.900 var=315) const () <1295>;
|
||||
() void_jump_bool_int10_ (__tmp.889 __trgt.900) <1296>;
|
||||
(__either.901 var=313) undefined () <1297>;
|
||||
} #383
|
||||
{
|
||||
(__tmp.890 var=65) merge (__true.899 __either.901) <1264>;
|
||||
} #8
|
||||
} #4
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.890) <155>;
|
||||
} #11
|
||||
{
|
||||
(__true.902 var=311) const () <1298>;
|
||||
} #13
|
||||
{
|
||||
#500 off=6
|
||||
(__link.701 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <954>;
|
||||
call {
|
||||
(b2.702 var=46 stl=AX off=0) assign (b2.54) <955>;
|
||||
(__a1.703 var=253 stl=AX off=1) assign (__ct_0.101) <956>;
|
||||
(__link.704 var=255 stl=LR off=0) assign (__link.701) <957>;
|
||||
(__tmp.705 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.704 b2.702 __a1.703) <958>;
|
||||
(__tmp.706 var=185) deassign (__tmp.705) <959>;
|
||||
} #501 off=7
|
||||
#497 off=8
|
||||
(__tmp.740 var=265) uint3__cmp_int72__int72_ (__tmp.706 __ct_0.217) <1008>;
|
||||
(__tmp.891 var=214) bool_equal_uint3_ (__tmp.740) <1265>;
|
||||
(__trgt.903 var=316) const () <1299>;
|
||||
() void_jump_bool_int10_ (__tmp.891 __trgt.903) <1300>;
|
||||
(__either.904 var=313) undefined () <1301>;
|
||||
} #388
|
||||
{
|
||||
(__tmp.892 var=71) merge (__true.902 __either.904) <1266>;
|
||||
} #14
|
||||
} #10
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.892) <185>;
|
||||
} #17
|
||||
{
|
||||
(__true.905 var=311) const () <1302>;
|
||||
} #19
|
||||
{
|
||||
#509 off=9
|
||||
(__link.711 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <967>;
|
||||
call {
|
||||
(a1.712 var=47 stl=AX off=0) assign (a1.57) <968>;
|
||||
(__a1.713 var=253 stl=AX off=1) assign (__ct_0.101) <969>;
|
||||
(__link.714 var=255 stl=LR off=0) assign (__link.711) <970>;
|
||||
(__tmp.715 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.714 a1.712 __a1.713) <971>;
|
||||
(__tmp.716 var=185) deassign (__tmp.715) <972>;
|
||||
} #510 off=10
|
||||
#506 off=11
|
||||
(__tmp.745 var=265) uint3__cmp_int72__int72_ (__tmp.716 __ct_0.217) <1016>;
|
||||
(__tmp.893 var=214) bool_equal_uint3_ (__tmp.745) <1267>;
|
||||
(__trgt.906 var=317) const () <1303>;
|
||||
() void_jump_bool_int10_ (__tmp.893 __trgt.906) <1304>;
|
||||
(__either.907 var=313) undefined () <1305>;
|
||||
} #393
|
||||
{
|
||||
(__tmp.894 var=77) merge (__true.905 __either.907) <1268>;
|
||||
} #20
|
||||
} #16
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.894) <215>;
|
||||
} #23
|
||||
{
|
||||
(__false.908 var=312) const () <1306>;
|
||||
} #25
|
||||
{
|
||||
#518 off=12
|
||||
(__link.721 var=255) dmaddr__call_dmaddr_ (_Z10float64_eqyy.680) <980>;
|
||||
call {
|
||||
(a2.722 var=48 stl=AX off=0) assign (a2.60) <981>;
|
||||
(__a1.723 var=253 stl=AX off=1) assign (__ct_0.101) <982>;
|
||||
(__link.724 var=255 stl=LR off=0) assign (__link.721) <983>;
|
||||
(__tmp.725 var=185 stl=RA off=0) F_Z10float64_eqyy (__link.724 a2.722 __a1.723) <984>;
|
||||
(__tmp.726 var=185) deassign (__tmp.725) <985>;
|
||||
} #519 off=13
|
||||
#515 off=14
|
||||
(__tmp.750 var=265) uint3__cmp_int72__int72_ (__tmp.726 __ct_0.217) <1024>;
|
||||
(__tmp.759 var=214) bool_nequal_uint3_ (__tmp.750) <1051>;
|
||||
(__trgt.909 var=318) const () <1307>;
|
||||
() void_jump_bool_int10_ (__tmp.759 __trgt.909) <1308>;
|
||||
(__either.910 var=313) undefined () <1309>;
|
||||
} #398
|
||||
{
|
||||
(__tmp.193 var=83) merge (__false.908 __either.910) <221>;
|
||||
} #26
|
||||
} #22
|
||||
if {
|
||||
{
|
||||
() if_expr (__tmp.193) <245>;
|
||||
} #29
|
||||
{
|
||||
(__M_WDMA.222 var=11 __extDM_SingleSignalPath_preemph_activated.223 var=36) store (__ct_0.217 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <251>;
|
||||
} #30 off=46
|
||||
{
|
||||
#545 off=15
|
||||
(__ct_1.224 var=89) const () <252>;
|
||||
(__M_WDMA.229 var=11 __extDM_SingleSignalPath_preemph_activated.230 var=36) store (__ct_1.224 __rt.417 __extDM_SingleSignalPath_preemph_activated.34) <257>;
|
||||
(__M_WDMA.234 var=11 __extDM_SingleSignalPath__preemph_scale_nbits.235 var=38) store (scale_bits.63 __rt.461 __extDM_SingleSignalPath__preemph_scale_nbits.36) <261>;
|
||||
(__rt.461 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.417 __ct_24.589) <576>;
|
||||
(__rt.483 var=164) __Pvoid__mi___Pvoid_int18_ (__rt.461 __ct_20.591) <604>;
|
||||
(__ct_24.589 var=207) const () <757>;
|
||||
(__ct_20.591 var=209) const () <761>;
|
||||
(_Z16int32_to_float64i.761 var=274) const () <1054>;
|
||||
(__link.762 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1055>;
|
||||
call {
|
||||
(scale_bits.763 var=49 stl=RA off=0) assign (scale_bits.63) <1056>;
|
||||
(__link.764 var=275 stl=LR off=0) assign (__link.762) <1057>;
|
||||
(__tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.765 var=277 stl=AX off=0) F_Z16int32_to_float64i (__link.764 scale_bits.763) <1058>;
|
||||
(__tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.766 var=54) deassign (__tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.765) <1059>;
|
||||
} #546 off=16
|
||||
#542 off=17
|
||||
(__ct_4611686018427387904.241 var=98) const () <267>;
|
||||
(ff_pow.625 var=227) const () <830>;
|
||||
(__link.626 var=228) dmaddr__call_dmaddr_ (ff_pow.625) <831>;
|
||||
call {
|
||||
(__a0.627 var=225 stl=AX off=1) assign (__ct_4611686018427387904.241) <832>;
|
||||
(__tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.628 var=54 stl=BX off=0) assign (__tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.766) <833>;
|
||||
(__link.629 var=228 stl=LR off=0) assign (__link.626) <834>;
|
||||
(__tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.630 var=53 stl=AX off=0) Fff_pow (__link.629 __a0.627 __tmpb2_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.628) <835>;
|
||||
(__tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.631 var=53) deassign (__tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.630) <836>;
|
||||
} #434 off=18
|
||||
#573 off=19
|
||||
(_Z11float64_subyy.770 var=280) const () <1066>;
|
||||
(__link.771 var=281) dmaddr__call_dmaddr_ (_Z11float64_subyy.770) <1067>;
|
||||
call {
|
||||
(__tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.772 var=53 stl=AX off=1) assign (__tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.631) <1068>;
|
||||
(__a1.773 var=279 stl=BX off=0) assign (__ct_4607182418800017408.75) <1069>;
|
||||
(__link.774 var=281 stl=LR off=0) assign (__link.771) <1070>;
|
||||
(__tmp.775 var=283 stl=AX off=0) F_Z11float64_subyy (__link.774 __tmpb0_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi.772 __a1.773) <1071>;
|
||||
(__tmp.776 var=103) deassign (__tmp.775) <1072>;
|
||||
} #574 off=20
|
||||
#579 off=21
|
||||
(_Z30float64_to_int32_round_to_zeroy.779 var=285) const () <1078>;
|
||||
(__link.780 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1079>;
|
||||
call {
|
||||
(__tmp.781 var=103 stl=AX off=0) assign (__tmp.776) <1080>;
|
||||
(__link.782 var=286 stl=LR off=0) assign (__link.780) <1081>;
|
||||
(scale.783 var=56 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.782 __tmp.781) <1082>;
|
||||
(scale.784 var=56) deassign (scale.783) <1083>;
|
||||
} #580 off=22
|
||||
#585 off=23
|
||||
(__link.788 var=275) dmaddr__call_dmaddr_ (_Z16int32_to_float64i.761) <1090>;
|
||||
call {
|
||||
(scale.789 var=56 stl=RA off=0) assign (scale.784) <1091>;
|
||||
(__link.790 var=275 stl=LR off=0) assign (__link.788) <1092>;
|
||||
(__tmp.791 var=289 stl=AX off=0) F_Z16int32_to_float64i (__link.790 scale.789) <1093>;
|
||||
(__tmp.792 var=105) deassign (__tmp.791) <1094>;
|
||||
} #586 off=24
|
||||
#591 off=25
|
||||
(_Z11float64_mulyy.796 var=292) const () <1101>;
|
||||
(__link.797 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1102>;
|
||||
call {
|
||||
(b0.798 var=44 stl=AX off=1) assign (b0.48) <1103>;
|
||||
(__tmp.799 var=105 stl=BX off=0) assign (__tmp.792) <1104>;
|
||||
(__link.800 var=293 stl=LR off=0) assign (__link.797) <1105>;
|
||||
(__tmp.801 var=295 stl=AX off=0) F_Z11float64_mulyy (__link.800 b0.798 __tmp.799) <1106>;
|
||||
(__tmp.802 var=106) deassign (__tmp.801) <1107>;
|
||||
} #592 off=26
|
||||
#597 off=27
|
||||
(__link.806 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1114>;
|
||||
call {
|
||||
(__tmp.807 var=106 stl=AX off=0) assign (__tmp.802) <1115>;
|
||||
(__link.808 var=286 stl=LR off=0) assign (__link.806) <1116>;
|
||||
(__tmp.809 var=107 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.808 __tmp.807) <1117>;
|
||||
(__tmp.810 var=107) deassign (__tmp.809) <1118>;
|
||||
} #598 off=28
|
||||
#603 off=29
|
||||
(__M_WDMA.257 var=11 __extDM_SingleSignalPath_b_preemph.258 var=39) store (__tmp.810 __rt.483 __extDM_SingleSignalPath_b_preemph.37) <283>;
|
||||
(__rt.505 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.483 __ct_4.592) <632>;
|
||||
(__ct_4.592 var=210) const () <763>;
|
||||
(__link.815 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1126>;
|
||||
call {
|
||||
(b1.816 var=45 stl=AX off=1) assign (b1.51) <1127>;
|
||||
(__tmp.817 var=105 stl=BX off=0) assign (__tmp.792) <1128>;
|
||||
(__link.818 var=293 stl=LR off=0) assign (__link.815) <1129>;
|
||||
(__tmp.819 var=297 stl=AX off=0) F_Z11float64_mulyy (__link.818 b1.816 __tmp.817) <1130>;
|
||||
(__tmp.820 var=115) deassign (__tmp.819) <1131>;
|
||||
} #604 off=30
|
||||
#609 off=31
|
||||
(__link.824 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1138>;
|
||||
call {
|
||||
(__tmp.825 var=115 stl=AX off=0) assign (__tmp.820) <1139>;
|
||||
(__link.826 var=286 stl=LR off=0) assign (__link.824) <1140>;
|
||||
(__tmp.827 var=116 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.826 __tmp.825) <1141>;
|
||||
(__tmp.828 var=116) deassign (__tmp.827) <1142>;
|
||||
} #610 off=32
|
||||
#615 off=33
|
||||
(__M_WDMA.268 var=11 __extDM_SingleSignalPath_b_preemph.269 var=39) store (__tmp.828 __rt.505 __extDM_SingleSignalPath_b_preemph.258) <293>;
|
||||
(__rt.527 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.505 __ct_4.592) <660>;
|
||||
(__link.833 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1150>;
|
||||
call {
|
||||
(b2.834 var=46 stl=AX off=1) assign (b2.54) <1151>;
|
||||
(__tmp.835 var=105 stl=BX off=0) assign (__tmp.792) <1152>;
|
||||
(__link.836 var=293 stl=LR off=0) assign (__link.833) <1153>;
|
||||
(__tmp.837 var=299 stl=AX off=0) F_Z11float64_mulyy (__link.836 b2.834 __tmp.835) <1154>;
|
||||
(__tmp.838 var=124) deassign (__tmp.837) <1155>;
|
||||
} #616 off=34
|
||||
#621 off=35
|
||||
(__link.842 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1162>;
|
||||
call {
|
||||
(__tmp.843 var=124 stl=AX off=0) assign (__tmp.838) <1163>;
|
||||
(__link.844 var=286 stl=LR off=0) assign (__link.842) <1164>;
|
||||
(__tmp.845 var=125 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.844 __tmp.843) <1165>;
|
||||
(__tmp.846 var=125) deassign (__tmp.845) <1166>;
|
||||
} #622 off=36
|
||||
#627 off=37
|
||||
(__M_WDMA.279 var=11 __extDM_SingleSignalPath_b_preemph.280 var=39) store (__tmp.846 __rt.527 __extDM_SingleSignalPath_b_preemph.269) <303>;
|
||||
(__rt.549 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.527 __ct_4.592) <688>;
|
||||
(__link.851 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1174>;
|
||||
call {
|
||||
(a1.852 var=47 stl=AX off=1) assign (a1.57) <1175>;
|
||||
(__tmp.853 var=105 stl=BX off=0) assign (__tmp.792) <1176>;
|
||||
(__link.854 var=293 stl=LR off=0) assign (__link.851) <1177>;
|
||||
(__tmp.855 var=301 stl=AX off=0) F_Z11float64_mulyy (__link.854 a1.852 __tmp.853) <1178>;
|
||||
(__tmp.856 var=133) deassign (__tmp.855) <1179>;
|
||||
} #628 off=38
|
||||
#633 off=39
|
||||
(__link.860 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1186>;
|
||||
call {
|
||||
(__tmp.861 var=133 stl=AX off=0) assign (__tmp.856) <1187>;
|
||||
(__link.862 var=286 stl=LR off=0) assign (__link.860) <1188>;
|
||||
(__tmp.863 var=134 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.862 __tmp.861) <1189>;
|
||||
(__tmp.864 var=134) deassign (__tmp.863) <1190>;
|
||||
} #634 off=40
|
||||
#639 off=41
|
||||
(__M_WDMA.290 var=11 __extDM_SingleSignalPath_b_preemph.291 var=39) store (__tmp.864 __rt.549 __extDM_SingleSignalPath_b_preemph.280) <313>;
|
||||
(__rt.571 var=164) __Pvoid__pl___Pvoid_int18_ (__rt.549 __ct_4.592) <716>;
|
||||
(__link.869 var=293) dmaddr__call_dmaddr_ (_Z11float64_mulyy.796) <1198>;
|
||||
call {
|
||||
(a2.870 var=48 stl=AX off=1) assign (a2.60) <1199>;
|
||||
(__tmp.871 var=105 stl=BX off=0) assign (__tmp.792) <1200>;
|
||||
(__link.872 var=293 stl=LR off=0) assign (__link.869) <1201>;
|
||||
(__tmp.873 var=303 stl=AX off=0) F_Z11float64_mulyy (__link.872 a2.870 __tmp.871) <1202>;
|
||||
(__tmp.874 var=142) deassign (__tmp.873) <1203>;
|
||||
} #640 off=42
|
||||
#645 off=43
|
||||
(__link.878 var=286) dmaddr__call_dmaddr_ (_Z30float64_to_int32_round_to_zeroy.779) <1210>;
|
||||
call {
|
||||
(__tmp.879 var=142 stl=AX off=0) assign (__tmp.874) <1211>;
|
||||
(__link.880 var=286 stl=LR off=0) assign (__link.878) <1212>;
|
||||
(__tmp.881 var=143 stl=RA off=0) F_Z30float64_to_int32_round_to_zeroy (__link.880 __tmp.879) <1213>;
|
||||
(__tmp.882 var=143) deassign (__tmp.881) <1214>;
|
||||
} #646 off=44
|
||||
#570 off=45
|
||||
(__M_WDMA.301 var=11 __extDM_SingleSignalPath_b_preemph.302 var=39) store (__tmp.882 __rt.571 __extDM_SingleSignalPath_b_preemph.291) <323>;
|
||||
(__trgt.911 var=319) const () <1310>;
|
||||
() void_jump_int10_ (__trgt.911) <1311>;
|
||||
} #247
|
||||
{
|
||||
(__extDM_SingleSignalPath_preemph_activated.303 var=36) merge (__extDM_SingleSignalPath_preemph_activated.223 __extDM_SingleSignalPath_preemph_activated.230) <324>;
|
||||
(__extDM_SingleSignalPath__preemph_scale_nbits.304 var=38) merge (__extDM_SingleSignalPath__preemph_scale_nbits.36 __extDM_SingleSignalPath__preemph_scale_nbits.235) <325>;
|
||||
(__extDM_SingleSignalPath_b_preemph.305 var=39) merge (__extDM_SingleSignalPath_b_preemph.37 __extDM_SingleSignalPath_b_preemph.302) <326>;
|
||||
} #32
|
||||
} #28
|
||||
#34 off=47 nxt=-2
|
||||
(__rd___sp.310 var=40) rd_res_reg (__R_SP.24 __sp.70) <331>;
|
||||
(__R_SP.314 var=26 __sp.315 var=34) wr_res_reg (__rt.439 __sp.70) <335>;
|
||||
() void_ret_dmaddr_ (__la.42) <336>;
|
||||
() sink (__sp.315) <342>;
|
||||
() sink (__extDM_SingleSignalPath_preemph_activated.303) <344>;
|
||||
() sink (__extDM_SingleSignalPath__preemph_scale_nbits.304) <346>;
|
||||
() sink (__extDM_SingleSignalPath_b_preemph.305) <347>;
|
||||
() sink (__ct_0.39) <348>;
|
||||
(__rt.439 var=164) __Pvoid__pl___Pvoid_int18_ (__rd___sp.310 __ct_0s0.588) <548>;
|
||||
(__ct_0s0.588 var=206) const () <755>;
|
||||
} #0
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
0 : (0,133:0,0);
|
||||
4 : (0,135:17,1);
|
||||
7 : (0,135:17,3);
|
||||
10 : (0,135:29,5);
|
||||
13 : (0,135:29,7);
|
||||
16 : (0,135:41,9);
|
||||
19 : (0,135:41,11);
|
||||
22 : (0,135:53,13);
|
||||
25 : (0,135:53,15);
|
||||
28 : (0,135:4,17);
|
||||
30 : (0,135:66,18);
|
||||
34 : (0,149:0,42);
|
||||
247 : (0,147:25,38);
|
||||
383 : (0,135:23,2);
|
||||
388 : (0,135:35,6);
|
||||
393 : (0,135:47,10);
|
||||
398 : (0,135:59,14);
|
||||
434 : (0,141:20,30);
|
||||
479 : (0,135:11,1);
|
||||
482 : (0,135:11,1);
|
||||
483 : (0,135:11,1);
|
||||
488 : (0,135:23,2);
|
||||
491 : (0,135:23,2);
|
||||
492 : (0,135:23,2);
|
||||
497 : (0,135:35,6);
|
||||
500 : (0,135:35,6);
|
||||
501 : (0,135:35,6);
|
||||
506 : (0,135:47,10);
|
||||
509 : (0,135:47,10);
|
||||
510 : (0,135:47,10);
|
||||
515 : (0,135:59,14);
|
||||
518 : (0,135:59,14);
|
||||
519 : (0,135:59,14);
|
||||
542 : (0,141:20,30);
|
||||
545 : (0,141:25,27);
|
||||
546 : (0,141:25,27);
|
||||
570 : (0,147:25,38);
|
||||
573 : (0,141:39,33);
|
||||
574 : (0,141:39,33);
|
||||
579 : (0,141:39,33);
|
||||
580 : (0,141:39,33);
|
||||
585 : (0,143:34,34);
|
||||
586 : (0,143:34,34);
|
||||
591 : (0,143:34,34);
|
||||
592 : (0,143:34,34);
|
||||
597 : (0,143:29,34);
|
||||
598 : (0,143:29,34);
|
||||
603 : (0,144:34,35);
|
||||
604 : (0,144:34,35);
|
||||
609 : (0,144:29,35);
|
||||
610 : (0,144:29,35);
|
||||
615 : (0,145:34,36);
|
||||
616 : (0,145:34,36);
|
||||
621 : (0,145:29,36);
|
||||
622 : (0,145:29,36);
|
||||
627 : (0,146:34,37);
|
||||
628 : (0,146:34,37);
|
||||
633 : (0,146:29,37);
|
||||
634 : (0,146:29,37);
|
||||
639 : (0,147:34,38);
|
||||
640 : (0,147:34,38);
|
||||
645 : (0,147:29,38);
|
||||
646 : (0,147:29,38);
|
||||
----------
|
||||
89 : (0,133:5,0);
|
||||
93 : (0,133:5,0);
|
||||
99 : (0,135:14,0);
|
||||
125 : (0,135:17,1);
|
||||
126 : (0,135:26,0);
|
||||
155 : (0,135:29,5);
|
||||
185 : (0,135:41,9);
|
||||
215 : (0,135:53,13);
|
||||
221 : (0,135:53,16);
|
||||
245 : (0,135:4,17);
|
||||
246 : (0,136:36,0);
|
||||
251 : (0,136:14,18);
|
||||
252 : (0,139:36,0);
|
||||
257 : (0,139:14,21);
|
||||
261 : (0,140:14,22);
|
||||
267 : (0,141:20,0);
|
||||
283 : (0,143:25,34);
|
||||
293 : (0,144:25,35);
|
||||
303 : (0,145:25,36);
|
||||
313 : (0,146:25,37);
|
||||
323 : (0,147:25,38);
|
||||
324 : (0,135:4,41);
|
||||
325 : (0,135:4,41);
|
||||
326 : (0,135:4,41);
|
||||
331 : (0,149:0,0);
|
||||
335 : (0,149:0,42);
|
||||
336 : (0,149:0,42);
|
||||
447 : (0,133:5,0);
|
||||
520 : (0,136:14,18);
|
||||
548 : (0,149:0,0);
|
||||
576 : (0,140:14,0);
|
||||
604 : (0,143:14,0);
|
||||
632 : (0,144:25,0);
|
||||
660 : (0,145:25,0);
|
||||
688 : (0,146:25,0);
|
||||
716 : (0,147:25,0);
|
||||
747 : (0,133:5,0);
|
||||
749 : (0,136:14,0);
|
||||
755 : (0,149:0,0);
|
||||
757 : (0,140:14,0);
|
||||
761 : (0,143:14,0);
|
||||
763 : (0,144:25,0);
|
||||
830 : (0,141:20,0);
|
||||
831 : (0,141:20,30);
|
||||
832 : (0,141:20,30);
|
||||
833 : (0,141:20,30);
|
||||
834 : (0,141:20,30);
|
||||
835 : (0,141:20,30);
|
||||
836 : (0,141:20,30);
|
||||
927 : (0,135:11,0);
|
||||
928 : (0,135:11,1);
|
||||
929 : (0,135:11,1);
|
||||
930 : (0,135:11,1);
|
||||
931 : (0,135:11,1);
|
||||
932 : (0,135:11,1);
|
||||
933 : (0,135:11,1);
|
||||
941 : (0,135:23,2);
|
||||
942 : (0,135:23,2);
|
||||
943 : (0,135:23,2);
|
||||
944 : (0,135:23,2);
|
||||
945 : (0,135:23,2);
|
||||
946 : (0,135:23,2);
|
||||
954 : (0,135:35,6);
|
||||
955 : (0,135:35,6);
|
||||
956 : (0,135:35,6);
|
||||
957 : (0,135:35,6);
|
||||
958 : (0,135:35,6);
|
||||
959 : (0,135:35,6);
|
||||
967 : (0,135:47,10);
|
||||
968 : (0,135:47,10);
|
||||
969 : (0,135:47,10);
|
||||
970 : (0,135:47,10);
|
||||
971 : (0,135:47,10);
|
||||
972 : (0,135:47,10);
|
||||
980 : (0,135:59,14);
|
||||
981 : (0,135:59,14);
|
||||
982 : (0,135:59,14);
|
||||
983 : (0,135:59,14);
|
||||
984 : (0,135:59,14);
|
||||
985 : (0,135:59,14);
|
||||
992 : (0,135:11,1);
|
||||
1000 : (0,135:23,2);
|
||||
1008 : (0,135:35,6);
|
||||
1016 : (0,135:47,10);
|
||||
1024 : (0,135:59,14);
|
||||
1051 : (0,135:59,14);
|
||||
1054 : (0,141:25,0);
|
||||
1055 : (0,141:25,27);
|
||||
1056 : (0,141:25,27);
|
||||
1057 : (0,141:25,27);
|
||||
1058 : (0,141:25,27);
|
||||
1059 : (0,141:25,27);
|
||||
1066 : (0,141:39,0);
|
||||
1067 : (0,141:39,33);
|
||||
1068 : (0,141:39,33);
|
||||
1069 : (0,141:39,33);
|
||||
1070 : (0,141:39,33);
|
||||
1071 : (0,141:39,33);
|
||||
1072 : (0,141:39,33);
|
||||
1078 : (0,141:39,0);
|
||||
1079 : (0,141:39,33);
|
||||
1080 : (0,141:39,33);
|
||||
1081 : (0,141:39,33);
|
||||
1082 : (0,141:39,33);
|
||||
1083 : (0,141:39,33);
|
||||
1090 : (0,143:34,34);
|
||||
1091 : (0,143:34,34);
|
||||
1092 : (0,143:34,34);
|
||||
1093 : (0,143:34,34);
|
||||
1094 : (0,143:34,34);
|
||||
1101 : (0,143:34,0);
|
||||
1102 : (0,143:34,34);
|
||||
1103 : (0,143:34,34);
|
||||
1104 : (0,143:34,34);
|
||||
1105 : (0,143:34,34);
|
||||
1106 : (0,143:34,34);
|
||||
1107 : (0,143:34,34);
|
||||
1114 : (0,143:29,34);
|
||||
1115 : (0,143:29,34);
|
||||
1116 : (0,143:29,34);
|
||||
1117 : (0,143:29,34);
|
||||
1118 : (0,143:29,34);
|
||||
1126 : (0,144:34,35);
|
||||
1127 : (0,144:34,35);
|
||||
1128 : (0,144:34,35);
|
||||
1129 : (0,144:34,35);
|
||||
1130 : (0,144:34,35);
|
||||
1131 : (0,144:34,35);
|
||||
1138 : (0,144:29,35);
|
||||
1139 : (0,144:29,35);
|
||||
1140 : (0,144:29,35);
|
||||
1141 : (0,144:29,35);
|
||||
1142 : (0,144:29,35);
|
||||
1150 : (0,145:34,36);
|
||||
1151 : (0,145:34,36);
|
||||
1152 : (0,145:34,36);
|
||||
1153 : (0,145:34,36);
|
||||
1154 : (0,145:34,36);
|
||||
1155 : (0,145:34,36);
|
||||
1162 : (0,145:29,36);
|
||||
1163 : (0,145:29,36);
|
||||
1164 : (0,145:29,36);
|
||||
1165 : (0,145:29,36);
|
||||
1166 : (0,145:29,36);
|
||||
1174 : (0,146:34,37);
|
||||
1175 : (0,146:34,37);
|
||||
1176 : (0,146:34,37);
|
||||
1177 : (0,146:34,37);
|
||||
1178 : (0,146:34,37);
|
||||
1179 : (0,146:34,37);
|
||||
1186 : (0,146:29,37);
|
||||
1187 : (0,146:29,37);
|
||||
1188 : (0,146:29,37);
|
||||
1189 : (0,146:29,37);
|
||||
1190 : (0,146:29,37);
|
||||
1198 : (0,147:34,38);
|
||||
1199 : (0,147:34,38);
|
||||
1200 : (0,147:34,38);
|
||||
1201 : (0,147:34,38);
|
||||
1202 : (0,147:34,38);
|
||||
1203 : (0,147:34,38);
|
||||
1210 : (0,147:29,38);
|
||||
1211 : (0,147:29,38);
|
||||
1212 : (0,147:29,38);
|
||||
1213 : (0,147:29,38);
|
||||
1214 : (0,147:29,38);
|
||||
1262 : (0,135:11,1);
|
||||
1263 : (0,135:23,2);
|
||||
1264 : (0,135:17,4);
|
||||
1265 : (0,135:35,6);
|
||||
1266 : (0,135:29,8);
|
||||
1267 : (0,135:47,10);
|
||||
1268 : (0,135:41,12);
|
||||
1292 : (0,135:17,1);
|
||||
1296 : (0,135:29,5);
|
||||
1300 : (0,135:41,9);
|
||||
1304 : (0,135:53,13);
|
||||
1308 : (0,135:4,17);
|
||||
|
||||
8
simulation/Release/chesswork/signal_path-fcd1fd.#
Normal file
8
simulation/Release/chesswork/signal_path-fcd1fd.#
Normal file
@@ -0,0 +1,8 @@
|
||||
6bd14b3bc305504dd7bb9269fe30bf59aca75a76
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
b00c70141a9ef8150a816e6a96c0a6bc875ec33f
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
122d38bb381f5f89236bf4743d8e37e54b004dea
|
||||
105
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path-fcd1fd.o
Normal file
BIN
simulation/Release/chesswork/signal_path-fcd1fd.o
Normal file
Binary file not shown.
115
simulation/Release/chesswork/signal_path-fcd1fd.sfg
Normal file
115
simulation/Release/chesswork/signal_path-fcd1fd.sfg
Normal file
@@ -0,0 +1,115 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
/***
|
||||
!! void sig_cirular_buffer_ptr_increment(BufferPtr *, int)
|
||||
F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_increment" 'void sig_cirular_buffer_ptr_increment(BufferPtr *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
}
|
||||
****
|
||||
***/
|
||||
|
||||
[
|
||||
0 : _Z32sig_cirular_buffer_ptr_incrementP9BufferPtri typ=uint20_ bnd=e stl=PM tref=void_____PBufferPtr___sint__
|
||||
11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
|
||||
26 : __R_SP typ=dmaddr_ bnd=d stl=SP
|
||||
34 : __sp typ=dmaddr_ bnd=b stl=SP
|
||||
36 : __extDM_BufferPtr_ptr_current typ=int8_ bnd=b stl=DM
|
||||
38 : __extDM_BufferPtr_ptr_start typ=int8_ bnd=b stl=DM
|
||||
39 : __extDM_BufferPtr_buffer_len typ=int8_ bnd=b stl=DM
|
||||
41 : __rd___sp typ=dmaddr_ bnd=m
|
||||
42 : __ct_0 typ=uint1_ val=0f bnd=m
|
||||
43 : __la typ=dmaddr_ bnd=p tref=dmaddr___
|
||||
44 : buffer typ=dmaddr_ bnd=p tref=__PBufferPtr__
|
||||
45 : i_incr typ=int32_ bnd=p tref=__sint__
|
||||
52 : __fch___extDM_BufferPtr_ptr_current typ=dmaddr_ bnd=m
|
||||
59 : __fch___extDM_BufferPtr_ptr_start typ=dmaddr_ bnd=m
|
||||
63 : __fch___extDM_BufferPtr_buffer_len typ=int32_ bnd=m
|
||||
67 : __tmp typ=dmaddr_ bnd=m
|
||||
90 : __ct_2 typ=int32_ val=2f bnd=m
|
||||
93 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
|
||||
118 : __ct_0S0 typ=int18_ val=0S0 bnd=m
|
||||
119 : __ct_8 typ=int18_ val=8f bnd=m
|
||||
122 : __ct_0s0 typ=int18_ val=0s0 bnd=m
|
||||
124 : __ct_4 typ=int18_ val=4f bnd=m
|
||||
128 : __ct_2 typ=uint2_ val=2f bnd=m
|
||||
133 : __tmp typ=int18_ bnd=m
|
||||
134 : __tmp typ=int18_ bnd=m
|
||||
]
|
||||
F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri {
|
||||
(__M_WDMA.9 var=11) st_def () <18>;
|
||||
(__R_SP.24 var=26) st_def () <48>;
|
||||
(__sp.32 var=34) source () <56>;
|
||||
(__extDM_BufferPtr_ptr_current.34 var=36) source () <58>;
|
||||
(__extDM_BufferPtr_ptr_start.36 var=38) source () <60>;
|
||||
(__extDM_BufferPtr_buffer_len.37 var=39) source () <61>;
|
||||
(__ct_0.40 var=42) const () <64>;
|
||||
(__la.42 var=43 stl=LR off=0) inp () <66>;
|
||||
(__la.43 var=43) deassign (__la.42) <67>;
|
||||
(buffer.45 var=44 stl=A off=0) inp () <69>;
|
||||
(buffer.46 var=44) deassign (buffer.45) <70>;
|
||||
(i_incr.48 var=45 stl=RA off=0) inp () <72>;
|
||||
(i_incr.49 var=45) deassign (i_incr.48) <73>;
|
||||
(__rd___sp.51 var=41) rd_res_reg (__R_SP.24 __sp.32) <75>;
|
||||
(__R_SP.55 var=26 __sp.56 var=34) wr_res_reg (__rt.133 __sp.32) <79>;
|
||||
(__fch___extDM_BufferPtr_ptr_current.60 var=52) load (__M_WDMA.9 __rt.155 __extDM_BufferPtr_ptr_current.34) <84>;
|
||||
(__fch___extDM_BufferPtr_ptr_start.67 var=59) load (__M_WDMA.9 __rt.199 __extDM_BufferPtr_ptr_start.36) <91>;
|
||||
(__fch___extDM_BufferPtr_buffer_len.71 var=63) load (__M_WDMA.9 __rt.221 __extDM_BufferPtr_buffer_len.37) <95>;
|
||||
(__M_WDMA.79 var=11 __extDM_BufferPtr_ptr_current.80 var=36) store (__tmp.110 __rt.243 __extDM_BufferPtr_ptr_current.34) <103>;
|
||||
(__rd___sp.81 var=41) rd_res_reg (__R_SP.24 __sp.56) <104>;
|
||||
(__R_SP.85 var=26 __sp.86 var=34) wr_res_reg (__rt.177 __sp.56) <108>;
|
||||
() void_ret_dmaddr_ (__la.43) <109>;
|
||||
() sink (__sp.86) <115>;
|
||||
() sink (__extDM_BufferPtr_ptr_current.80) <117>;
|
||||
() sink (__ct_0.40) <122>;
|
||||
(__tmp.110 var=67) dmaddr__add_mod_dmaddr__int18__dmaddr__int18_ (__fch___extDM_BufferPtr_ptr_current.60 __tmp.266 __fch___extDM_BufferPtr_ptr_start.67 __tmp.271) <155>;
|
||||
(__ct_2.119 var=90) const () <175>;
|
||||
(__rt.133 var=93) __Pvoid__pl___Pvoid_int18_ (__rd___sp.51 __ct_0S0.256) <201>;
|
||||
(__rt.155 var=93) __Pvoid__pl___Pvoid_int18_ (buffer.46 __ct_8.257) <229>;
|
||||
(__rt.177 var=93) __Pvoid__pl___Pvoid_int18_ (__rd___sp.81 __ct_0s0.260) <257>;
|
||||
(__rt.199 var=93) __Pvoid__mi___Pvoid_int18_ (__rt.155 __ct_4.262) <285>;
|
||||
(__rt.221 var=93) __Pvoid__mi___Pvoid_int18_ (__rt.199 __ct_4.262) <313>;
|
||||
(__rt.243 var=93) __Pvoid__pl___Pvoid_int18_ (__rt.221 __ct_8.257) <341>;
|
||||
(__ct_0S0.256 var=118) const () <367>;
|
||||
(__ct_8.257 var=119) const () <369>;
|
||||
(__ct_0s0.260 var=122) const () <375>;
|
||||
(__ct_4.262 var=124) const () <379>;
|
||||
(__ct_2.265 var=128) const () <384>;
|
||||
(__tmp.266 var=133) int72__shift_int72__int72__uint2_ (i_incr.49 __ct_2.119 __ct_2.265) <385>;
|
||||
(__tmp.271 var=134) int72__shift_int72__int72__uint2_ (__fch___extDM_BufferPtr_buffer_len.71 __ct_2.119 __ct_2.265) <393>;
|
||||
} #5 off=0 nxt=-2
|
||||
0 : 'signal_processing\\signal_path.c';
|
||||
----------
|
||||
5 : (0,105:0,2);
|
||||
----------
|
||||
75 : (0,103:5,0);
|
||||
79 : (0,103:5,0);
|
||||
84 : (0,104:43,1);
|
||||
91 : (0,104:72,1);
|
||||
95 : (0,104:91,1);
|
||||
103 : (0,104:10,1);
|
||||
104 : (0,105:0,0);
|
||||
108 : (0,105:0,2);
|
||||
109 : (0,105:0,2);
|
||||
155 : (0,104:26,1);
|
||||
175 : (0,104:58,0);
|
||||
201 : (0,103:5,0);
|
||||
229 : (0,104:43,1);
|
||||
257 : (0,105:0,0);
|
||||
285 : (0,104:72,0);
|
||||
341 : (0,104:43,0);
|
||||
367 : (0,103:5,0);
|
||||
369 : (0,104:43,0);
|
||||
375 : (0,105:0,0);
|
||||
379 : (0,104:72,0);
|
||||
384 : (0,104:58,0);
|
||||
385 : (0,104:58,1);
|
||||
393 : (0,104:91,1);
|
||||
|
||||
0
simulation/Release/chesswork/signal_path.aliases
Normal file
0
simulation/Release/chesswork/signal_path.aliases
Normal file
24
simulation/Release/chesswork/signal_path.ctt
Normal file
24
simulation/Release/chesswork/signal_path.ctt
Normal file
@@ -0,0 +1,24 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
#const float_tininess_after_rounding enum __anonymous0__signal_path_ 0 (0x0)
|
||||
#const float_tininess_before_rounding enum __anonymous0__signal_path_ 1 (0x1)
|
||||
#const float_round_nearest_even enum __anonymous1__signal_path_ 0 (0x0)
|
||||
#const float_round_to_zero enum __anonymous1__signal_path_ 1 (0x1)
|
||||
#const float_round_up enum __anonymous1__signal_path_ 2 (0x2)
|
||||
#const float_round_down enum __anonymous1__signal_path_ 3 (0x3)
|
||||
#const block_len const int 1 (0x1)
|
||||
#const OUTPUT_MODE_C_SENSOR enum OutputMode 0 (0x0)
|
||||
#const OUTPUT_MODE_ACC_SENSOR enum OutputMode 1 (0x1)
|
||||
#const OUTPUT_MODE_FIR_LMS enum OutputMode 2 (0x2)
|
||||
#const OUTPUT_MODE_FIR enum OutputMode 3 (0x3)
|
||||
#const OUTPUT_MODE_FIR_LMS_LEAKY enum OutputMode 4 (0x4)
|
||||
#const ones unsigned 4294967295 (0xffffffff)
|
||||
#const scale_bits int 31 (0x1f)
|
||||
#const scale int 2147483647 (0x7fffffff)
|
||||
#const __tmpb1_F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi const double 2.0000000000000000 (0x4000000000000000)
|
||||
#const __inl_x double 2.0000000000000000 (0x4000000000000000)
|
||||
#const __tmpb1_F_Z15sig_init_weightP16SingleSignalPathdi const double 2.0000000000000000 (0x4000000000000000)
|
||||
#const __inl_x double 2.0000000000000000 (0x4000000000000000)
|
||||
255
simulation/Release/chesswork/signal_path.dti
Normal file
255
simulation/Release/chesswork/signal_path.dti
Normal file
@@ -0,0 +1,255 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
bool__ : _basic() bool;
|
||||
__cchar__ : _basic() __cchar;
|
||||
__schar__ : _basic() __schar;
|
||||
__uchar__ : _basic() __uchar;
|
||||
__sshort__ : _basic() __sshort;
|
||||
__ushort__ : _basic() __ushort;
|
||||
__sint__ : _basic() __sint;
|
||||
__uint__ : _basic() __uint;
|
||||
__slong__ : _basic() __slong;
|
||||
__ulong__ : _basic() __ulong;
|
||||
__flongdouble__ : _basic() __flongdouble;
|
||||
int72___ : _basic() int72_;
|
||||
int32___ : _basic() int32_;
|
||||
__slonglong__ : _basic() __slonglong;
|
||||
__ulonglong__ : _basic() __ulonglong;
|
||||
__Pvoid__ : _basic() __Pvoid;
|
||||
int64___ : _basic() int64_;
|
||||
accum_t__ : _basic() accum_t;
|
||||
flags_t__ : _basic() flags_t;
|
||||
__rtp__ : _typedef() __rtp $__ulonglong__;
|
||||
__atp0__ : _typedef() __atp0 $accum_t__;
|
||||
__atp1__ : _typedef() __atp1 $accum_t__;
|
||||
__atp2__ : _typedef() __atp2 $__ulonglong__;
|
||||
dmaddr___ : _basic() dmaddr_;
|
||||
float32__ : _typedef() float32 $__uint__;
|
||||
__rtp___1 : _typedef() __rtp $float32__;
|
||||
__atp0___1 : _typedef() __atp0 $__sint__;
|
||||
float64__ : _typedef() float64 $__ulonglong__;
|
||||
__rtp___2 : _typedef() __rtp $float64__;
|
||||
__atp0___2 : _typedef() __atp0 $__sint__;
|
||||
__rtp___3 : _typedef() __rtp $float32__;
|
||||
__atp0___3 : _typedef() __atp0 $__slonglong__;
|
||||
__rtp___4 : _typedef() __rtp $float64__;
|
||||
__atp0___4 : _typedef() __atp0 $__slonglong__;
|
||||
__rtp___5 : _typedef() __rtp $__sint__;
|
||||
__atp0___5 : _typedef() __atp0 $float32__;
|
||||
__rtp___6 : _typedef() __rtp $__slonglong__;
|
||||
__atp0___6 : _typedef() __atp0 $float32__;
|
||||
__rtp___7 : _typedef() __rtp $float64__;
|
||||
__atp0___7 : _typedef() __atp0 $float32__;
|
||||
__rtp___8 : _typedef() __rtp $float32__;
|
||||
__atp0___8 : _typedef() __atp0 $float32__;
|
||||
__rtp___9 : _typedef() __rtp $float32__;
|
||||
__atp0___9 : _typedef() __atp0 $float32__;
|
||||
__atp1___1 : _typedef() __atp1 $float32__;
|
||||
__rtp___10 : _typedef() __rtp $float32__;
|
||||
__atp0___10 : _typedef() __atp0 $float32__;
|
||||
__atp1___2 : _typedef() __atp1 $float32__;
|
||||
__rtp___11 : _typedef() __rtp $float32__;
|
||||
__atp0___11 : _typedef() __atp0 $float32__;
|
||||
__atp1___3 : _typedef() __atp1 $float32__;
|
||||
__rtp___12 : _typedef() __rtp $float32__;
|
||||
__atp0___12 : _typedef() __atp0 $float32__;
|
||||
__atp1___4 : _typedef() __atp1 $float32__;
|
||||
__rtp___13 : _typedef() __rtp $__sint__;
|
||||
__atp0___13 : _typedef() __atp0 $float32__;
|
||||
__atp1___5 : _typedef() __atp1 $float32__;
|
||||
__rtp___14 : _typedef() __rtp $__sint__;
|
||||
__atp0___14 : _typedef() __atp0 $float32__;
|
||||
__atp1___6 : _typedef() __atp1 $float32__;
|
||||
__rtp___15 : _typedef() __rtp $__sint__;
|
||||
__atp0___15 : _typedef() __atp0 $float32__;
|
||||
__atp1___7 : _typedef() __atp1 $float32__;
|
||||
__rtp___16 : _typedef() __rtp $__sint__;
|
||||
__atp0___16 : _typedef() __atp0 $float64__;
|
||||
__rtp___17 : _typedef() __rtp $__slonglong__;
|
||||
__atp0___17 : _typedef() __atp0 $float64__;
|
||||
__rtp___18 : _typedef() __rtp $float32__;
|
||||
__atp0___18 : _typedef() __atp0 $float64__;
|
||||
__rtp___19 : _typedef() __rtp $float64__;
|
||||
__atp0___19 : _typedef() __atp0 $float64__;
|
||||
__rtp___20 : _typedef() __rtp $float64__;
|
||||
__atp0___20 : _typedef() __atp0 $float64__;
|
||||
__atp1___8 : _typedef() __atp1 $float64__;
|
||||
__rtp___21 : _typedef() __rtp $float64__;
|
||||
__atp0___21 : _typedef() __atp0 $float64__;
|
||||
__atp1___9 : _typedef() __atp1 $float64__;
|
||||
__rtp___22 : _typedef() __rtp $float64__;
|
||||
__atp0___22 : _typedef() __atp0 $float64__;
|
||||
__atp1___10 : _typedef() __atp1 $float64__;
|
||||
__rtp___23 : _typedef() __rtp $float64__;
|
||||
__atp0___23 : _typedef() __atp0 $float64__;
|
||||
__atp1___11 : _typedef() __atp1 $float64__;
|
||||
__rtp___24 : _typedef() __rtp $__sint__;
|
||||
__atp0___24 : _typedef() __atp0 $float64__;
|
||||
__atp1___12 : _typedef() __atp1 $float64__;
|
||||
__rtp___25 : _typedef() __rtp $__sint__;
|
||||
__atp0___25 : _typedef() __atp0 $float64__;
|
||||
__atp1___13 : _typedef() __atp1 $float64__;
|
||||
__rtp___26 : _typedef() __rtp $__sint__;
|
||||
__atp0___26 : _typedef() __atp0 $float64__;
|
||||
__atp1___14 : _typedef() __atp1 $float64__;
|
||||
__ffloat__ : _basic() __ffloat;
|
||||
__fdouble__ : _basic() __fdouble;
|
||||
uint15__IMSK : _basic(IMSK,1,1) uint15_;
|
||||
uint15__irq_stat : _basic(irq_stat,1,1) uint15_;
|
||||
__sint_DMA : _basic(DMA,4,4) __sint;
|
||||
__Pvoid_DMA : _basic(DMA,4,4) __Pvoid;
|
||||
__P__sint_DMA : _pointer(DMA,4,4) $__Pvoid_DMA $__sint_DMA;
|
||||
BufferPtr_DMA : _struct(DMA,12,4) BufferPtr {
|
||||
buffer_len $__sint_DMA @0;
|
||||
ptr_start $__P__sint_DMA @4;
|
||||
ptr_current $__P__sint_DMA @8;
|
||||
}
|
||||
__sint_DMB : _basic(DMB,4,4) __sint;
|
||||
__Pvoid_DMB : _basic(DMB,4,4) __Pvoid;
|
||||
__PDMB__sint_DMB : _pointer(DMB,4,4) $__Pvoid_DMB $__sint_DMB;
|
||||
BufferPtrDMB_DMB : _struct(DMB,12,4) BufferPtrDMB {
|
||||
buffer_len $__sint_DMB @0;
|
||||
ptr_start $__PDMB__sint_DMB @4;
|
||||
ptr_current $__PDMB__sint_DMB @8;
|
||||
}
|
||||
__A64DMB__sint_DMB : _array(DMB,256,4) [64] $__sint_DMB;
|
||||
__A64__sint_DMA : _array(DMA,256,4) [64] $__sint_DMA;
|
||||
__rtp___27 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___27 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___15 : _typedef() __atp1 $__sint__;
|
||||
__rtp___28 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___28 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___16 : _typedef() __atp1 $__sint__;
|
||||
__rtp___29 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___29 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___30 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___30 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___31 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___31 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___32 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___32 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___33 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___33 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___34 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___34 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___35 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___35 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___36 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___36 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___37 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___37 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___38 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___38 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___39 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___39 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___40 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___40 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___41 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___41 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___42 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___42 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___43 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___43 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___44 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___44 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___45 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___45 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___46 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___46 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___47 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___47 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___17 : _typedef() __atp1 $__ffloat__;
|
||||
__rtp___48 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___48 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___18 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___49 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___49 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___19 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___50 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___50 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___51 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___51 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___52 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___52 : _typedef() __atp0 $__ffloat__;
|
||||
__rtp___53 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___53 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___54 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___54 : _typedef() __atp0 $__fdouble__;
|
||||
__rtp___55 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___55 : _typedef() __atp0 $__ffloat__;
|
||||
__atp1___20 : _typedef() __atp1 $__ffloat__;
|
||||
__rtp___56 : _typedef() __rtp $__fdouble__;
|
||||
__atp0___56 : _typedef() __atp0 $__fdouble__;
|
||||
__atp1___21 : _typedef() __atp1 $__fdouble__;
|
||||
__rtp___57 : _typedef() __rtp $__ffloat__;
|
||||
__atp0___57 : _typedef() __atp0 $__ffloat__;
|
||||
__PDMBvoid__ : _basic() __PDMBvoid;
|
||||
fract_t__ : _basic() fract_t;
|
||||
pmem_t__ : _basic() pmem_t;
|
||||
__PDMvoid__ : _basic() __PDMvoid;
|
||||
__PDMAvoid__ : _basic() __PDMAvoid;
|
||||
__PDMIOvoid__ : _basic() __PDMIOvoid;
|
||||
__PPMvoid__ : _basic() __PPMvoid;
|
||||
__A1__sint_DMA : _array(DMA,4,4) [1] $__sint_DMA;
|
||||
__A1DMB__sint_DMB : _array(DMB,4,4) [1] $__sint_DMB;
|
||||
__P__sint__ : _pointer() $__Pvoid__ $__sint_DMA;
|
||||
__PDMB__sint_DMA : _pointer(DMA,4,4) $__Pvoid_DMA $__sint_DMB;
|
||||
__PDMB__sint__ : _pointer() $__Pvoid__ $__sint_DMB;
|
||||
__PBufferPtr__ : _pointer() $__Pvoid__ $BufferPtr_DMA;
|
||||
__sint_____PBufferPtr___P__sint___sint___sint__ : _function() $__sint__ $__PBufferPtr__ $__P__sint__ $__sint__ $__sint__;
|
||||
__PDMBBufferPtrDMB__ : _pointer() $__Pvoid__ $BufferPtrDMB_DMB;
|
||||
__sint_____PDMBBufferPtrDMB___PDMB__sint___sint___sint__ : _function() $__sint__ $__PDMBBufferPtrDMB__ $__PDMB__sint__ $__sint__ $__sint__;
|
||||
void_____PBufferPtr___sint__ : _function() _void $__PBufferPtr__ $__sint__;
|
||||
BufferPtrDMB_DMA : _struct(DMA,12,4) BufferPtrDMB {
|
||||
buffer_len $__sint_DMA @0;
|
||||
ptr_start $__PDMB__sint_DMA @4;
|
||||
ptr_current $__PDMB__sint_DMA @8;
|
||||
}
|
||||
__PBufferPtrDMB__ : _pointer() $__Pvoid__ $BufferPtrDMB_DMA;
|
||||
void_____PBufferPtrDMB___sint__ : _function() _void $__PBufferPtrDMB__ $__sint__;
|
||||
void_____PBufferPtr___sint___1 : _function() _void $__PBufferPtr__ $__sint__;
|
||||
void_____PDMBBufferPtrDMB___sint__ : _function() _void $__PDMBBufferPtrDMB__ $__sint__;
|
||||
__A5__sint_DMA : _array(DMA,20,4) [5] $__sint_DMA;
|
||||
__A2__sint_DMA : _array(DMA,8,4) [2] $__sint_DMA;
|
||||
__A16__sint_DMA : _array(DMA,64,4) [16] $__sint_DMA;
|
||||
SingleSignalPath_DMA : _struct(DMA,144,4) SingleSignalPath {
|
||||
input_scale $__sint_DMA @0;
|
||||
x_nbit_bitshift $__sint_DMA @4;
|
||||
preemph_activated $__sint_DMA @8;
|
||||
b_preemph $__A5__sint_DMA @12;
|
||||
_preemph_scale_nbits $__sint_DMA @32;
|
||||
_xd $__A2__sint_DMA @36;
|
||||
_yd $__A2__sint_DMA @44;
|
||||
_delay_buffer $__A16__sint_DMA @52;
|
||||
delay_buffer $BufferPtr_DMA @116;
|
||||
n_delay_samps $__sint_DMA @128;
|
||||
weight_actived $__sint_DMA @132;
|
||||
weight $__sint_DMA @136;
|
||||
_weight_scale_nbits $__sint_DMA @140;
|
||||
}
|
||||
__PSingleSignalPath__ : _pointer() $__Pvoid__ $SingleSignalPath_DMA;
|
||||
void_____PSingleSignalPath___fdouble___fdouble___fdouble___fdouble___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__fdouble__ $__fdouble__ $__fdouble__ $__fdouble__ $__fdouble__ $__sint__;
|
||||
__sint_____PSingleSignalPath___sint__ : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
|
||||
void_____PSingleSignalPath___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__fdouble__ $__sint__;
|
||||
__sint_____PSingleSignalPath___sint___1 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
|
||||
__sint_____PSingleSignalPath___sint___2 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
|
||||
__sint_____PSingleSignalPath___sint___3 : _function() $__sint__ $__PSingleSignalPath__ $__sint__;
|
||||
__fdouble_DMA : _basic(DMA,8,8) __fdouble;
|
||||
__P__fdouble__ : _pointer() $__Pvoid__ $__fdouble_DMA;
|
||||
void_____PSingleSignalPath___PSingleSignalPath___P__fdouble___P__fdouble___sint___sint___fdouble___fdouble___fdouble___sint__ : _function() _void $__PSingleSignalPath__ $__PSingleSignalPath__ $__P__fdouble__ $__P__fdouble__ $__sint__ $__sint__ $__fdouble__ $__fdouble__ $__fdouble__ $__sint__;
|
||||
OutputMode__ : _enum() OutputMode $__sint__ {
|
||||
OUTPUT_MODE_C_SENSOR = 0;
|
||||
OUTPUT_MODE_ACC_SENSOR = 1;
|
||||
OUTPUT_MODE_FIR_LMS = 2;
|
||||
OUTPUT_MODE_FIR = 3;
|
||||
OUTPUT_MODE_FIR_LMS_LEAKY = 4;
|
||||
}
|
||||
__sshort_DMB : _basic(DMB,2,2) __sshort;
|
||||
int16_t_DMB : _typedef(DMB,2,2) int16_t $__sshort_DMB;
|
||||
__PDMB__sshort__ : _pointer() $__Pvoid__ $int16_t_DMB;
|
||||
void_____PSingleSignalPath___PSingleSignalPath_OutputMode___PDMB__sshort___PDMB__sshort___PDMB__sshort__ : _function() _void $__PSingleSignalPath__ $__PSingleSignalPath__ $OutputMode__ $__PDMB__sshort__ $__PDMB__sshort__ $__PDMB__sshort__;
|
||||
uint32_t__ : _typedef() uint32_t $__uint__;
|
||||
void__ : _basic() void;
|
||||
152
simulation/Release/chesswork/signal_path.fnm
Normal file
152
simulation/Release/chesswork/signal_path.fnm
Normal file
@@ -0,0 +1,152 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
// toolrelease _25R2;
|
||||
|
||||
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\simulation\\signal_processing\\signal_path.c"
|
||||
"C:\\Users\\phangl\\00_Repos\\06_DSP_Simulation\\simulation"
|
||||
|
||||
"signal_path-154f66.sfg"
|
||||
: _Z15sig_init_bufferP9BufferPtrPiii
|
||||
: "sig_init_buffer" global "signal_processing\\signal_path.c" 71 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-f55921.sfg"
|
||||
: _Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii
|
||||
: "sig_init_buffer_DMB" global "signal_processing\\signal_path.c" 87 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-fcd1fd.sfg"
|
||||
: _Z32sig_cirular_buffer_ptr_incrementP9BufferPtri
|
||||
: "sig_cirular_buffer_ptr_increment" global "signal_processing\\signal_path.c" 103 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-352f49.sfg"
|
||||
: _Z36sig_cirular_buffer_ptr_increment_DMBP12BufferPtrDMBi
|
||||
: "sig_cirular_buffer_ptr_increment_DMB" global "signal_processing\\signal_path.c" 107 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-e110bc.sfg"
|
||||
: _Z33sig_cirular_buffer_ptr_put_sampleP9BufferPtri
|
||||
: "sig_cirular_buffer_ptr_put_sample" global "signal_processing\\signal_path.c" 111 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-e7968f.sfg"
|
||||
: _Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi
|
||||
: "sig_cirular_buffer_ptr_put_sample_DMB" global "signal_processing\\signal_path.c" 116 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-f8ba01.sfg"
|
||||
: _Z21sig_init_preemph_coefP16SingleSignalPathdddddi
|
||||
: "sig_init_preemph_coef" global "signal_processing\\signal_path.c" 133 Ofile
|
||||
(
|
||||
ff_pow
|
||||
_Z10float64_eqyy
|
||||
_Z16int32_to_float64i
|
||||
_Z11float64_subyy
|
||||
_Z30float64_to_int32_round_to_zeroy
|
||||
_Z11float64_mulyy
|
||||
)
|
||||
|
||||
"signal_path-6fcf7f.sfg"
|
||||
: _Z14sig_init_delayP16SingleSignalPathi
|
||||
: "sig_init_delay" global "signal_processing\\signal_path.c" 152 Ofile
|
||||
(
|
||||
_Z15sig_init_bufferP9BufferPtrPiii
|
||||
)
|
||||
|
||||
"signal_path-d74ce2.sfg"
|
||||
: _Z15sig_init_weightP16SingleSignalPathdi
|
||||
: "sig_init_weight" global "signal_processing\\signal_path.c" 157 Ofile
|
||||
(
|
||||
ff_pow
|
||||
_Z10float64_eqyy
|
||||
_Z16int32_to_float64i
|
||||
_Z11float64_subyy
|
||||
_Z30float64_to_int32_round_to_zeroy
|
||||
_Z11float64_mulyy
|
||||
)
|
||||
|
||||
"signal_path-d6dbe4.sfg"
|
||||
: _Z15sig_calc_biquadP16SingleSignalPathi
|
||||
: "sig_calc_biquad" global "signal_processing\\signal_path.c" 173 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-a30375.sfg"
|
||||
: _Z29sig_delay_buffer_load_and_getP16SingleSignalPathi
|
||||
: "sig_delay_buffer_load_and_get" global "signal_processing\\signal_path.c" 194 Ofile
|
||||
(
|
||||
_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri
|
||||
)
|
||||
|
||||
"signal_path-530a42.sfg"
|
||||
: _Z15sig_calc_weightP16SingleSignalPathi
|
||||
: "sig_calc_weight" global "signal_processing\\signal_path.c" 204 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
"signal_path-9c02ae.sfg"
|
||||
: _Z4initP16SingleSignalPathS0_PdS1_iidddi
|
||||
: "init" global "signal_processing\\signal_path.c" 309 Ofile
|
||||
(
|
||||
_Z21sig_init_preemph_coefP16SingleSignalPathdddddi
|
||||
_Z14sig_init_delayP16SingleSignalPathi
|
||||
_Z15sig_init_weightP16SingleSignalPathdi
|
||||
_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii
|
||||
_Z15sig_init_bufferP9BufferPtrPiii
|
||||
_Z11float64_mulyy
|
||||
_Z30float64_to_int32_round_to_zeroy
|
||||
)
|
||||
|
||||
"signal_path-101f20.sfg"
|
||||
: _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
: "calc" global "signal_processing\\signal_path.c" 348 Ofile
|
||||
(
|
||||
_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi
|
||||
)
|
||||
|
||||
""
|
||||
: ff_pow
|
||||
: "ff_pow" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\runtime\\include\\math.h" 80 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z10float64_eqyy
|
||||
: "float64_eq" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\softfloat\\softfloat.h" 162 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z16int32_to_float64i
|
||||
: "int32_to_float64" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\softfloat\\softfloat.h" 112 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z11float64_subyy
|
||||
: "float64_sub" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\softfloat\\softfloat.h" 157 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z30float64_to_int32_round_to_zeroy
|
||||
: "float64_to_int32_round_to_zero" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\softfloat\\softfloat.h" 147 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
""
|
||||
: _Z11float64_mulyy
|
||||
: "float64_mul" global "..\\..\\..\\OneDrive - MED-EL\\Desktop\\LPDSP32_Modell\\lib\\softfloat\\softfloat.h" 158 Ofile
|
||||
(
|
||||
)
|
||||
|
||||
33
simulation/Release/chesswork/signal_path.gvt
Normal file
33
simulation/Release/chesswork/signal_path.gvt
Normal file
@@ -0,0 +1,33 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
[
|
||||
1 : _imsk_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=IMSK tref=uint15__IMSK
|
||||
2 : _irq_stat_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=irq_stat tref=uint15__irq_stat
|
||||
3 : ptr_fir_lms_coeffs typ=int8_ bnd=e sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
|
||||
4 : ptr_fir_lms_delay_line typ=int8_ bnd=e sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
|
||||
5 : fir_lms_delay_line typ=int8_ bnd=e sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
|
||||
6 : _ZL7counter typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
7 : _ZL2mu typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
8 : _ZL4leak typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__sint_DMA
|
||||
9 : fir_lms_delay_line typ=int8_ bnd=g sz=256 algn=4 stl=DMB tref=__A64DMB__sint_DMB
|
||||
10 : ptr_fir_lms_delay_line typ=int8_ bnd=g sz=12 algn=4 stl=DMB tref=BufferPtrDMB_DMB
|
||||
11 : ptr_fir_lms_coeffs typ=int8_ bnd=g sz=12 algn=4 stl=DMA tref=BufferPtr_DMA
|
||||
12 : fir_lms_coeffs typ=int8_ bnd=g sz=256 algn=8 stl=DMA tref=__A64__sint_DMA
|
||||
13 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
14 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
15 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
16 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__A1__sint_DMA
|
||||
17 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
|
||||
18 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMB tref=__A1DMB__sint_DMB
|
||||
19 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__P__sint_DMA
|
||||
20 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__P__sint_DMA
|
||||
21 : _ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32 typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sint_DMA
|
||||
]
|
||||
__signal_path_sttc {
|
||||
} #0
|
||||
----------
|
||||
----------
|
||||
|
||||
8
simulation/Release/chesswork/signal_path.gvt.#
Normal file
8
simulation/Release/chesswork/signal_path.gvt.#
Normal file
@@ -0,0 +1,8 @@
|
||||
b94f5e81f66808a8f4f9315bd020e05811fb8d4a
|
||||
842f4b2e587ac9c93f0ed2be9e41223a9cf4fa79
|
||||
42695db990e5aaff0b9f36d25938c80e96ce47cc
|
||||
afdf5390cdc5affd5e50c6ca82dc307d96b63dce
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
da39a3ee5e6b4b0d3255bfef95601890afd80709
|
||||
0
|
||||
0
|
||||
BIN
simulation/Release/chesswork/signal_path.gvt.o
Normal file
BIN
simulation/Release/chesswork/signal_path.gvt.o
Normal file
Binary file not shown.
21
simulation/Release/chesswork/signal_path.ini
Normal file
21
simulation/Release/chesswork/signal_path.ini
Normal file
@@ -0,0 +1,21 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
_ZL7counter/6 $ counter
|
||||
_ZL2mu/7 $ mu
|
||||
_ZL4leak/8 $ leak
|
||||
_ZL4leak/8 : #1d #ac #ff #7f
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre/13 $ c_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre/14 $ acc_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E10cSensor_32/15 $ cSensor_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E12accSensor_32/16 $ accSensor_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E14acc_block_filt/17 $ acc_block_filt _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32/18 $ out_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre/19 $ p_c_block_pre _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13p_c_block_pre/19 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E11c_block_pre #00 #00 #00 #00
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt/20 $ p_acc_block_filt _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E16p_acc_block_filt/20 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E13acc_block_pre #00 #00 #00 #00
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32/21 $ p_out_32 _Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_
|
||||
_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E8p_out_32/21 : (dmaddr_:int32_:0)_ZZ4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_E6out_32 #00 #00 #00 #00
|
||||
207
simulation/Release/chesswork/signal_path.lib
Normal file
207
simulation/Release/chesswork/signal_path.lib
Normal file
@@ -0,0 +1,207 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
toolrelease _25R2;
|
||||
|
||||
|
||||
// additional
|
||||
prop gp_offset_type = ( __sint );
|
||||
|
||||
prop static_variable_registers = ( IMSK irq_stat );
|
||||
|
||||
// float64 int32_to_float64(int)
|
||||
F_Z16int32_to_float64i : user_defined, called {
|
||||
fnm : "int32_to_float64" 'float64 int32_to_float64(int)';
|
||||
arg : ( dmaddr_:i int64_:r int32_:i );
|
||||
loc : ( LR[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// int float64_to_int32_round_to_zero(float64)
|
||||
F_Z30float64_to_int32_round_to_zeroy : user_defined, called {
|
||||
fnm : "float64_to_int32_round_to_zero" 'int float64_to_int32_round_to_zero(float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// float64 float64_sub(float64, float64)
|
||||
F_Z11float64_subyy : user_defined, called {
|
||||
fnm : "float64_sub" 'float64 float64_sub(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// float64 float64_mul(float64, float64)
|
||||
F_Z11float64_mulyy : user_defined, called {
|
||||
fnm : "float64_mul" 'float64 float64_mul(float64, float64)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// int float64_eq(float64, float64)
|
||||
F_Z10float64_eqyy : user_defined, called {
|
||||
fnm : "float64_eq" 'int float64_eq(float64, float64)';
|
||||
arg : ( dmaddr_:i int32_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] RA[0] AX[0] AX[1] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// double ff_pow(double, double)
|
||||
Fff_pow : user_defined, called {
|
||||
fnm : "ff_pow" 'double ff_pow(double, double)';
|
||||
arg : ( dmaddr_:i int64_:r int64_:i int64_:i );
|
||||
loc : ( LR[0] AX[0] AX[1] BX[0] );
|
||||
vac : ( srIM[0] );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
|
||||
F_Z4initP16SingleSignalPathS0_PdS1_iidddi : user_defined, called {
|
||||
fnm : "init" 'void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i dmaddr_:i int32_:i int32_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] A[1] A[2] A[3] RA[0] RA[1] AX[0] AX[1] BX[0] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( b=8 );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
|
||||
F_Z4calcP16SingleSignalPathS0_10OutputModePU17chess_storage_DMBVsS3_S3_ : user_defined, called {
|
||||
fnm : "calc" 'void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)';
|
||||
arg : ( dmaddr_:i dmaddr_:i dmaddr_:i int32_:i dmaddr_:i dmaddr_:i dmaddr_:i );
|
||||
loc : ( LR[0] A[0] A[1] RA[0] A[4] A[5] __spill_WDMA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_init_buffer(BufferPtr *, int *, int, int)
|
||||
F_Z15sig_init_bufferP9BufferPtrPiii : user_defined, called {
|
||||
fnm : "sig_init_buffer" 'int sig_init_buffer(BufferPtr *, int *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] A[1] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
|
||||
F_Z19sig_init_buffer_DMBPU17chess_storage_DMB12BufferPtrDMBPU17chess_storage_DMBiii : user_defined, called {
|
||||
fnm : "sig_init_buffer_DMB" 'int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i dmaddr_:i int32_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[4] A[5] RA[1] RB[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_cirular_buffer_ptr_increment(BufferPtr *, int)
|
||||
F_Z32sig_cirular_buffer_ptr_incrementP9BufferPtri : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_increment" 'void sig_cirular_buffer_ptr_increment(BufferPtr *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_cirular_buffer_ptr_increment_DMB(BufferPtrDMB *, int)
|
||||
F_Z36sig_cirular_buffer_ptr_increment_DMBP12BufferPtrDMBi : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_increment_DMB" 'void sig_cirular_buffer_ptr_increment_DMB(BufferPtrDMB *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_cirular_buffer_ptr_put_sample(BufferPtr *, int)
|
||||
F_Z33sig_cirular_buffer_ptr_put_sampleP9BufferPtri : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_put_sample" 'void sig_cirular_buffer_ptr_put_sample(BufferPtr *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)
|
||||
F_Z37sig_cirular_buffer_ptr_put_sample_DMBPU17chess_storage_DMB12BufferPtrDMBi : user_defined, called {
|
||||
fnm : "sig_cirular_buffer_ptr_put_sample_DMB" 'void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] A[4] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
|
||||
F_Z21sig_init_preemph_coefP16SingleSignalPathdddddi : user_defined, called {
|
||||
fnm : "sig_init_preemph_coef" 'void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int64_:i int64_:i int64_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] AX[1] BX[0] BX[1] __spill_LDMA[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_init_delay(SingleSignalPath *, int)
|
||||
F_Z14sig_init_delayP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_init_delay" 'int sig_init_delay(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// void sig_init_weight(SingleSignalPath *, double, int)
|
||||
F_Z15sig_init_weightP16SingleSignalPathdi : user_defined, called {
|
||||
fnm : "sig_init_weight" 'void sig_init_weight(SingleSignalPath *, double, int)';
|
||||
arg : ( dmaddr_:i dmaddr_:i int64_:i int32_:i );
|
||||
loc : ( LR[0] A[0] AX[0] RA[0] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 1 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_calc_biquad(SingleSignalPath *, int)
|
||||
F_Z15sig_calc_biquadP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_calc_biquad" 'int sig_calc_biquad(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
|
||||
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_delay_buffer_load_and_get" 'int sig_delay_buffer_load_and_get(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
// int sig_calc_weight(SingleSignalPath *, int)
|
||||
F_Z15sig_calc_weightP16SingleSignalPathi : user_defined, called {
|
||||
fnm : "sig_calc_weight" 'int sig_calc_weight(SingleSignalPath *, int)';
|
||||
arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
|
||||
loc : ( LR[0] RA[0] A[0] RA[1] );
|
||||
vac : ( srIM[0] );
|
||||
frm : ( );
|
||||
llv : 0 0 0 0 0 ;
|
||||
}
|
||||
|
||||
15
simulation/Release/chesswork/signal_path.objlist
Normal file
15
simulation/Release/chesswork/signal_path.objlist
Normal file
@@ -0,0 +1,15 @@
|
||||
"signal_path-154f66.o" 0
|
||||
"signal_path-f55921.o" 0
|
||||
"signal_path-fcd1fd.o" 0
|
||||
"signal_path-352f49.o" 0
|
||||
"signal_path-e110bc.o" 0
|
||||
"signal_path-e7968f.o" 0
|
||||
"signal_path-f8ba01.o" 0
|
||||
"signal_path-6fcf7f.o" 0
|
||||
"signal_path-d74ce2.o" 0
|
||||
"signal_path-d6dbe4.o" 0
|
||||
"signal_path-a30375.o" 0
|
||||
"signal_path-530a42.o" 0
|
||||
"signal_path-9c02ae.o" 0
|
||||
"signal_path-101f20.o" 0
|
||||
"signal_path.gvt.o" 0
|
||||
54
simulation/Release/chesswork/signal_path.tof
Normal file
54
simulation/Release/chesswork/signal_path.tof
Normal file
@@ -0,0 +1,54 @@
|
||||
|
||||
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Jan 15 13:02:45 2026
|
||||
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
|
||||
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32
|
||||
|
||||
|
||||
// per defined called function, table of invoked intrinsic functions (excluding built-in operators):
|
||||
|
||||
// int sig_init_buffer(BufferPtr *, int *, int, int)
|
||||
|
||||
// int sig_init_buffer_DMB(BufferPtrDMB chess_storage(DMB) *, int chess_storage(DMB) *, int, int)
|
||||
|
||||
// void sig_cirular_buffer_ptr_increment(BufferPtr *, int)
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
|
||||
// void sig_cirular_buffer_ptr_increment_DMB(BufferPtrDMB *, int)
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
|
||||
// void sig_cirular_buffer_ptr_put_sample(BufferPtr *, int)
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
|
||||
// void sig_cirular_buffer_ptr_put_sample_DMB(BufferPtrDMB chess_storage(DMB) *, int)
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
|
||||
// void sig_init_preemph_coef(SingleSignalPath *, double, double, double, double, double, int)
|
||||
|
||||
// int sig_init_delay(SingleSignalPath *, int)
|
||||
|
||||
// void sig_init_weight(SingleSignalPath *, double, int)
|
||||
|
||||
// int sig_calc_biquad(SingleSignalPath *, int)
|
||||
accum_t fract_mult(int, int)
|
||||
accum_t operator+(accum_t, accum_t)
|
||||
accum_t operator<<(accum_t, int)
|
||||
int rnd_saturate(accum_t)
|
||||
|
||||
// int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
|
||||
|
||||
// int sig_calc_weight(SingleSignalPath *, int)
|
||||
accum_t fract_mult(int, int)
|
||||
int rnd_saturate(accum_t)
|
||||
|
||||
// void init(SingleSignalPath *, SingleSignalPath *, double *, double *, int, int, double, double, double, int)
|
||||
|
||||
// void calc(SingleSignalPath *, SingleSignalPath *, OutputMode, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *, volatile int16_t chess_storage(DMB) *)
|
||||
accum_t to_accum(int)
|
||||
void *cyclic_add(void *, int, void *, int)
|
||||
accum_t fract_mult(int, int)
|
||||
accum_t operator+(accum_t, accum_t)
|
||||
int rnd_saturate(accum_t)
|
||||
void lldecompose(unsigned long long, int &, int &)
|
||||
unsigned long long llcompose(int, int)
|
||||
accum_t operator>>(accum_t, int)
|
||||
|
||||
Reference in New Issue
Block a user