C/DSP_Simulation
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This commit is contained in:
Patrick Hangl
2026-03-25 16:30:37 +01:00
parent 91e62d48e8
commit 165ed73a9a
71 changed files with 11028 additions and 11431 deletions
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simulation/Release/chesswork/main.gvt
+6 -6
View File
@@ -1,7 +1,7 @@
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Thu Mar 19 16:03:50 2026
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Wed Mar 25 16:19:32 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=16 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=48 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork main.c lpdsp32
[
1 : _imsk_var_ typ=uint15_ bnd=e sz=1 algn=1 stl=IMSK tref=uint15__IMSK
@@ -17,12 +17,12 @@
16 : _ZL14output_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
17 : _ZL14sample_pointer typ=int8_ bnd=f sz=4 algn=4 stl=DMA tref=__PDMB__sshort_DMA
18 : _ZL6sample typ=int8_ bnd=f sz=2 algn=2 stl=DMB tref=int16_t_DMB
19 : _ZL13__stradd574a4 typ=int8_ bnd=F sz=75 algn=1 stl=DMA tref=__A75__cchar_DMA
19 : _ZL13__str75097c0a typ=int8_ bnd=F sz=76 algn=1 stl=DMA tref=__A76__cchar_DMA
20 : _ZL13__str00f02b8f typ=int8_ bnd=F sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA
21 : _ZL13__str0fe4b1b6 typ=int8_ bnd=F sz=75 algn=1 stl=DMA tref=__A75__cchar_DMA
22 : _ZL13__stre6369ab8 typ=int8_ bnd=F sz=63 algn=1 stl=DMA tref=__A63__cchar_DMA
21 : _ZL13__strd718b91c typ=int8_ bnd=F sz=76 algn=1 stl=DMA tref=__A76__cchar_DMA
22 : _ZL13__str36a0c6ea typ=int8_ bnd=F sz=64 algn=1 stl=DMA tref=__A64__cchar_DMA
23 : _ZL13__str00f52cca typ=int8_ bnd=F sz=2 algn=1 stl=DMA tref=__A2__cchar_DMA
24 : _ZL13__strcf6f2fde typ=int8_ bnd=F sz=76 algn=1 stl=DMA tref=__A76__cchar_DMA
24 : _ZL13__str7a9ae62c typ=int8_ bnd=F sz=77 algn=1 stl=DMA tref=__A77__cchar_DMA
25 : _ZL13__str41232700 typ=int8_ bnd=F sz=3 algn=1 stl=DMA tref=__A3__cchar_DMA
26 : _ZL13__str2eb09b76 typ=int8_ bnd=F sz=4 algn=1 stl=DMA tref=__A4__cchar_DMA
]