
// File generated by noodle version X-2025.06#84ea4f0b1c#250602, Mon Feb  2 09:15:24 2026
// Copyright 2014-2025 Synopsys, Inc. All rights reserved.
// C:\Synopsys\ASIP Programmer\X-2025.06\win64\bin\WINbin\noodle.exe -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/isg -IC:/Users/phangl/OneDrive - MED-EL/Desktop/LPDSP32_Modell/lib/runtime/include -DBLOCK_LEN=1 -DMAX_FIR_COEFFS=64 -D__tct_patch__=0 -ilpdsp32_chess.h +Stof +wRelease/chesswork signal_processing/signal_path.c lpdsp32


/***
!!  int sig_delay_buffer_load_and_get(SingleSignalPath *, int)
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi : user_defined, called {
    fnm : "sig_delay_buffer_load_and_get" 'int sig_delay_buffer_load_and_get(SingleSignalPath *, int)';
    arg : ( dmaddr_:i int32_:r dmaddr_:i int32_:i );
    loc : ( LR[0] RA[0] A[0] RA[1] );
    vac : ( srIM[0] );
    frm : ( );
}
****
!!  void increment_buffer(BufferPtr *, int)
F_Z16increment_bufferP9BufferPtri : user_defined, called {
    fnm : "increment_buffer" 'void increment_buffer(BufferPtr *, int)';
    arg : ( dmaddr_:i dmaddr_:i int32_:i );
    loc : ( LR[0] A[0] RA[0] );
    vac : ( srIM[0] );
    llv : 0 0 0 0 0 ;
}
***/

[
    0 : _Z29sig_delay_buffer_load_and_getP16SingleSignalPathi typ=uint20_ bnd=e stl=PM tref=__sint_____PSingleSignalPath___sint___2
   11 : __M_WDMA typ=int32_ bnd=d stl=WDMA
   26 : __R_SP typ=dmaddr_ bnd=d stl=SP
   29 : __vola typ=uint20_ bnd=b stl=PM
   32 : __extDM typ=int8_ bnd=b stl=DM
   33 : __extPM typ=uint20_ bnd=b stl=PM
   34 : __sp typ=dmaddr_ bnd=b stl=SP
   35 : __extDM_SingleSignalPath typ=int8_ bnd=b stl=DM
   36 : __extDM_SingleSignalPath_delay_buffer typ=int8_ bnd=b stl=DM
   37 : __extDM_BufferPtr typ=int8_ bnd=b stl=DM
   38 : __extDM_SingleSignalPath_delay_buffer_buffer_len typ=int8_ bnd=b stl=DM
   39 : __extDM_int32_ typ=int8_ bnd=b stl=DM
   40 : __extDM_SingleSignalPath_delay_buffer_ptr_current typ=int8_ bnd=b stl=DM
   41 : __extDM___PDMint32_ typ=int8_ bnd=b stl=DM
   42 : __extDM_void typ=int8_ bnd=b stl=DM
   43 : __extPM_void typ=uint20_ bnd=b stl=PM
   44 : __rd___sp typ=dmaddr_ bnd=m
   45 : __ct_0 typ=uint1_ val=0f bnd=m
   46 : __la typ=dmaddr_ bnd=p tref=dmaddr___
   47 : __rt typ=int32_ bnd=p tref=__sint__
   48 : signal typ=dmaddr_ bnd=p tref=__PSingleSignalPath__
   49 : x typ=int32_ bnd=p tref=__sint__
   57 : __ct_0 typ=int32_ val=0f bnd=m
   60 : __fch___extDM_SingleSignalPath_delay_buffer_buffer_len typ=int32_ bnd=m
   63 : __tmp typ=bool bnd=m
   70 : __fch___extDM_SingleSignalPath_delay_buffer_ptr_current typ=dmaddr_ bnd=m
   81 : __tmp typ=dmaddr_ bnd=m
   82 : __ct_1 typ=int32_ val=1f bnd=m
   83 : __ct typ=int32_ bnd=m
   84 : _Z16increment_bufferP9BufferPtri typ=dmaddr_ val=0r bnd=m
   86 : __link typ=dmaddr_ bnd=m
  100 : __rt typ=dmaddr_ bnd=m tref=__Pvoid__
  124 : __ct_0S0 typ=int18_ val=0S0 bnd=m
  125 : __ct_116 typ=int18_ val=116f bnd=m
  128 : __ct_8 typ=int18_ val=8f bnd=m
  130 : __ct_0s0 typ=int18_ val=0s0 bnd=m
  134 : __tmp typ=uint3_ bnd=m
  144 : __either typ=bool bnd=m
  145 : __trgt typ=int10_ val=0j bnd=m
  146 : __trgt typ=int10_ val=0j bnd=m
]
F_Z29sig_delay_buffer_load_and_getP16SingleSignalPathi {
    #228 off=0
    (__M_WDMA.9 var=11) st_def ()  <18>;
    (__R_SP.24 var=26) st_def ()  <48>;
    (__vola.27 var=29) source ()  <51>;
    (__extDM.30 var=32) source ()  <54>;
    (__extPM.31 var=33) source ()  <55>;
    (__sp.32 var=34) source ()  <56>;
    (__extDM_SingleSignalPath.33 var=35) source ()  <57>;
    (__extDM_SingleSignalPath_delay_buffer.34 var=36) source ()  <58>;
    (__extDM_BufferPtr.35 var=37) source ()  <59>;
    (__extDM_SingleSignalPath_delay_buffer_buffer_len.36 var=38) source ()  <60>;
    (__extDM_int32_.37 var=39) source ()  <61>;
    (__extDM_SingleSignalPath_delay_buffer_ptr_current.38 var=40) source ()  <62>;
    (__extDM___PDMint32_.39 var=41) source ()  <63>;
    (__extDM_void.40 var=42) source ()  <64>;
    (__extPM_void.41 var=43) source ()  <65>;
    (__ct_0.43 var=45) const ()  <67>;
    (__la.45 var=46 stl=LR off=0) inp ()  <69>;
    (__la.46 var=46) deassign (__la.45)  <70>;
    (signal.49 var=48 stl=A off=0) inp ()  <73>;
    (signal.50 var=48) deassign (signal.49)  <74>;
    (x.52 var=49 stl=RA off=1) inp ()  <76>;
    (x.53 var=49) deassign (x.52)  <77>;
    (__rd___sp.55 var=44) rd_res_reg (__R_SP.24 __sp.32)  <79>;
    (__R_SP.59 var=26 __sp.60 var=34) wr_res_reg (__rt.195 __sp.32)  <83>;
    (__ct_0.65 var=57) const ()  <89>;
    (__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 var=60) load (__M_WDMA.9 __rt.217 __extDM_SingleSignalPath_delay_buffer_buffer_len.36)  <92>;
    (__rt.195 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.55 __ct_0S0.296)  <259>;
    (__rt.217 var=100) __Pvoid__pl___Pvoid_int18_ (signal.50 __ct_116.297)  <287>;
    (__ct_0S0.296 var=124) const ()  <399>;
    (__ct_116.297 var=125) const ()  <401>;
    (__tmp.305 var=134) uint3__cmp_int72__int72_ (__fch___extDM_SingleSignalPath_delay_buffer_buffer_len.68 __ct_0.65)  <416>;
    (__tmp.306 var=63) bool_equal_uint3_ (__tmp.305)  <417>;
    (__trgt.314 var=145) const ()  <457>;
    () void_jump_bool_int10_ (__tmp.306 __trgt.314)  <458>;
    (__either.315 var=144) undefined ()  <459>;
    if {
        {
            () if_expr (__either.315)  <116>;
        } #5
        {
        } #6 off=4
        {
            #157 off=1
            (__fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 var=70) load (__M_WDMA.9 __rt.239 __extDM_SingleSignalPath_delay_buffer_ptr_current.38)  <124>;
            (__rt.100 var=47) load (__M_WDMA.9 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37)  <125>;
            (__M_WDMA.108 var=11 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 var=38 __extDM_int32_.110 var=39) store (x.53 __fch___extDM_SingleSignalPath_delay_buffer_ptr_current.99 __extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_int32_.37)  <133>;
            (__ct_1.115 var=82) const ()  <138>;
            (_Z16increment_bufferP9BufferPtri.118 var=84) const ()  <141>;
            (__link.120 var=86) dmaddr__call_dmaddr_ (_Z16increment_bufferP9BufferPtri.118)  <143>;
            (__rt.239 var=100) __Pvoid__pl___Pvoid_int18_ (__rt.217 __ct_8.300)  <315>;
            (__rt.283 var=100) __Pvoid__mi___Pvoid_int18_ (__rt.239 __ct_8.300)  <371>;
            (__ct_8.300 var=128) const ()  <407>;
            call {
                (__tmp.114 var=81 stl=A off=0) assign (__rt.283)  <137>;
                (__ct.117 var=83 stl=RA off=0) assign (__ct_1.115)  <140>;
                (__link.121 var=86 stl=LR off=0) assign (__link.120)  <144>;
                (__extDM.122 var=32 __extDM_BufferPtr.123 var=37 __extDM_SingleSignalPath.124 var=35 __extDM_SingleSignalPath_delay_buffer.125 var=36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126 var=38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127 var=40 __extDM___PDMint32_.128 var=41 __extDM_int32_.129 var=39 __extDM_void.130 var=42 __extPM.131 var=33 __extPM_void.132 var=43 __vola.133 var=29) F_Z16increment_bufferP9BufferPtri (__link.121 __tmp.114 __ct.117 __extDM.30 __extDM_BufferPtr.35 __extDM_SingleSignalPath.33 __extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer_buffer_len.109 __extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM___PDMint32_.39 __extDM_int32_.110 __extDM_void.40 __extPM.31 __extPM_void.41 __vola.27)  <145>;
            } #9 off=2
            #231 off=3
            (__trgt.316 var=146) const ()  <460>;
            () void_jump_int10_ (__trgt.316)  <461>;
        } #7
        {
            (__vola.134 var=29) merge (__vola.27 __vola.133)  <146>;
            (__extDM.135 var=32) merge (__extDM.30 __extDM.122)  <147>;
            (__extPM.136 var=33) merge (__extPM.31 __extPM.131)  <148>;
            (__extDM_SingleSignalPath.137 var=35) merge (__extDM_SingleSignalPath.33 __extDM_SingleSignalPath.124)  <149>;
            (__extDM_SingleSignalPath_delay_buffer.138 var=36) merge (__extDM_SingleSignalPath_delay_buffer.34 __extDM_SingleSignalPath_delay_buffer.125)  <150>;
            (__extDM_BufferPtr.139 var=37) merge (__extDM_BufferPtr.35 __extDM_BufferPtr.123)  <151>;
            (__extDM_SingleSignalPath_delay_buffer_buffer_len.140 var=38) merge (__extDM_SingleSignalPath_delay_buffer_buffer_len.36 __extDM_SingleSignalPath_delay_buffer_buffer_len.126)  <152>;
            (__extDM_int32_.141 var=39) merge (__extDM_int32_.37 __extDM_int32_.129)  <153>;
            (__extDM_SingleSignalPath_delay_buffer_ptr_current.142 var=40) merge (__extDM_SingleSignalPath_delay_buffer_ptr_current.38 __extDM_SingleSignalPath_delay_buffer_ptr_current.127)  <154>;
            (__extDM___PDMint32_.143 var=41) merge (__extDM___PDMint32_.39 __extDM___PDMint32_.128)  <155>;
            (__extDM_void.144 var=42) merge (__extDM_void.40 __extDM_void.130)  <156>;
            (__extPM_void.145 var=43) merge (__extPM_void.41 __extPM_void.132)  <157>;
            (__rt.146 var=47) merge (x.53 __rt.100)  <158>;
        } #10
    } #4
    #12 off=5 nxt=-2
    (__rd___sp.148 var=44) rd_res_reg (__R_SP.24 __sp.60)  <160>;
    (__R_SP.152 var=26 __sp.153 var=34) wr_res_reg (__rt.261 __sp.60)  <164>;
    () void_ret_dmaddr_ (__la.46)  <165>;
    (__rt.154 var=47 stl=RA off=0) assign (__rt.146)  <166>;
    () out (__rt.154)  <167>;
    () sink (__vola.134)  <168>;
    () sink (__extDM.135)  <171>;
    () sink (__extPM.136)  <172>;
    () sink (__sp.153)  <173>;
    () sink (__extDM_SingleSignalPath.137)  <174>;
    () sink (__extDM_SingleSignalPath_delay_buffer.138)  <175>;
    () sink (__extDM_BufferPtr.139)  <176>;
    () sink (__extDM_SingleSignalPath_delay_buffer_buffer_len.140)  <177>;
    () sink (__extDM_int32_.141)  <178>;
    () sink (__extDM_SingleSignalPath_delay_buffer_ptr_current.142)  <179>;
    () sink (__extDM___PDMint32_.143)  <180>;
    () sink (__extDM_void.144)  <181>;
    () sink (__extPM_void.145)  <182>;
    () sink (__ct_0.43)  <183>;
    (__rt.261 var=100) __Pvoid__pl___Pvoid_int18_ (__rd___sp.148 __ct_0s0.302)  <343>;
    (__ct_0s0.302 var=130) const ()  <411>;
} #0
0 : 'signal_processing\\signal_path.c';
----------
0 : (0,201:0,0);
4 : (0,202:4,1);
6 : (0,202:46,2);
7 : (0,203:8,5);
9 : (0,207:4,8);
12 : (0,208:4,13);
157 : (0,207:4,8);
228 : (0,202:40,1);
----------
79 : (0,201:4,0);
83 : (0,201:4,0);
89 : (0,202:28,0);
92 : (0,202:28,1);
116 : (0,202:4,1);
124 : (0,205:35,6);
125 : (0,205:14,6);
133 : (0,206:4,7);
137 : (0,207:28,0);
138 : (0,207:44,0);
140 : (0,207:44,0);
143 : (0,207:4,8);
144 : (0,207:4,0);
145 : (0,207:4,8);
146 : (0,202:4,12);
147 : (0,202:4,12);
148 : (0,202:4,12);
149 : (0,202:4,12);
150 : (0,202:4,12);
151 : (0,202:4,12);
152 : (0,202:4,12);
153 : (0,202:4,12);
154 : (0,202:4,12);
155 : (0,202:4,12);
156 : (0,202:4,12);
157 : (0,202:4,12);
158 : (0,202:4,12);
160 : (0,208:4,0);
164 : (0,208:4,13);
165 : (0,208:4,13);
166 : (0,208:4,0);
259 : (0,201:4,0);
287 : (0,202:14,1);
315 : (0,205:35,6);
343 : (0,208:4,0);
371 : (0,202:14,0);
399 : (0,201:4,0);
401 : (0,202:14,0);
407 : (0,205:35,0);
411 : (0,208:4,0);
416 : (0,202:40,1);
417 : (0,202:40,1);
458 : (0,202:4,1);

