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This commit is contained in:
Patrick Hangl
154
main.c
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154
main.c
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//#define SIMULATE
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#ifdef SIMULATE
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#include <stdio.h>
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#endif
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#define BLOCK_LEN 1 // define block length for processing - currently only 1 is supported
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#include <stdint.h>
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#include "signalProcessing/include/signal_path.h"
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// Register und Bitmasken für Interrupts zwischen ARM und LPDSP Prozessor
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#define CSS_CMD 0xC00004
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#define CSS_CMD_0 (1<<0)
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#define CSS_CMD_1 (1<<1)
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// Shared Memory von ARM und DSP definieren
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#define INPUT_PORT0_ADD 0x800000 // Feste Adressen für Eingangsdaten im Shared Memory
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//#define INPUT_PORT1_ADD INPUT_PORT0_ADD + 2 //DMB - warum auskommentiert?
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#define OUTPUT_PORT_ADD (INPUT_PORT0_ADD + 16) // Feste Adressen für Ausgangsdatensdaten im Shared Memory, 16 Byte von Eingangsadresse Weg (PS: 2* for 2 channels)
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//Chess Compiler spezifisch: Interrupt-Register festlegen um ARM zu kontaktieren nach fertiger Berechnung (PS: Define the interrupt register to notify the ARM of a completed operation)
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volatile static unsigned char chess_storage(DMIO:CSS_CMD) CssCmdGen;
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// Interrupt-Flag, welche von ARM gesetzt wird, wenn eine Berechnung gewünscht ist
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static volatile int actionRequired;
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// Structs anlegen für die Signalpfade - hier werden Konfigurationen abgelegt(signal_path.h)
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static SingleSignalPath cSensorSignal;
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static SingleSignalPath accSensorSignal;
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// Umschaltung zwischen sampleweiser und blockweiser Verarbeitung
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// Sampleweise Verarbeitung: Adresse aus Shared Memory wird direkt verwendet
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// Blockweise Verarbeitung: Blöcke kopiert und verarbeitet? Offensichtlicch nicht genutzt bisher
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#if BLOCK_LEN == 1
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static volatile int16_t chess_storage(DMB:INPUT_PORT0_ADD) intputPort[4]; //TODO: if BLOCK_LEN >1 is used, the data is interleaved: ch0ch1, ch0ch1 .... chess_storage(DMA % alignof(int)) ?
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//static volatile int16_t chess_storage(DMB:INPUT_PORT1_ADD) intputPort1[BLOCK_LEN];
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static volatile int16_t chess_storage(DMB:OUTPUT_PORT_ADD) outputPort[4];
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static volatile int16_t chess_storage(DMB) *inPtr0;
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static volatile int16_t chess_storage(DMB) *inPtr1;
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static volatile int16_t chess_storage(DMB) *outPtr;
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static volatile int16_t chess_storage(DMB) sample;
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static volatile int16_t chess_storage(DMB) *sample_ptr;
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#else
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// Int-Array für Blockverarbeitung im Shared Memory DMA anlegen (Eingabe)
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static int16_t chess_storage(DMA) intputPort[BLOCK_LEN]; //chess_storage(DMA:INPUT_PORT_ADD) TODO: volatile? chess_storage(DMA % alignof(int))
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//static int16_t chess_storage(DMA) intputPort1[BLOCK_LEN]; //chess_storage(DMA:INPUT_PORT_ADD)
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// Int-Array für Blockverarbeitung im Shared Memory DMA anlegen (Ausgabe)
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static int16_t chess_storage(DMB) outputPort[BLOCK_LEN]; // chess_storage(DMB:OUTPUT_PORT_ADD) TODO: determine output port add
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#endif
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//void isr0() ist eine Interrupt Service Routine Funktion, welche als C Funktion deklariert wird
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// property (isr) ist Chess Compiler spezifisch und kennzeichnet eine Funktion als Interrupt Service Routine
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//wird Interrupt getriggert, wird actionRequired auf 1 gesetzt - etwas muss dannpassieren
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extern "C" void isr0() property (isr) {
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actionRequired = 1;
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}
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#ifdef __chess__
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extern "C"
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#endif
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int main(void) {
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// Enum, welcher den Ausgabemodus definiert - wird in calc()-Funktion verwendet
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static OutputMode mode = OUTPUT_MODE_FIR_LMS;
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// Initialize the signal path
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// Initialize the csensor signal subpath
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// Instanciate the signal path state structs
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// Deactivate preemphasis filter by initializing with coefficients {1., 0., 0., 0., 0.}
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// biquad filter coefficients - off
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double b0[5]={0.75, 0., 0., 0., 0.};
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double b1[5]={0.75, 0., 0., 0., 0.};
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int N_lms_fir_coeffs = MAX_FIR_COEFFS; // always test with max coeffs
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//init-Funktion aufrufen
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init(
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&cSensorSignal, &accSensorSignal,
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//&ptr_fir_lms_delay_line, &ptr_fir_lms_coeffs,
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b0,
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b1,
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2, // sample delayS
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2,
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0.9, // weight
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0.9,
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0.01, // lms learning rate
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N_lms_fir_coeffs // Numer of lms fir coefficients
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);
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if (mode == OUTPUT_MODE_FIR){ //FIR filter mit fixen coeffizienten wenn nicht adaptiv
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for (int i=0; i<N_lms_fir_coeffs; i++){
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#ifdef LPDSP16
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ptr_fir_lms_coeffs.ptr_start[i] = ((pow(2, 15)-1) /N_lms_fir_coeffs);
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#else
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ptr_fir_lms_coeffs.ptr_start[i] = ((pow(2, 31)-1) /N_lms_fir_coeffs);
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#endif
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}
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}
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#ifdef SIMULATE // use the simulator with file I/O
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FILE *fp1 = fopen("./test/testdata/input/chirp_disturber.txt", "r");
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FILE *fp2 = fopen("./test/testdata/input/disturber.txt", "r");
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FILE *fp3 = fopen("./test/testdata/output/out_simulated.txt", "w");
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int d0, d1;
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while (!(feof(fp1) || feof(fp2))){
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for (int i=0; i<BLOCK_LEN; i++){
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fscanf(fp1, "%d", &d0); //load blocks
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fscanf(fp2, "%d", &d1);
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intputPort[i] = (int16_t) d0;
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intputPort[i+1] = (int16_t) d1;
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}
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calc(
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&cSensorSignal, &accSensorSignal,
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//&ptr_fir_lms_delay_line, &ptr_fir_lms_coeffs,
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mode,
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&intputPort[0],
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&intputPort[1],
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outputPort
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);
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for (int i=0; i<BLOCK_LEN; i++){
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fprintf(fp3, "%d\n", outputPort[i]);
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}
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}
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fclose(fp1);
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fclose(fp2);
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fclose(fp3);
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#else // how its done in hw
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// enable the interrupts
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enable_interrupts();
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outPtr = &outputPort[1]; // start with second half of buffer
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sample_ptr = &sample;
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/*Signalprocessing, called by an interrupt*/
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actionRequired = 0;
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while (1){
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CssCmdGen = CSS_CMD_1; // indicate going to sleep to the cm3
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core_halt();
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if (actionRequired == 1) {
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CssCmdGen = CSS_CMD_0; // indicate wakeup to the cm3
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actionRequired = 0;
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outPtr = cyclic_add(outPtr, 2, outputPort, 4);
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*outPtr = *sample_ptr;
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calc(&cSensorSignal, &accSensorSignal, mode, &intputPort[1], &intputPort[0], sample_ptr);
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}
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}
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#endif
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}
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